1 /* 2 * QEMU PIIX PCI ISA Bridge Emulation 3 * 4 * Copyright (c) 2006 Fabrice Bellard 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a copy 7 * of this software and associated documentation files (the "Software"), to deal 8 * in the Software without restriction, including without limitation the rights 9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 10 * copies of the Software, and to permit persons to whom the Software is 11 * furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice shall be included in 14 * all copies or substantial portions of the Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN 22 * THE SOFTWARE. 23 */ 24 25 #include "qemu/osdep.h" 26 #include "qemu/range.h" 27 #include "hw/southbridge/piix.h" 28 #include "hw/irq.h" 29 #include "hw/isa/isa.h" 30 #include "hw/xen/xen.h" 31 #include "sysemu/xen.h" 32 #include "sysemu/reset.h" 33 #include "sysemu/runstate.h" 34 #include "migration/vmstate.h" 35 #include "hw/acpi/acpi_aml_interface.h" 36 37 #define XEN_PIIX_NUM_PIRQS 128ULL 38 39 static void piix3_set_irq_pic(PIIX3State *piix3, int pic_irq) 40 { 41 qemu_set_irq(piix3->pic[pic_irq], 42 !!(piix3->pic_levels & 43 (((1ULL << PIIX_NUM_PIRQS) - 1) << 44 (pic_irq * PIIX_NUM_PIRQS)))); 45 } 46 47 static void piix3_set_irq_level_internal(PIIX3State *piix3, int pirq, int level) 48 { 49 int pic_irq; 50 uint64_t mask; 51 52 pic_irq = piix3->dev.config[PIIX_PIRQCA + pirq]; 53 if (pic_irq >= PIIX_NUM_PIC_IRQS) { 54 return; 55 } 56 57 mask = 1ULL << ((pic_irq * PIIX_NUM_PIRQS) + pirq); 58 piix3->pic_levels &= ~mask; 59 piix3->pic_levels |= mask * !!level; 60 } 61 62 static void piix3_set_irq_level(PIIX3State *piix3, int pirq, int level) 63 { 64 int pic_irq; 65 66 pic_irq = piix3->dev.config[PIIX_PIRQCA + pirq]; 67 if (pic_irq >= PIIX_NUM_PIC_IRQS) { 68 return; 69 } 70 71 piix3_set_irq_level_internal(piix3, pirq, level); 72 73 piix3_set_irq_pic(piix3, pic_irq); 74 } 75 76 static void piix3_set_irq(void *opaque, int pirq, int level) 77 { 78 PIIX3State *piix3 = opaque; 79 piix3_set_irq_level(piix3, pirq, level); 80 } 81 82 /* 83 * Return the global irq number corresponding to a given device irq 84 * pin. We could also use the bus number to have a more precise mapping. 85 */ 86 static int pci_slot_get_pirq(PCIDevice *pci_dev, int pci_intx) 87 { 88 int slot_addend; 89 slot_addend = PCI_SLOT(pci_dev->devfn) - 1; 90 return (pci_intx + slot_addend) & 3; 91 } 92 93 static PCIINTxRoute piix3_route_intx_pin_to_irq(void *opaque, int pin) 94 { 95 PIIX3State *piix3 = opaque; 96 int irq = piix3->dev.config[PIIX_PIRQCA + pin]; 97 PCIINTxRoute route; 98 99 if (irq < PIIX_NUM_PIC_IRQS) { 100 route.mode = PCI_INTX_ENABLED; 101 route.irq = irq; 102 } else { 103 route.mode = PCI_INTX_DISABLED; 104 route.irq = -1; 105 } 106 return route; 107 } 108 109 /* irq routing is changed. so rebuild bitmap */ 110 static void piix3_update_irq_levels(PIIX3State *piix3) 111 { 112 PCIBus *bus = pci_get_bus(&piix3->dev); 113 int pirq; 114 115 piix3->pic_levels = 0; 116 for (pirq = 0; pirq < PIIX_NUM_PIRQS; pirq++) { 117 piix3_set_irq_level(piix3, pirq, pci_bus_get_irq_level(bus, pirq)); 118 } 119 } 120 121 static void piix3_write_config(PCIDevice *dev, 122 uint32_t address, uint32_t val, int len) 123 { 124 pci_default_write_config(dev, address, val, len); 125 if (ranges_overlap(address, len, PIIX_PIRQCA, 4)) { 126 PIIX3State *piix3 = PIIX3_PCI_DEVICE(dev); 127 int pic_irq; 128 129 pci_bus_fire_intx_routing_notifier(pci_get_bus(&piix3->dev)); 130 piix3_update_irq_levels(piix3); 131 for (pic_irq = 0; pic_irq < PIIX_NUM_PIC_IRQS; pic_irq++) { 132 piix3_set_irq_pic(piix3, pic_irq); 133 } 134 } 135 } 136 137 static void piix3_write_config_xen(PCIDevice *dev, 138 uint32_t address, uint32_t val, int len) 139 { 140 xen_piix_pci_write_config_client(address, val, len); 141 piix3_write_config(dev, address, val, len); 142 } 143 144 static void piix3_reset(void *opaque) 145 { 146 PIIX3State *d = opaque; 147 uint8_t *pci_conf = d->dev.config; 148 149 pci_conf[0x04] = 0x07; /* master, memory and I/O */ 150 pci_conf[0x05] = 0x00; 151 pci_conf[0x06] = 0x00; 152 pci_conf[0x07] = 0x02; /* PCI_status_devsel_medium */ 153 pci_conf[0x4c] = 0x4d; 154 pci_conf[0x4e] = 0x03; 155 pci_conf[0x4f] = 0x00; 156 pci_conf[0x60] = 0x80; 157 pci_conf[0x61] = 0x80; 158 pci_conf[0x62] = 0x80; 159 pci_conf[0x63] = 0x80; 160 pci_conf[0x69] = 0x02; 161 pci_conf[0x70] = 0x80; 162 pci_conf[0x76] = 0x0c; 163 pci_conf[0x77] = 0x0c; 164 pci_conf[0x78] = 0x02; 165 pci_conf[0x79] = 0x00; 166 pci_conf[0x80] = 0x00; 167 pci_conf[0x82] = 0x00; 168 pci_conf[0xa0] = 0x08; 169 pci_conf[0xa2] = 0x00; 170 pci_conf[0xa3] = 0x00; 171 pci_conf[0xa4] = 0x00; 172 pci_conf[0xa5] = 0x00; 173 pci_conf[0xa6] = 0x00; 174 pci_conf[0xa7] = 0x00; 175 pci_conf[0xa8] = 0x0f; 176 pci_conf[0xaa] = 0x00; 177 pci_conf[0xab] = 0x00; 178 pci_conf[0xac] = 0x00; 179 pci_conf[0xae] = 0x00; 180 181 d->pic_levels = 0; 182 d->rcr = 0; 183 } 184 185 static int piix3_post_load(void *opaque, int version_id) 186 { 187 PIIX3State *piix3 = opaque; 188 int pirq; 189 190 /* 191 * Because the i8259 has not been deserialized yet, qemu_irq_raise 192 * might bring the system to a different state than the saved one; 193 * for example, the interrupt could be masked but the i8259 would 194 * not know that yet and would trigger an interrupt in the CPU. 195 * 196 * Here, we update irq levels without raising the interrupt. 197 * Interrupt state will be deserialized separately through the i8259. 198 */ 199 piix3->pic_levels = 0; 200 for (pirq = 0; pirq < PIIX_NUM_PIRQS; pirq++) { 201 piix3_set_irq_level_internal(piix3, pirq, 202 pci_bus_get_irq_level(pci_get_bus(&piix3->dev), pirq)); 203 } 204 return 0; 205 } 206 207 static int piix3_pre_save(void *opaque) 208 { 209 int i; 210 PIIX3State *piix3 = opaque; 211 212 for (i = 0; i < ARRAY_SIZE(piix3->pci_irq_levels_vmstate); i++) { 213 piix3->pci_irq_levels_vmstate[i] = 214 pci_bus_get_irq_level(pci_get_bus(&piix3->dev), i); 215 } 216 217 return 0; 218 } 219 220 static bool piix3_rcr_needed(void *opaque) 221 { 222 PIIX3State *piix3 = opaque; 223 224 return (piix3->rcr != 0); 225 } 226 227 static const VMStateDescription vmstate_piix3_rcr = { 228 .name = "PIIX3/rcr", 229 .version_id = 1, 230 .minimum_version_id = 1, 231 .needed = piix3_rcr_needed, 232 .fields = (VMStateField[]) { 233 VMSTATE_UINT8(rcr, PIIX3State), 234 VMSTATE_END_OF_LIST() 235 } 236 }; 237 238 static const VMStateDescription vmstate_piix3 = { 239 .name = "PIIX3", 240 .version_id = 3, 241 .minimum_version_id = 2, 242 .post_load = piix3_post_load, 243 .pre_save = piix3_pre_save, 244 .fields = (VMStateField[]) { 245 VMSTATE_PCI_DEVICE(dev, PIIX3State), 246 VMSTATE_INT32_ARRAY_V(pci_irq_levels_vmstate, PIIX3State, 247 PIIX_NUM_PIRQS, 3), 248 VMSTATE_END_OF_LIST() 249 }, 250 .subsections = (const VMStateDescription*[]) { 251 &vmstate_piix3_rcr, 252 NULL 253 } 254 }; 255 256 257 static void rcr_write(void *opaque, hwaddr addr, uint64_t val, unsigned len) 258 { 259 PIIX3State *d = opaque; 260 261 if (val & 4) { 262 qemu_system_reset_request(SHUTDOWN_CAUSE_GUEST_RESET); 263 return; 264 } 265 d->rcr = val & 2; /* keep System Reset type only */ 266 } 267 268 static uint64_t rcr_read(void *opaque, hwaddr addr, unsigned len) 269 { 270 PIIX3State *d = opaque; 271 272 return d->rcr; 273 } 274 275 static const MemoryRegionOps rcr_ops = { 276 .read = rcr_read, 277 .write = rcr_write, 278 .endianness = DEVICE_LITTLE_ENDIAN 279 }; 280 281 static void piix3_realize(PCIDevice *dev, Error **errp) 282 { 283 PIIX3State *d = PIIX3_PCI_DEVICE(dev); 284 285 if (!isa_bus_new(DEVICE(d), get_system_memory(), 286 pci_address_space_io(dev), errp)) { 287 return; 288 } 289 290 memory_region_init_io(&d->rcr_mem, OBJECT(dev), &rcr_ops, d, 291 "piix3-reset-control", 1); 292 memory_region_add_subregion_overlap(pci_address_space_io(dev), 293 PIIX_RCR_IOPORT, &d->rcr_mem, 1); 294 295 qemu_register_reset(piix3_reset, d); 296 } 297 298 static void build_pci_isa_aml(AcpiDevAmlIf *adev, Aml *scope) 299 { 300 BusChild *kid; 301 BusState *bus = qdev_get_child_bus(DEVICE(adev), "isa.0"); 302 303 /* PIIX PCI to ISA irq remapping */ 304 aml_append(scope, aml_operation_region("P40C", AML_PCI_CONFIG, 305 aml_int(0x60), 0x04)); 306 QTAILQ_FOREACH(kid, &bus->children, sibling) { 307 call_dev_aml_func(DEVICE(kid->child), scope); 308 } 309 } 310 311 static void pci_piix3_class_init(ObjectClass *klass, void *data) 312 { 313 DeviceClass *dc = DEVICE_CLASS(klass); 314 PCIDeviceClass *k = PCI_DEVICE_CLASS(klass); 315 AcpiDevAmlIfClass *adevc = ACPI_DEV_AML_IF_CLASS(klass); 316 317 dc->desc = "ISA bridge"; 318 dc->vmsd = &vmstate_piix3; 319 dc->hotpluggable = false; 320 k->realize = piix3_realize; 321 k->vendor_id = PCI_VENDOR_ID_INTEL; 322 /* 82371SB PIIX3 PCI-to-ISA bridge (Step A1) */ 323 k->device_id = PCI_DEVICE_ID_INTEL_82371SB_0; 324 k->class_id = PCI_CLASS_BRIDGE_ISA; 325 /* 326 * Reason: part of PIIX3 southbridge, needs to be wired up by 327 * pc_piix.c's pc_init1() 328 */ 329 dc->user_creatable = false; 330 adevc->build_dev_aml = build_pci_isa_aml; 331 } 332 333 static const TypeInfo piix3_pci_type_info = { 334 .name = TYPE_PIIX3_PCI_DEVICE, 335 .parent = TYPE_PCI_DEVICE, 336 .instance_size = sizeof(PIIX3State), 337 .abstract = true, 338 .class_init = pci_piix3_class_init, 339 .interfaces = (InterfaceInfo[]) { 340 { INTERFACE_CONVENTIONAL_PCI_DEVICE }, 341 { TYPE_ACPI_DEV_AML_IF }, 342 { }, 343 }, 344 }; 345 346 static void piix3_class_init(ObjectClass *klass, void *data) 347 { 348 PCIDeviceClass *k = PCI_DEVICE_CLASS(klass); 349 350 k->config_write = piix3_write_config; 351 } 352 353 static const TypeInfo piix3_info = { 354 .name = TYPE_PIIX3_DEVICE, 355 .parent = TYPE_PIIX3_PCI_DEVICE, 356 .class_init = piix3_class_init, 357 }; 358 359 static void piix3_xen_class_init(ObjectClass *klass, void *data) 360 { 361 PCIDeviceClass *k = PCI_DEVICE_CLASS(klass); 362 363 k->config_write = piix3_write_config_xen; 364 }; 365 366 static const TypeInfo piix3_xen_info = { 367 .name = TYPE_PIIX3_XEN_DEVICE, 368 .parent = TYPE_PIIX3_PCI_DEVICE, 369 .class_init = piix3_xen_class_init, 370 }; 371 372 static void piix3_register_types(void) 373 { 374 type_register_static(&piix3_pci_type_info); 375 type_register_static(&piix3_info); 376 type_register_static(&piix3_xen_info); 377 } 378 379 type_init(piix3_register_types) 380 381 PIIX3State *piix3_create(PCIBus *pci_bus, ISABus **isa_bus) 382 { 383 PIIX3State *piix3; 384 PCIDevice *pci_dev; 385 386 /* 387 * Xen supports additional interrupt routes from the PCI devices to 388 * the IOAPIC: the four pins of each PCI device on the bus are also 389 * connected to the IOAPIC directly. 390 * These additional routes can be discovered through ACPI. 391 */ 392 if (xen_enabled()) { 393 pci_dev = pci_create_simple_multifunction(pci_bus, -1, true, 394 TYPE_PIIX3_XEN_DEVICE); 395 piix3 = PIIX3_PCI_DEVICE(pci_dev); 396 pci_bus_irqs(pci_bus, xen_piix3_set_irq, xen_pci_slot_get_pirq, 397 piix3, XEN_PIIX_NUM_PIRQS); 398 } else { 399 pci_dev = pci_create_simple_multifunction(pci_bus, -1, true, 400 TYPE_PIIX3_DEVICE); 401 piix3 = PIIX3_PCI_DEVICE(pci_dev); 402 pci_bus_irqs(pci_bus, piix3_set_irq, pci_slot_get_pirq, 403 piix3, PIIX_NUM_PIRQS); 404 pci_bus_set_route_irq_fn(pci_bus, piix3_route_intx_pin_to_irq); 405 } 406 *isa_bus = ISA_BUS(qdev_get_child_bus(DEVICE(piix3), "isa.0")); 407 408 return piix3; 409 } 410