1 /* 2 * QEMU PIIX PCI ISA Bridge Emulation 3 * 4 * Copyright (c) 2006 Fabrice Bellard 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a copy 7 * of this software and associated documentation files (the "Software"), to deal 8 * in the Software without restriction, including without limitation the rights 9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 10 * copies of the Software, and to permit persons to whom the Software is 11 * furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice shall be included in 14 * all copies or substantial portions of the Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN 22 * THE SOFTWARE. 23 */ 24 25 #include "qemu/osdep.h" 26 #include "qemu/range.h" 27 #include "hw/southbridge/piix.h" 28 #include "hw/irq.h" 29 #include "hw/isa/isa.h" 30 #include "hw/xen/xen.h" 31 #include "sysemu/xen.h" 32 #include "sysemu/reset.h" 33 #include "sysemu/runstate.h" 34 #include "migration/vmstate.h" 35 #include "hw/acpi/acpi_aml_interface.h" 36 37 #define XEN_PIIX_NUM_PIRQS 128ULL 38 39 static void piix3_set_irq_pic(PIIX3State *piix3, int pic_irq) 40 { 41 qemu_set_irq(piix3->pic[pic_irq], 42 !!(piix3->pic_levels & 43 (((1ULL << PIIX_NUM_PIRQS) - 1) << 44 (pic_irq * PIIX_NUM_PIRQS)))); 45 } 46 47 static void piix3_set_irq_level_internal(PIIX3State *piix3, int pirq, int level) 48 { 49 int pic_irq; 50 uint64_t mask; 51 52 pic_irq = piix3->dev.config[PIIX_PIRQCA + pirq]; 53 if (pic_irq >= PIIX_NUM_PIC_IRQS) { 54 return; 55 } 56 57 mask = 1ULL << ((pic_irq * PIIX_NUM_PIRQS) + pirq); 58 piix3->pic_levels &= ~mask; 59 piix3->pic_levels |= mask * !!level; 60 } 61 62 static void piix3_set_irq_level(PIIX3State *piix3, int pirq, int level) 63 { 64 int pic_irq; 65 66 pic_irq = piix3->dev.config[PIIX_PIRQCA + pirq]; 67 if (pic_irq >= PIIX_NUM_PIC_IRQS) { 68 return; 69 } 70 71 piix3_set_irq_level_internal(piix3, pirq, level); 72 73 piix3_set_irq_pic(piix3, pic_irq); 74 } 75 76 static void piix3_set_irq(void *opaque, int pirq, int level) 77 { 78 PIIX3State *piix3 = opaque; 79 piix3_set_irq_level(piix3, pirq, level); 80 } 81 82 static PCIINTxRoute piix3_route_intx_pin_to_irq(void *opaque, int pin) 83 { 84 PIIX3State *piix3 = opaque; 85 int irq = piix3->dev.config[PIIX_PIRQCA + pin]; 86 PCIINTxRoute route; 87 88 if (irq < PIIX_NUM_PIC_IRQS) { 89 route.mode = PCI_INTX_ENABLED; 90 route.irq = irq; 91 } else { 92 route.mode = PCI_INTX_DISABLED; 93 route.irq = -1; 94 } 95 return route; 96 } 97 98 /* irq routing is changed. so rebuild bitmap */ 99 static void piix3_update_irq_levels(PIIX3State *piix3) 100 { 101 PCIBus *bus = pci_get_bus(&piix3->dev); 102 int pirq; 103 104 piix3->pic_levels = 0; 105 for (pirq = 0; pirq < PIIX_NUM_PIRQS; pirq++) { 106 piix3_set_irq_level(piix3, pirq, pci_bus_get_irq_level(bus, pirq)); 107 } 108 } 109 110 static void piix3_write_config(PCIDevice *dev, 111 uint32_t address, uint32_t val, int len) 112 { 113 pci_default_write_config(dev, address, val, len); 114 if (ranges_overlap(address, len, PIIX_PIRQCA, 4)) { 115 PIIX3State *piix3 = PIIX3_PCI_DEVICE(dev); 116 int pic_irq; 117 118 pci_bus_fire_intx_routing_notifier(pci_get_bus(&piix3->dev)); 119 piix3_update_irq_levels(piix3); 120 for (pic_irq = 0; pic_irq < PIIX_NUM_PIC_IRQS; pic_irq++) { 121 piix3_set_irq_pic(piix3, pic_irq); 122 } 123 } 124 } 125 126 static void piix3_write_config_xen(PCIDevice *dev, 127 uint32_t address, uint32_t val, int len) 128 { 129 xen_piix_pci_write_config_client(address, val, len); 130 piix3_write_config(dev, address, val, len); 131 } 132 133 static void piix3_reset(void *opaque) 134 { 135 PIIX3State *d = opaque; 136 uint8_t *pci_conf = d->dev.config; 137 138 pci_conf[0x04] = 0x07; /* master, memory and I/O */ 139 pci_conf[0x05] = 0x00; 140 pci_conf[0x06] = 0x00; 141 pci_conf[0x07] = 0x02; /* PCI_status_devsel_medium */ 142 pci_conf[0x4c] = 0x4d; 143 pci_conf[0x4e] = 0x03; 144 pci_conf[0x4f] = 0x00; 145 pci_conf[0x60] = 0x80; 146 pci_conf[0x61] = 0x80; 147 pci_conf[0x62] = 0x80; 148 pci_conf[0x63] = 0x80; 149 pci_conf[0x69] = 0x02; 150 pci_conf[0x70] = 0x80; 151 pci_conf[0x76] = 0x0c; 152 pci_conf[0x77] = 0x0c; 153 pci_conf[0x78] = 0x02; 154 pci_conf[0x79] = 0x00; 155 pci_conf[0x80] = 0x00; 156 pci_conf[0x82] = 0x00; 157 pci_conf[0xa0] = 0x08; 158 pci_conf[0xa2] = 0x00; 159 pci_conf[0xa3] = 0x00; 160 pci_conf[0xa4] = 0x00; 161 pci_conf[0xa5] = 0x00; 162 pci_conf[0xa6] = 0x00; 163 pci_conf[0xa7] = 0x00; 164 pci_conf[0xa8] = 0x0f; 165 pci_conf[0xaa] = 0x00; 166 pci_conf[0xab] = 0x00; 167 pci_conf[0xac] = 0x00; 168 pci_conf[0xae] = 0x00; 169 170 d->pic_levels = 0; 171 d->rcr = 0; 172 } 173 174 static int piix3_post_load(void *opaque, int version_id) 175 { 176 PIIX3State *piix3 = opaque; 177 int pirq; 178 179 /* 180 * Because the i8259 has not been deserialized yet, qemu_irq_raise 181 * might bring the system to a different state than the saved one; 182 * for example, the interrupt could be masked but the i8259 would 183 * not know that yet and would trigger an interrupt in the CPU. 184 * 185 * Here, we update irq levels without raising the interrupt. 186 * Interrupt state will be deserialized separately through the i8259. 187 */ 188 piix3->pic_levels = 0; 189 for (pirq = 0; pirq < PIIX_NUM_PIRQS; pirq++) { 190 piix3_set_irq_level_internal(piix3, pirq, 191 pci_bus_get_irq_level(pci_get_bus(&piix3->dev), pirq)); 192 } 193 return 0; 194 } 195 196 static int piix3_pre_save(void *opaque) 197 { 198 int i; 199 PIIX3State *piix3 = opaque; 200 201 for (i = 0; i < ARRAY_SIZE(piix3->pci_irq_levels_vmstate); i++) { 202 piix3->pci_irq_levels_vmstate[i] = 203 pci_bus_get_irq_level(pci_get_bus(&piix3->dev), i); 204 } 205 206 return 0; 207 } 208 209 static bool piix3_rcr_needed(void *opaque) 210 { 211 PIIX3State *piix3 = opaque; 212 213 return (piix3->rcr != 0); 214 } 215 216 static const VMStateDescription vmstate_piix3_rcr = { 217 .name = "PIIX3/rcr", 218 .version_id = 1, 219 .minimum_version_id = 1, 220 .needed = piix3_rcr_needed, 221 .fields = (VMStateField[]) { 222 VMSTATE_UINT8(rcr, PIIX3State), 223 VMSTATE_END_OF_LIST() 224 } 225 }; 226 227 static const VMStateDescription vmstate_piix3 = { 228 .name = "PIIX3", 229 .version_id = 3, 230 .minimum_version_id = 2, 231 .post_load = piix3_post_load, 232 .pre_save = piix3_pre_save, 233 .fields = (VMStateField[]) { 234 VMSTATE_PCI_DEVICE(dev, PIIX3State), 235 VMSTATE_INT32_ARRAY_V(pci_irq_levels_vmstate, PIIX3State, 236 PIIX_NUM_PIRQS, 3), 237 VMSTATE_END_OF_LIST() 238 }, 239 .subsections = (const VMStateDescription*[]) { 240 &vmstate_piix3_rcr, 241 NULL 242 } 243 }; 244 245 246 static void rcr_write(void *opaque, hwaddr addr, uint64_t val, unsigned len) 247 { 248 PIIX3State *d = opaque; 249 250 if (val & 4) { 251 qemu_system_reset_request(SHUTDOWN_CAUSE_GUEST_RESET); 252 return; 253 } 254 d->rcr = val & 2; /* keep System Reset type only */ 255 } 256 257 static uint64_t rcr_read(void *opaque, hwaddr addr, unsigned len) 258 { 259 PIIX3State *d = opaque; 260 261 return d->rcr; 262 } 263 264 static const MemoryRegionOps rcr_ops = { 265 .read = rcr_read, 266 .write = rcr_write, 267 .endianness = DEVICE_LITTLE_ENDIAN 268 }; 269 270 static void piix3_realize(PCIDevice *dev, Error **errp) 271 { 272 PIIX3State *d = PIIX3_PCI_DEVICE(dev); 273 274 if (!isa_bus_new(DEVICE(d), get_system_memory(), 275 pci_address_space_io(dev), errp)) { 276 return; 277 } 278 279 memory_region_init_io(&d->rcr_mem, OBJECT(dev), &rcr_ops, d, 280 "piix3-reset-control", 1); 281 memory_region_add_subregion_overlap(pci_address_space_io(dev), 282 PIIX_RCR_IOPORT, &d->rcr_mem, 1); 283 284 qemu_register_reset(piix3_reset, d); 285 } 286 287 static void build_pci_isa_aml(AcpiDevAmlIf *adev, Aml *scope) 288 { 289 BusChild *kid; 290 BusState *bus = qdev_get_child_bus(DEVICE(adev), "isa.0"); 291 292 /* PIIX PCI to ISA irq remapping */ 293 aml_append(scope, aml_operation_region("P40C", AML_PCI_CONFIG, 294 aml_int(0x60), 0x04)); 295 QTAILQ_FOREACH(kid, &bus->children, sibling) { 296 call_dev_aml_func(DEVICE(kid->child), scope); 297 } 298 } 299 300 static void pci_piix3_class_init(ObjectClass *klass, void *data) 301 { 302 DeviceClass *dc = DEVICE_CLASS(klass); 303 PCIDeviceClass *k = PCI_DEVICE_CLASS(klass); 304 AcpiDevAmlIfClass *adevc = ACPI_DEV_AML_IF_CLASS(klass); 305 306 dc->desc = "ISA bridge"; 307 dc->vmsd = &vmstate_piix3; 308 dc->hotpluggable = false; 309 k->realize = piix3_realize; 310 k->vendor_id = PCI_VENDOR_ID_INTEL; 311 /* 82371SB PIIX3 PCI-to-ISA bridge (Step A1) */ 312 k->device_id = PCI_DEVICE_ID_INTEL_82371SB_0; 313 k->class_id = PCI_CLASS_BRIDGE_ISA; 314 /* 315 * Reason: part of PIIX3 southbridge, needs to be wired up by 316 * pc_piix.c's pc_init1() 317 */ 318 dc->user_creatable = false; 319 adevc->build_dev_aml = build_pci_isa_aml; 320 } 321 322 static const TypeInfo piix3_pci_type_info = { 323 .name = TYPE_PIIX3_PCI_DEVICE, 324 .parent = TYPE_PCI_DEVICE, 325 .instance_size = sizeof(PIIX3State), 326 .abstract = true, 327 .class_init = pci_piix3_class_init, 328 .interfaces = (InterfaceInfo[]) { 329 { INTERFACE_CONVENTIONAL_PCI_DEVICE }, 330 { TYPE_ACPI_DEV_AML_IF }, 331 { }, 332 }, 333 }; 334 335 static void piix3_class_init(ObjectClass *klass, void *data) 336 { 337 PCIDeviceClass *k = PCI_DEVICE_CLASS(klass); 338 339 k->config_write = piix3_write_config; 340 } 341 342 static const TypeInfo piix3_info = { 343 .name = TYPE_PIIX3_DEVICE, 344 .parent = TYPE_PIIX3_PCI_DEVICE, 345 .class_init = piix3_class_init, 346 }; 347 348 static void piix3_xen_class_init(ObjectClass *klass, void *data) 349 { 350 PCIDeviceClass *k = PCI_DEVICE_CLASS(klass); 351 352 k->config_write = piix3_write_config_xen; 353 }; 354 355 static const TypeInfo piix3_xen_info = { 356 .name = TYPE_PIIX3_XEN_DEVICE, 357 .parent = TYPE_PIIX3_PCI_DEVICE, 358 .class_init = piix3_xen_class_init, 359 }; 360 361 static void piix3_register_types(void) 362 { 363 type_register_static(&piix3_pci_type_info); 364 type_register_static(&piix3_info); 365 type_register_static(&piix3_xen_info); 366 } 367 368 type_init(piix3_register_types) 369 370 /* 371 * Return the global irq number corresponding to a given device irq 372 * pin. We could also use the bus number to have a more precise mapping. 373 */ 374 static int pci_slot_get_pirq(PCIDevice *pci_dev, int pci_intx) 375 { 376 int slot_addend; 377 slot_addend = PCI_SLOT(pci_dev->devfn) - 1; 378 return (pci_intx + slot_addend) & 3; 379 } 380 381 PIIX3State *piix3_create(PCIBus *pci_bus, ISABus **isa_bus) 382 { 383 PIIX3State *piix3; 384 PCIDevice *pci_dev; 385 386 /* 387 * Xen supports additional interrupt routes from the PCI devices to 388 * the IOAPIC: the four pins of each PCI device on the bus are also 389 * connected to the IOAPIC directly. 390 * These additional routes can be discovered through ACPI. 391 */ 392 if (xen_enabled()) { 393 pci_dev = pci_create_simple_multifunction(pci_bus, -1, true, 394 TYPE_PIIX3_XEN_DEVICE); 395 piix3 = PIIX3_PCI_DEVICE(pci_dev); 396 pci_bus_irqs(pci_bus, xen_piix3_set_irq, xen_pci_slot_get_pirq, 397 piix3, XEN_PIIX_NUM_PIRQS); 398 } else { 399 pci_dev = pci_create_simple_multifunction(pci_bus, -1, true, 400 TYPE_PIIX3_DEVICE); 401 piix3 = PIIX3_PCI_DEVICE(pci_dev); 402 pci_bus_irqs(pci_bus, piix3_set_irq, pci_slot_get_pirq, 403 piix3, PIIX_NUM_PIRQS); 404 pci_bus_set_route_irq_fn(pci_bus, piix3_route_intx_pin_to_irq); 405 } 406 *isa_bus = ISA_BUS(qdev_get_child_bus(DEVICE(piix3), "isa.0")); 407 408 return piix3; 409 } 410