1 /* 2 * QEMU PIIX PCI ISA Bridge Emulation 3 * 4 * Copyright (c) 2006 Fabrice Bellard 5 * Copyright (c) 2018 Hervé Poussineau 6 * 7 * Permission is hereby granted, free of charge, to any person obtaining a copy 8 * of this software and associated documentation files (the "Software"), to deal 9 * in the Software without restriction, including without limitation the rights 10 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 11 * copies of the Software, and to permit persons to whom the Software is 12 * furnished to do so, subject to the following conditions: 13 * 14 * The above copyright notice and this permission notice shall be included in 15 * all copies or substantial portions of the Software. 16 * 17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 19 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 20 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 21 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 22 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN 23 * THE SOFTWARE. 24 */ 25 26 #include "qemu/osdep.h" 27 #include "qemu/range.h" 28 #include "qapi/error.h" 29 #include "hw/dma/i8257.h" 30 #include "hw/southbridge/piix.h" 31 #include "hw/timer/i8254.h" 32 #include "hw/irq.h" 33 #include "hw/qdev-properties.h" 34 #include "hw/ide/piix.h" 35 #include "hw/intc/i8259.h" 36 #include "hw/isa/isa.h" 37 #include "sysemu/runstate.h" 38 #include "migration/vmstate.h" 39 #include "hw/acpi/acpi_aml_interface.h" 40 41 typedef struct PIIXState PIIX4State; 42 43 DECLARE_INSTANCE_CHECKER(PIIX4State, PIIX4_PCI_DEVICE, TYPE_PIIX4_PCI_DEVICE) 44 45 static void piix3_set_irq_pic(PIIXState *piix3, int pic_irq) 46 { 47 qemu_set_irq(piix3->isa_irqs_in[pic_irq], 48 !!(piix3->pic_levels & 49 (((1ULL << PIIX_NUM_PIRQS) - 1) << 50 (pic_irq * PIIX_NUM_PIRQS)))); 51 } 52 53 static void piix3_set_irq_level_internal(PIIXState *piix3, int pirq, int level) 54 { 55 int pic_irq; 56 uint64_t mask; 57 58 pic_irq = piix3->dev.config[PIIX_PIRQCA + pirq]; 59 if (pic_irq >= ISA_NUM_IRQS) { 60 return; 61 } 62 63 mask = 1ULL << ((pic_irq * PIIX_NUM_PIRQS) + pirq); 64 piix3->pic_levels &= ~mask; 65 piix3->pic_levels |= mask * !!level; 66 } 67 68 static void piix3_set_irq_level(PIIXState *piix3, int pirq, int level) 69 { 70 int pic_irq; 71 72 pic_irq = piix3->dev.config[PIIX_PIRQCA + pirq]; 73 if (pic_irq >= ISA_NUM_IRQS) { 74 return; 75 } 76 77 piix3_set_irq_level_internal(piix3, pirq, level); 78 79 piix3_set_irq_pic(piix3, pic_irq); 80 } 81 82 static void piix3_set_irq(void *opaque, int pirq, int level) 83 { 84 PIIXState *piix3 = opaque; 85 piix3_set_irq_level(piix3, pirq, level); 86 } 87 88 static void piix4_set_irq(void *opaque, int irq_num, int level) 89 { 90 int i, pic_irq, pic_level; 91 PIIX4State *s = opaque; 92 PCIBus *bus = pci_get_bus(&s->dev); 93 94 /* now we change the pic irq level according to the piix irq mappings */ 95 /* XXX: optimize */ 96 pic_irq = s->dev.config[PIIX_PIRQCA + irq_num]; 97 if (pic_irq < ISA_NUM_IRQS) { 98 /* The pic level is the logical OR of all the PCI irqs mapped to it. */ 99 pic_level = 0; 100 for (i = 0; i < PIIX_NUM_PIRQS; i++) { 101 if (pic_irq == s->dev.config[PIIX_PIRQCA + i]) { 102 pic_level |= pci_bus_get_irq_level(bus, i); 103 } 104 } 105 qemu_set_irq(s->isa_irqs_in[pic_irq], pic_level); 106 } 107 } 108 109 static void piix4_request_i8259_irq(void *opaque, int irq, int level) 110 { 111 PIIX4State *s = opaque; 112 qemu_set_irq(s->cpu_intr, level); 113 } 114 115 static PCIINTxRoute piix3_route_intx_pin_to_irq(void *opaque, int pin) 116 { 117 PIIXState *piix3 = opaque; 118 int irq = piix3->dev.config[PIIX_PIRQCA + pin]; 119 PCIINTxRoute route; 120 121 if (irq < ISA_NUM_IRQS) { 122 route.mode = PCI_INTX_ENABLED; 123 route.irq = irq; 124 } else { 125 route.mode = PCI_INTX_DISABLED; 126 route.irq = -1; 127 } 128 return route; 129 } 130 131 /* irq routing is changed. so rebuild bitmap */ 132 static void piix3_update_irq_levels(PIIXState *piix3) 133 { 134 PCIBus *bus = pci_get_bus(&piix3->dev); 135 int pirq; 136 137 piix3->pic_levels = 0; 138 for (pirq = 0; pirq < PIIX_NUM_PIRQS; pirq++) { 139 piix3_set_irq_level(piix3, pirq, pci_bus_get_irq_level(bus, pirq)); 140 } 141 } 142 143 static void piix3_write_config(PCIDevice *dev, 144 uint32_t address, uint32_t val, int len) 145 { 146 pci_default_write_config(dev, address, val, len); 147 if (ranges_overlap(address, len, PIIX_PIRQCA, 4)) { 148 PIIXState *piix3 = PIIX_PCI_DEVICE(dev); 149 int pic_irq; 150 151 pci_bus_fire_intx_routing_notifier(pci_get_bus(&piix3->dev)); 152 piix3_update_irq_levels(piix3); 153 for (pic_irq = 0; pic_irq < ISA_NUM_IRQS; pic_irq++) { 154 piix3_set_irq_pic(piix3, pic_irq); 155 } 156 } 157 } 158 159 static void piix_reset(PIIXState *d) 160 { 161 uint8_t *pci_conf = d->dev.config; 162 163 pci_conf[0x04] = 0x07; /* master, memory and I/O */ 164 pci_conf[0x05] = 0x00; 165 pci_conf[0x06] = 0x00; 166 pci_conf[0x07] = 0x02; /* PCI_status_devsel_medium */ 167 pci_conf[0x4c] = 0x4d; 168 pci_conf[0x4e] = 0x03; 169 pci_conf[0x4f] = 0x00; 170 pci_conf[0x60] = 0x80; 171 pci_conf[0x61] = 0x80; 172 pci_conf[0x62] = 0x80; 173 pci_conf[0x63] = 0x80; 174 pci_conf[0x69] = 0x02; 175 pci_conf[0x70] = 0x80; 176 pci_conf[0x76] = 0x0c; 177 pci_conf[0x77] = 0x0c; 178 pci_conf[0x78] = 0x02; 179 pci_conf[0x79] = 0x00; 180 pci_conf[0x80] = 0x00; 181 pci_conf[0x82] = 0x00; 182 pci_conf[0xa0] = 0x08; 183 pci_conf[0xa2] = 0x00; 184 pci_conf[0xa3] = 0x00; 185 pci_conf[0xa4] = 0x00; 186 pci_conf[0xa5] = 0x00; 187 pci_conf[0xa6] = 0x00; 188 pci_conf[0xa7] = 0x00; 189 pci_conf[0xa8] = 0x0f; 190 pci_conf[0xaa] = 0x00; 191 pci_conf[0xab] = 0x00; 192 pci_conf[0xac] = 0x00; 193 pci_conf[0xae] = 0x00; 194 195 d->pic_levels = 0; 196 d->rcr = 0; 197 } 198 199 static void piix3_reset(DeviceState *dev) 200 { 201 PIIXState *d = PIIX_PCI_DEVICE(dev); 202 203 piix_reset(d); 204 } 205 206 static int piix3_post_load(void *opaque, int version_id) 207 { 208 PIIXState *piix3 = opaque; 209 int pirq; 210 211 /* 212 * Because the i8259 has not been deserialized yet, qemu_irq_raise 213 * might bring the system to a different state than the saved one; 214 * for example, the interrupt could be masked but the i8259 would 215 * not know that yet and would trigger an interrupt in the CPU. 216 * 217 * Here, we update irq levels without raising the interrupt. 218 * Interrupt state will be deserialized separately through the i8259. 219 */ 220 piix3->pic_levels = 0; 221 for (pirq = 0; pirq < PIIX_NUM_PIRQS; pirq++) { 222 piix3_set_irq_level_internal(piix3, pirq, 223 pci_bus_get_irq_level(pci_get_bus(&piix3->dev), pirq)); 224 } 225 return 0; 226 } 227 228 static int piix4_post_load(void *opaque, int version_id) 229 { 230 PIIX4State *s = opaque; 231 232 if (version_id == 2) { 233 s->rcr = 0; 234 } 235 236 return 0; 237 } 238 239 static int piix3_pre_save(void *opaque) 240 { 241 int i; 242 PIIXState *piix3 = opaque; 243 244 for (i = 0; i < ARRAY_SIZE(piix3->pci_irq_levels_vmstate); i++) { 245 piix3->pci_irq_levels_vmstate[i] = 246 pci_bus_get_irq_level(pci_get_bus(&piix3->dev), i); 247 } 248 249 return 0; 250 } 251 252 static bool piix3_rcr_needed(void *opaque) 253 { 254 PIIXState *piix3 = opaque; 255 256 return (piix3->rcr != 0); 257 } 258 259 static const VMStateDescription vmstate_piix3_rcr = { 260 .name = "PIIX3/rcr", 261 .version_id = 1, 262 .minimum_version_id = 1, 263 .needed = piix3_rcr_needed, 264 .fields = (VMStateField[]) { 265 VMSTATE_UINT8(rcr, PIIXState), 266 VMSTATE_END_OF_LIST() 267 } 268 }; 269 270 static const VMStateDescription vmstate_piix3 = { 271 .name = "PIIX3", 272 .version_id = 3, 273 .minimum_version_id = 2, 274 .post_load = piix3_post_load, 275 .pre_save = piix3_pre_save, 276 .fields = (VMStateField[]) { 277 VMSTATE_PCI_DEVICE(dev, PIIXState), 278 VMSTATE_INT32_ARRAY_V(pci_irq_levels_vmstate, PIIXState, 279 PIIX_NUM_PIRQS, 3), 280 VMSTATE_END_OF_LIST() 281 }, 282 .subsections = (const VMStateDescription*[]) { 283 &vmstate_piix3_rcr, 284 NULL 285 } 286 }; 287 288 static const VMStateDescription vmstate_piix4 = { 289 .name = "PIIX4", 290 .version_id = 3, 291 .minimum_version_id = 2, 292 .post_load = piix4_post_load, 293 .fields = (VMStateField[]) { 294 VMSTATE_PCI_DEVICE(dev, PIIX4State), 295 VMSTATE_UINT8_V(rcr, PIIX4State, 3), 296 VMSTATE_END_OF_LIST() 297 } 298 }; 299 300 static void rcr_write(void *opaque, hwaddr addr, uint64_t val, unsigned len) 301 { 302 PIIXState *d = opaque; 303 304 if (val & 4) { 305 qemu_system_reset_request(SHUTDOWN_CAUSE_GUEST_RESET); 306 return; 307 } 308 d->rcr = val & 2; /* keep System Reset type only */ 309 } 310 311 static uint64_t rcr_read(void *opaque, hwaddr addr, unsigned len) 312 { 313 PIIXState *d = opaque; 314 315 return d->rcr; 316 } 317 318 static const MemoryRegionOps rcr_ops = { 319 .read = rcr_read, 320 .write = rcr_write, 321 .endianness = DEVICE_LITTLE_ENDIAN, 322 .impl = { 323 .min_access_size = 1, 324 .max_access_size = 1, 325 }, 326 }; 327 328 static void pci_piix3_realize(PCIDevice *dev, Error **errp) 329 { 330 PIIXState *d = PIIX_PCI_DEVICE(dev); 331 PCIBus *pci_bus = pci_get_bus(dev); 332 ISABus *isa_bus; 333 uint32_t irq; 334 335 isa_bus = isa_bus_new(DEVICE(d), pci_address_space(dev), 336 pci_address_space_io(dev), errp); 337 if (!isa_bus) { 338 return; 339 } 340 341 memory_region_init_io(&d->rcr_mem, OBJECT(dev), &rcr_ops, d, 342 "piix3-reset-control", 1); 343 memory_region_add_subregion_overlap(pci_address_space_io(dev), 344 PIIX_RCR_IOPORT, &d->rcr_mem, 1); 345 346 isa_bus_register_input_irqs(isa_bus, d->isa_irqs_in); 347 348 i8257_dma_init(isa_bus, 0); 349 350 /* RTC */ 351 qdev_prop_set_int32(DEVICE(&d->rtc), "base_year", 2000); 352 if (!qdev_realize(DEVICE(&d->rtc), BUS(isa_bus), errp)) { 353 return; 354 } 355 irq = object_property_get_uint(OBJECT(&d->rtc), "irq", &error_fatal); 356 isa_connect_gpio_out(ISA_DEVICE(&d->rtc), 0, irq); 357 358 /* IDE */ 359 qdev_prop_set_int32(DEVICE(&d->ide), "addr", dev->devfn + 1); 360 if (!qdev_realize(DEVICE(&d->ide), BUS(pci_bus), errp)) { 361 return; 362 } 363 364 /* USB */ 365 if (d->has_usb) { 366 object_initialize_child(OBJECT(dev), "uhci", &d->uhci, 367 TYPE_PIIX3_USB_UHCI); 368 qdev_prop_set_int32(DEVICE(&d->uhci), "addr", dev->devfn + 2); 369 if (!qdev_realize(DEVICE(&d->uhci), BUS(pci_bus), errp)) { 370 return; 371 } 372 } 373 374 /* Power Management */ 375 if (d->has_acpi) { 376 object_initialize_child(OBJECT(d), "pm", &d->pm, TYPE_PIIX4_PM); 377 qdev_prop_set_int32(DEVICE(&d->pm), "addr", dev->devfn + 3); 378 qdev_prop_set_uint32(DEVICE(&d->pm), "smb_io_base", d->smb_io_base); 379 qdev_prop_set_bit(DEVICE(&d->pm), "smm-enabled", d->smm_enabled); 380 if (!qdev_realize(DEVICE(&d->pm), BUS(pci_bus), errp)) { 381 return; 382 } 383 qdev_connect_gpio_out(DEVICE(&d->pm), 0, d->isa_irqs_in[9]); 384 } 385 } 386 387 static void build_pci_isa_aml(AcpiDevAmlIf *adev, Aml *scope) 388 { 389 Aml *field; 390 Aml *sb_scope = aml_scope("\\_SB"); 391 BusState *bus = qdev_get_child_bus(DEVICE(adev), "isa.0"); 392 393 /* PIIX PCI to ISA irq remapping */ 394 aml_append(scope, aml_operation_region("P40C", AML_PCI_CONFIG, 395 aml_int(0x60), 0x04)); 396 /* Fields declarion has to happen *after* operation region */ 397 field = aml_field("PCI0.S08.P40C", AML_BYTE_ACC, AML_NOLOCK, AML_PRESERVE); 398 aml_append(field, aml_named_field("PRQ0", 8)); 399 aml_append(field, aml_named_field("PRQ1", 8)); 400 aml_append(field, aml_named_field("PRQ2", 8)); 401 aml_append(field, aml_named_field("PRQ3", 8)); 402 aml_append(sb_scope, field); 403 aml_append(scope, sb_scope); 404 405 qbus_build_aml(bus, scope); 406 } 407 408 static void pci_piix3_init(Object *obj) 409 { 410 PIIXState *d = PIIX_PCI_DEVICE(obj); 411 412 qdev_init_gpio_out_named(DEVICE(obj), d->isa_irqs_in, "isa-irqs", 413 ISA_NUM_IRQS); 414 415 object_initialize_child(obj, "rtc", &d->rtc, TYPE_MC146818_RTC); 416 object_initialize_child(obj, "ide", &d->ide, TYPE_PIIX3_IDE); 417 } 418 419 static Property pci_piix3_props[] = { 420 DEFINE_PROP_UINT32("smb_io_base", PIIXState, smb_io_base, 0), 421 DEFINE_PROP_BOOL("has-acpi", PIIXState, has_acpi, true), 422 DEFINE_PROP_BOOL("has-usb", PIIXState, has_usb, true), 423 DEFINE_PROP_BOOL("smm-enabled", PIIXState, smm_enabled, false), 424 DEFINE_PROP_END_OF_LIST(), 425 }; 426 427 static void pci_piix3_class_init(ObjectClass *klass, void *data) 428 { 429 DeviceClass *dc = DEVICE_CLASS(klass); 430 PCIDeviceClass *k = PCI_DEVICE_CLASS(klass); 431 AcpiDevAmlIfClass *adevc = ACPI_DEV_AML_IF_CLASS(klass); 432 433 k->config_write = piix3_write_config; 434 dc->reset = piix3_reset; 435 dc->desc = "ISA bridge"; 436 dc->vmsd = &vmstate_piix3; 437 dc->hotpluggable = false; 438 k->vendor_id = PCI_VENDOR_ID_INTEL; 439 /* 82371SB PIIX3 PCI-to-ISA bridge (Step A1) */ 440 k->device_id = PCI_DEVICE_ID_INTEL_82371SB_0; 441 k->class_id = PCI_CLASS_BRIDGE_ISA; 442 /* 443 * Reason: part of PIIX3 southbridge, needs to be wired up by 444 * pc_piix.c's pc_init1() 445 */ 446 dc->user_creatable = false; 447 device_class_set_props(dc, pci_piix3_props); 448 adevc->build_dev_aml = build_pci_isa_aml; 449 } 450 451 static const TypeInfo piix_pci_type_info = { 452 .name = TYPE_PIIX_PCI_DEVICE, 453 .parent = TYPE_PCI_DEVICE, 454 .instance_size = sizeof(PIIXState), 455 .instance_init = pci_piix3_init, 456 .abstract = true, 457 .class_init = pci_piix3_class_init, 458 .interfaces = (InterfaceInfo[]) { 459 { INTERFACE_CONVENTIONAL_PCI_DEVICE }, 460 { TYPE_ACPI_DEV_AML_IF }, 461 { }, 462 }, 463 }; 464 465 static void piix3_realize(PCIDevice *dev, Error **errp) 466 { 467 ERRP_GUARD(); 468 PIIXState *piix3 = PIIX_PCI_DEVICE(dev); 469 PCIBus *pci_bus = pci_get_bus(dev); 470 471 pci_piix3_realize(dev, errp); 472 if (*errp) { 473 return; 474 } 475 476 pci_bus_irqs(pci_bus, piix3_set_irq, piix3, PIIX_NUM_PIRQS); 477 pci_bus_set_route_irq_fn(pci_bus, piix3_route_intx_pin_to_irq); 478 } 479 480 static void piix3_class_init(ObjectClass *klass, void *data) 481 { 482 PCIDeviceClass *k = PCI_DEVICE_CLASS(klass); 483 484 k->realize = piix3_realize; 485 } 486 487 static const TypeInfo piix3_info = { 488 .name = TYPE_PIIX3_DEVICE, 489 .parent = TYPE_PIIX_PCI_DEVICE, 490 .class_init = piix3_class_init, 491 }; 492 493 static void piix4_realize(PCIDevice *dev, Error **errp) 494 { 495 PIIX4State *s = PIIX4_PCI_DEVICE(dev); 496 PCIBus *pci_bus = pci_get_bus(dev); 497 ISABus *isa_bus; 498 qemu_irq *i8259_out_irq; 499 qemu_irq *i8259; 500 size_t i; 501 502 isa_bus = isa_bus_new(DEVICE(dev), pci_address_space(dev), 503 pci_address_space_io(dev), errp); 504 if (!isa_bus) { 505 return; 506 } 507 508 qdev_init_gpio_out_named(DEVICE(dev), &s->cpu_intr, 509 "intr", 1); 510 511 memory_region_init_io(&s->rcr_mem, OBJECT(dev), &rcr_ops, s, 512 "reset-control", 1); 513 memory_region_add_subregion_overlap(pci_address_space_io(dev), 514 PIIX_RCR_IOPORT, &s->rcr_mem, 1); 515 516 /* initialize i8259 pic */ 517 i8259_out_irq = qemu_allocate_irqs(piix4_request_i8259_irq, s, 1); 518 i8259 = i8259_init(isa_bus, *i8259_out_irq); 519 520 for (i = 0; i < ISA_NUM_IRQS; i++) { 521 s->isa_irqs_in[i] = i8259[i]; 522 } 523 524 g_free(i8259); 525 526 /* initialize ISA irqs */ 527 isa_bus_register_input_irqs(isa_bus, s->isa_irqs_in); 528 529 /* initialize pit */ 530 i8254_pit_init(isa_bus, 0x40, 0, NULL); 531 532 /* DMA */ 533 i8257_dma_init(isa_bus, 0); 534 535 /* RTC */ 536 qdev_prop_set_int32(DEVICE(&s->rtc), "base_year", 2000); 537 if (!qdev_realize(DEVICE(&s->rtc), BUS(isa_bus), errp)) { 538 return; 539 } 540 s->rtc.irq = isa_get_irq(ISA_DEVICE(&s->rtc), s->rtc.isairq); 541 542 /* IDE */ 543 qdev_prop_set_int32(DEVICE(&s->ide), "addr", dev->devfn + 1); 544 if (!qdev_realize(DEVICE(&s->ide), BUS(pci_bus), errp)) { 545 return; 546 } 547 548 /* USB */ 549 qdev_prop_set_int32(DEVICE(&s->uhci), "addr", dev->devfn + 2); 550 if (!qdev_realize(DEVICE(&s->uhci), BUS(pci_bus), errp)) { 551 return; 552 } 553 554 /* ACPI controller */ 555 qdev_prop_set_int32(DEVICE(&s->pm), "addr", dev->devfn + 3); 556 if (!qdev_realize(DEVICE(&s->pm), BUS(pci_bus), errp)) { 557 return; 558 } 559 qdev_connect_gpio_out(DEVICE(&s->pm), 0, s->isa_irqs_in[9]); 560 561 pci_bus_irqs(pci_bus, piix4_set_irq, s, PIIX_NUM_PIRQS); 562 } 563 564 static void piix4_isa_reset(DeviceState *dev) 565 { 566 PIIX4State *s = PIIX4_PCI_DEVICE(dev); 567 568 piix_reset(s); 569 } 570 571 static void piix4_init(Object *obj) 572 { 573 PIIX4State *s = PIIX4_PCI_DEVICE(obj); 574 575 object_initialize_child(obj, "rtc", &s->rtc, TYPE_MC146818_RTC); 576 object_initialize_child(obj, "ide", &s->ide, TYPE_PIIX4_IDE); 577 object_initialize_child(obj, "uhci", &s->uhci, TYPE_PIIX4_USB_UHCI); 578 579 object_initialize_child(obj, "pm", &s->pm, TYPE_PIIX4_PM); 580 qdev_prop_set_uint32(DEVICE(&s->pm), "smb_io_base", 0x1100); 581 qdev_prop_set_bit(DEVICE(&s->pm), "smm-enabled", 0); 582 } 583 584 static void piix4_class_init(ObjectClass *klass, void *data) 585 { 586 DeviceClass *dc = DEVICE_CLASS(klass); 587 PCIDeviceClass *k = PCI_DEVICE_CLASS(klass); 588 589 k->realize = piix4_realize; 590 k->vendor_id = PCI_VENDOR_ID_INTEL; 591 k->device_id = PCI_DEVICE_ID_INTEL_82371AB_0; 592 k->class_id = PCI_CLASS_BRIDGE_ISA; 593 dc->reset = piix4_isa_reset; 594 dc->desc = "ISA bridge"; 595 dc->vmsd = &vmstate_piix4; 596 /* 597 * Reason: part of PIIX4 southbridge, needs to be wired up, 598 * e.g. by mips_malta_init() 599 */ 600 dc->user_creatable = false; 601 dc->hotpluggable = false; 602 } 603 604 static const TypeInfo piix4_info = { 605 .name = TYPE_PIIX4_PCI_DEVICE, 606 .parent = TYPE_PCI_DEVICE, 607 .instance_size = sizeof(PIIX4State), 608 .instance_init = piix4_init, 609 .class_init = piix4_class_init, 610 .interfaces = (InterfaceInfo[]) { 611 { INTERFACE_CONVENTIONAL_PCI_DEVICE }, 612 { }, 613 }, 614 }; 615 616 static void piix3_register_types(void) 617 { 618 type_register_static(&piix_pci_type_info); 619 type_register_static(&piix3_info); 620 type_register_static(&piix4_info); 621 } 622 623 type_init(piix3_register_types) 624