1 /* 2 * QEMU National Semiconductor PC87312 (Super I/O) 3 * 4 * Copyright (c) 2010-2012 Herve Poussineau 5 * Copyright (c) 2011-2012 Andreas Färber 6 * 7 * Permission is hereby granted, free of charge, to any person obtaining a copy 8 * of this software and associated documentation files (the "Software"), to deal 9 * in the Software without restriction, including without limitation the rights 10 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 11 * copies of the Software, and to permit persons to whom the Software is 12 * furnished to do so, subject to the following conditions: 13 * 14 * The above copyright notice and this permission notice shall be included in 15 * all copies or substantial portions of the Software. 16 * 17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 19 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 20 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 21 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 22 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN 23 * THE SOFTWARE. 24 */ 25 26 #include "qemu/osdep.h" 27 #include "hw/isa/pc87312.h" 28 #include "qapi/error.h" 29 #include "qemu/error-report.h" 30 #include "sysemu/block-backend.h" 31 #include "sysemu/blockdev.h" 32 #include "sysemu/sysemu.h" 33 #include "chardev/char.h" 34 #include "trace.h" 35 36 37 #define REG_FER 0 38 #define REG_FAR 1 39 #define REG_PTR 2 40 41 #define FER_PARALLEL_EN 0x01 42 #define FER_UART1_EN 0x02 43 #define FER_UART2_EN 0x04 44 #define FER_FDC_EN 0x08 45 #define FER_FDC_4 0x10 46 #define FER_FDC_ADDR 0x20 47 #define FER_IDE_EN 0x40 48 #define FER_IDE_ADDR 0x80 49 50 #define FAR_PARALLEL_ADDR 0x03 51 #define FAR_UART1_ADDR 0x0C 52 #define FAR_UART2_ADDR 0x30 53 #define FAR_UART_3_4 0xC0 54 55 #define PTR_POWER_DOWN 0x01 56 #define PTR_CLOCK_DOWN 0x02 57 #define PTR_PWDN 0x04 58 #define PTR_IRQ_5_7 0x08 59 #define PTR_UART1_TEST 0x10 60 #define PTR_UART2_TEST 0x20 61 #define PTR_LOCK_CONF 0x40 62 #define PTR_EPP_MODE 0x80 63 64 65 /* Parallel port */ 66 67 static bool is_parallel_enabled(ISASuperIODevice *sio, uint8_t index) 68 { 69 PC87312State *s = PC87312(sio); 70 return index ? false : s->regs[REG_FER] & FER_PARALLEL_EN; 71 } 72 73 static const uint16_t parallel_base[] = { 0x378, 0x3bc, 0x278, 0x00 }; 74 75 static uint16_t get_parallel_iobase(ISASuperIODevice *sio, uint8_t index) 76 { 77 PC87312State *s = PC87312(sio); 78 return parallel_base[s->regs[REG_FAR] & FAR_PARALLEL_ADDR]; 79 } 80 81 static const unsigned int parallel_irq[] = { 5, 7, 5, 0 }; 82 83 static unsigned int get_parallel_irq(ISASuperIODevice *sio, uint8_t index) 84 { 85 PC87312State *s = PC87312(sio); 86 int idx; 87 idx = (s->regs[REG_FAR] & FAR_PARALLEL_ADDR); 88 if (idx == 0) { 89 return (s->regs[REG_PTR] & PTR_IRQ_5_7) ? 7 : 5; 90 } else { 91 return parallel_irq[idx]; 92 } 93 } 94 95 96 /* UARTs */ 97 98 static const uint16_t uart_base[2][4] = { 99 { 0x3e8, 0x338, 0x2e8, 0x220 }, 100 { 0x2e8, 0x238, 0x2e0, 0x228 } 101 }; 102 103 static inline uint16_t get_uart_iobase(PC87312State *s, int i) 104 { 105 int idx; 106 idx = (s->regs[REG_FAR] >> (2 * i + 2)) & 0x3; 107 if (idx == 0) { 108 return 0x3f8; 109 } else if (idx == 1) { 110 return 0x2f8; 111 } else { 112 return uart_base[idx & 1][(s->regs[REG_FAR] & FAR_UART_3_4) >> 6]; 113 } 114 } 115 116 static inline unsigned int get_uart_irq(PC87312State *s, int i) 117 { 118 int idx; 119 idx = (s->regs[REG_FAR] >> (2 * i + 2)) & 0x3; 120 return (idx & 1) ? 3 : 4; 121 } 122 123 static inline bool is_uart_enabled(PC87312State *s, int i) 124 { 125 return s->regs[REG_FER] & (FER_UART1_EN << i); 126 } 127 128 129 /* Floppy controller */ 130 131 static inline bool is_fdc_enabled(PC87312State *s) 132 { 133 return s->regs[REG_FER] & FER_FDC_EN; 134 } 135 136 static inline uint16_t get_fdc_iobase(PC87312State *s) 137 { 138 return (s->regs[REG_FER] & FER_FDC_ADDR) ? 0x370 : 0x3f0; 139 } 140 141 142 /* IDE controller */ 143 144 static inline bool is_ide_enabled(PC87312State *s) 145 { 146 return s->regs[REG_FER] & FER_IDE_EN; 147 } 148 149 static inline uint16_t get_ide_iobase(PC87312State *s) 150 { 151 return (s->regs[REG_FER] & FER_IDE_ADDR) ? 0x170 : 0x1f0; 152 } 153 154 155 static void reconfigure_devices(PC87312State *s) 156 { 157 error_report("pc87312: unsupported device reconfiguration (%02x %02x %02x)", 158 s->regs[REG_FER], s->regs[REG_FAR], s->regs[REG_PTR]); 159 } 160 161 static void pc87312_soft_reset(PC87312State *s) 162 { 163 static const uint8_t fer_init[] = { 164 0x4f, 0x4f, 0x4f, 0x4f, 0x4f, 0x4f, 0x4b, 0x4b, 165 0x4b, 0x4b, 0x4b, 0x4b, 0x0f, 0x0f, 0x0f, 0x0f, 166 0x49, 0x49, 0x49, 0x49, 0x07, 0x07, 0x07, 0x07, 167 0x47, 0x47, 0x47, 0x47, 0x47, 0x47, 0x08, 0x00, 168 }; 169 static const uint8_t far_init[] = { 170 0x10, 0x11, 0x11, 0x39, 0x24, 0x38, 0x00, 0x01, 171 0x01, 0x09, 0x08, 0x08, 0x10, 0x11, 0x39, 0x24, 172 0x00, 0x01, 0x01, 0x00, 0x10, 0x11, 0x39, 0x24, 173 0x10, 0x11, 0x11, 0x39, 0x24, 0x38, 0x10, 0x10, 174 }; 175 static const uint8_t ptr_init[] = { 176 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 177 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 178 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 179 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x02, 180 }; 181 182 s->read_id_step = 0; 183 s->selected_index = REG_FER; 184 185 s->regs[REG_FER] = fer_init[s->config & 0x1f]; 186 s->regs[REG_FAR] = far_init[s->config & 0x1f]; 187 s->regs[REG_PTR] = ptr_init[s->config & 0x1f]; 188 } 189 190 static void pc87312_hard_reset(PC87312State *s) 191 { 192 pc87312_soft_reset(s); 193 } 194 195 static void pc87312_io_write(void *opaque, hwaddr addr, uint64_t val, 196 unsigned int size) 197 { 198 PC87312State *s = opaque; 199 200 trace_pc87312_io_write(addr, val); 201 202 if ((addr & 1) == 0) { 203 /* Index register */ 204 s->read_id_step = 2; 205 s->selected_index = val; 206 } else { 207 /* Data register */ 208 if (s->selected_index < 3) { 209 s->regs[s->selected_index] = val; 210 reconfigure_devices(s); 211 } 212 } 213 } 214 215 static uint64_t pc87312_io_read(void *opaque, hwaddr addr, unsigned int size) 216 { 217 PC87312State *s = opaque; 218 uint32_t val; 219 220 if ((addr & 1) == 0) { 221 /* Index register */ 222 if (s->read_id_step++ == 0) { 223 val = 0x88; 224 } else if (s->read_id_step++ == 1) { 225 val = 0; 226 } else { 227 val = s->selected_index; 228 } 229 } else { 230 /* Data register */ 231 if (s->selected_index < 3) { 232 val = s->regs[s->selected_index]; 233 } else { 234 /* Invalid selected index */ 235 val = 0; 236 } 237 } 238 239 trace_pc87312_io_read(addr, val); 240 return val; 241 } 242 243 static const MemoryRegionOps pc87312_io_ops = { 244 .read = pc87312_io_read, 245 .write = pc87312_io_write, 246 .endianness = DEVICE_LITTLE_ENDIAN, 247 .valid = { 248 .min_access_size = 1, 249 .max_access_size = 1, 250 }, 251 }; 252 253 static int pc87312_post_load(void *opaque, int version_id) 254 { 255 PC87312State *s = opaque; 256 257 reconfigure_devices(s); 258 return 0; 259 } 260 261 static void pc87312_reset(DeviceState *d) 262 { 263 PC87312State *s = PC87312(d); 264 265 pc87312_soft_reset(s); 266 } 267 268 static void pc87312_realize(DeviceState *dev, Error **errp) 269 { 270 PC87312State *s; 271 DeviceState *d; 272 ISADevice *isa; 273 ISABus *bus; 274 Chardev *chr; 275 DriveInfo *drive; 276 Error *local_err = NULL; 277 char name[5]; 278 int i; 279 280 s = PC87312(dev); 281 isa = ISA_DEVICE(dev); 282 bus = isa_bus_from_device(isa); 283 isa_register_ioport(isa, &s->io, s->iobase); 284 pc87312_hard_reset(s); 285 286 ISA_SUPERIO_GET_CLASS(dev)->parent_realize(dev, &local_err); 287 if (local_err) { 288 error_propagate(errp, local_err); 289 return; 290 } 291 292 for (i = 0; i < 2; i++) { 293 if (is_uart_enabled(s, i)) { 294 /* FIXME use a qdev chardev prop instead of serial_hds[] */ 295 chr = serial_hds[i]; 296 if (chr == NULL) { 297 snprintf(name, sizeof(name), "ser%d", i); 298 chr = qemu_chr_new(name, "null"); 299 } 300 isa = isa_create(bus, "isa-serial"); 301 d = DEVICE(isa); 302 qdev_prop_set_uint32(d, "index", i); 303 qdev_prop_set_uint32(d, "iobase", get_uart_iobase(s, i)); 304 qdev_prop_set_uint32(d, "irq", get_uart_irq(s, i)); 305 qdev_prop_set_chr(d, "chardev", chr); 306 qdev_init_nofail(d); 307 s->uart[i].dev = isa; 308 trace_pc87312_info_serial(i, get_uart_iobase(s, i), 309 get_uart_irq(s, i)); 310 } 311 } 312 313 if (is_fdc_enabled(s)) { 314 isa = isa_create(bus, "isa-fdc"); 315 d = DEVICE(isa); 316 qdev_prop_set_uint32(d, "iobase", get_fdc_iobase(s)); 317 qdev_prop_set_uint32(d, "irq", 6); 318 /* FIXME use a qdev drive property instead of drive_get() */ 319 drive = drive_get(IF_FLOPPY, 0, 0); 320 if (drive != NULL) { 321 qdev_prop_set_drive(d, "driveA", blk_by_legacy_dinfo(drive), 322 &error_fatal); 323 } 324 /* FIXME use a qdev drive property instead of drive_get() */ 325 drive = drive_get(IF_FLOPPY, 0, 1); 326 if (drive != NULL) { 327 qdev_prop_set_drive(d, "driveB", blk_by_legacy_dinfo(drive), 328 &error_fatal); 329 } 330 qdev_init_nofail(d); 331 s->fdc.dev = isa; 332 trace_pc87312_info_floppy(get_fdc_iobase(s)); 333 } 334 335 if (is_ide_enabled(s)) { 336 isa = isa_create(bus, "isa-ide"); 337 d = DEVICE(isa); 338 qdev_prop_set_uint32(d, "iobase", get_ide_iobase(s)); 339 qdev_prop_set_uint32(d, "iobase2", get_ide_iobase(s) + 0x206); 340 qdev_prop_set_uint32(d, "irq", 14); 341 qdev_init_nofail(d); 342 s->ide.dev = isa; 343 trace_pc87312_info_ide(get_ide_iobase(s)); 344 } 345 } 346 347 static void pc87312_initfn(Object *obj) 348 { 349 PC87312State *s = PC87312(obj); 350 351 memory_region_init_io(&s->io, obj, &pc87312_io_ops, s, "pc87312", 2); 352 } 353 354 static const VMStateDescription vmstate_pc87312 = { 355 .name = "pc87312", 356 .version_id = 1, 357 .minimum_version_id = 1, 358 .post_load = pc87312_post_load, 359 .fields = (VMStateField[]) { 360 VMSTATE_UINT8(read_id_step, PC87312State), 361 VMSTATE_UINT8(selected_index, PC87312State), 362 VMSTATE_UINT8_ARRAY(regs, PC87312State, 3), 363 VMSTATE_END_OF_LIST() 364 } 365 }; 366 367 static Property pc87312_properties[] = { 368 DEFINE_PROP_UINT16("iobase", PC87312State, iobase, 0x398), 369 DEFINE_PROP_UINT8("config", PC87312State, config, 1), 370 DEFINE_PROP_END_OF_LIST() 371 }; 372 373 static void pc87312_class_init(ObjectClass *klass, void *data) 374 { 375 DeviceClass *dc = DEVICE_CLASS(klass); 376 ISASuperIOClass *sc = ISA_SUPERIO_CLASS(klass); 377 378 sc->parent_realize = dc->realize; 379 dc->realize = pc87312_realize; 380 dc->reset = pc87312_reset; 381 dc->vmsd = &vmstate_pc87312; 382 dc->props = pc87312_properties; 383 /* Reason: Uses serial_hds[0] in realize(), so it can't be used twice */ 384 dc->user_creatable = false; 385 386 sc->parallel = (ISASuperIOFuncs){ 387 .count = 1, 388 .is_enabled = is_parallel_enabled, 389 .get_iobase = get_parallel_iobase, 390 .get_irq = get_parallel_irq, 391 }; 392 } 393 394 static const TypeInfo pc87312_type_info = { 395 .name = TYPE_PC87312_SUPERIO, 396 .parent = TYPE_ISA_SUPERIO, 397 .instance_size = sizeof(PC87312State), 398 .instance_init = pc87312_initfn, 399 .class_init = pc87312_class_init, 400 }; 401 402 static void pc87312_register_types(void) 403 { 404 type_register_static(&pc87312_type_info); 405 } 406 407 type_init(pc87312_register_types) 408