1 /* 2 * QEMU ICH9 Emulation 3 * 4 * Copyright (c) 2006 Fabrice Bellard 5 * Copyright (c) 2009, 2010, 2011 6 * Isaku Yamahata <yamahata at valinux co jp> 7 * VA Linux Systems Japan K.K. 8 * Copyright (C) 2012 Jason Baron <jbaron@redhat.com> 9 * 10 * This is based on piix.c, but heavily modified. 11 * 12 * Permission is hereby granted, free of charge, to any person obtaining a copy 13 * of this software and associated documentation files (the "Software"), to deal 14 * in the Software without restriction, including without limitation the rights 15 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 16 * copies of the Software, and to permit persons to whom the Software is 17 * furnished to do so, subject to the following conditions: 18 * 19 * The above copyright notice and this permission notice shall be included in 20 * all copies or substantial portions of the Software. 21 * 22 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 23 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 24 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 25 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 26 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 27 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN 28 * THE SOFTWARE. 29 */ 30 31 #include "qemu/osdep.h" 32 #include "qemu/log.h" 33 #include "cpu.h" 34 #include "qapi/error.h" 35 #include "qapi/visitor.h" 36 #include "qemu/range.h" 37 #include "hw/dma/i8257.h" 38 #include "hw/isa/isa.h" 39 #include "migration/vmstate.h" 40 #include "hw/irq.h" 41 #include "hw/isa/apm.h" 42 #include "hw/pci/pci.h" 43 #include "hw/southbridge/ich9.h" 44 #include "hw/acpi/acpi.h" 45 #include "hw/acpi/ich9.h" 46 #include "hw/acpi/ich9_timer.h" 47 #include "hw/pci/pci_bus.h" 48 #include "hw/qdev-properties.h" 49 #include "system/runstate.h" 50 #include "system/system.h" 51 #include "hw/core/cpu.h" 52 #include "hw/nvram/fw_cfg.h" 53 #include "qemu/cutils.h" 54 #include "hw/acpi/acpi_aml_interface.h" 55 #include "trace.h" 56 57 /*****************************************************************************/ 58 /* ICH9 LPC PCI to ISA bridge */ 59 60 /* chipset configuration register 61 * to access chipset configuration registers, pci_[sg]et_{byte, word, long} 62 * are used. 63 * Although it's not pci configuration space, it's little endian as Intel. 64 */ 65 66 static void ich9_cc_update_ir(uint8_t irr[PCI_NUM_PINS], uint16_t ir) 67 { 68 int intx; 69 for (intx = 0; intx < PCI_NUM_PINS; intx++) { 70 irr[intx] = (ir >> (intx * ICH9_CC_DIR_SHIFT)) & ICH9_CC_DIR_MASK; 71 } 72 } 73 74 static void ich9_cc_update(ICH9LPCState *lpc) 75 { 76 int slot; 77 int pci_intx; 78 79 const int reg_offsets[] = { 80 ICH9_CC_D25IR, 81 ICH9_CC_D26IR, 82 ICH9_CC_D27IR, 83 ICH9_CC_D28IR, 84 ICH9_CC_D29IR, 85 ICH9_CC_D30IR, 86 ICH9_CC_D31IR, 87 }; 88 const int *offset; 89 90 /* D{25 - 31}IR, but D30IR is read only to 0. */ 91 for (slot = 25, offset = reg_offsets; slot < 32; slot++, offset++) { 92 if (slot == 30) { 93 continue; 94 } 95 ich9_cc_update_ir(lpc->irr[slot], 96 pci_get_word(lpc->chip_config + *offset)); 97 } 98 99 /* 100 * D30: DMI2PCI bridge 101 * It is arbitrarily decided how INTx lines of PCI devices behind 102 * the bridge are connected to pirq lines. Our choice is PIRQ[E-H]. 103 * INT[A-D] are connected to PIRQ[E-H] 104 */ 105 for (pci_intx = 0; pci_intx < PCI_NUM_PINS; pci_intx++) { 106 lpc->irr[30][pci_intx] = pci_intx + 4; 107 } 108 } 109 110 static void ich9_cc_init(ICH9LPCState *lpc) 111 { 112 int slot; 113 int intx; 114 115 /* the default irq routing is arbitrary as long as it matches with 116 * acpi irq routing table. 117 * The one that is incompatible with piix_pci(= bochs) one is 118 * intentionally chosen to let the users know that the different 119 * board is used. 120 * 121 * int[A-D] -> pirq[E-F] 122 * avoid pirq A-D because they are used for pci express port 123 */ 124 for (slot = 0; slot < PCI_SLOT_MAX; slot++) { 125 for (intx = 0; intx < PCI_NUM_PINS; intx++) { 126 lpc->irr[slot][intx] = (slot + intx) % 4 + 4; 127 } 128 } 129 ich9_cc_update(lpc); 130 } 131 132 static void ich9_cc_reset(ICH9LPCState *lpc) 133 { 134 uint8_t *c = lpc->chip_config; 135 136 memset(lpc->chip_config, 0, sizeof(lpc->chip_config)); 137 138 pci_set_long(c + ICH9_CC_D31IR, ICH9_CC_DIR_DEFAULT); 139 pci_set_long(c + ICH9_CC_D30IR, ICH9_CC_D30IR_DEFAULT); 140 pci_set_long(c + ICH9_CC_D29IR, ICH9_CC_DIR_DEFAULT); 141 pci_set_long(c + ICH9_CC_D28IR, ICH9_CC_DIR_DEFAULT); 142 pci_set_long(c + ICH9_CC_D27IR, ICH9_CC_DIR_DEFAULT); 143 pci_set_long(c + ICH9_CC_D26IR, ICH9_CC_DIR_DEFAULT); 144 pci_set_long(c + ICH9_CC_D25IR, ICH9_CC_DIR_DEFAULT); 145 pci_set_long(c + ICH9_CC_GCS, ICH9_CC_GCS_DEFAULT); 146 147 ich9_cc_update(lpc); 148 } 149 150 static void ich9_cc_addr_len(uint64_t *addr, unsigned *len) 151 { 152 *addr &= ICH9_CC_ADDR_MASK; 153 if (*addr + *len >= ICH9_CC_SIZE) { 154 *len = ICH9_CC_SIZE - *addr; 155 } 156 } 157 158 /* val: little endian */ 159 static void ich9_cc_write(void *opaque, hwaddr addr, 160 uint64_t val, unsigned len) 161 { 162 ICH9LPCState *lpc = (ICH9LPCState *)opaque; 163 164 trace_ich9_cc_write(addr, val, len); 165 ich9_cc_addr_len(&addr, &len); 166 memcpy(lpc->chip_config + addr, &val, len); 167 pci_bus_fire_intx_routing_notifier(pci_get_bus(&lpc->d)); 168 ich9_cc_update(lpc); 169 } 170 171 /* return value: little endian */ 172 static uint64_t ich9_cc_read(void *opaque, hwaddr addr, 173 unsigned len) 174 { 175 ICH9LPCState *lpc = (ICH9LPCState *)opaque; 176 177 uint32_t val = 0; 178 ich9_cc_addr_len(&addr, &len); 179 memcpy(&val, lpc->chip_config + addr, len); 180 trace_ich9_cc_read(addr, val, len); 181 return val; 182 } 183 184 /* IRQ routing */ 185 static void ich9_lpc_rout(uint8_t pirq_rout, int *pic_irq, int *pic_dis) 186 { 187 *pic_irq = pirq_rout & ICH9_LPC_PIRQ_ROUT_MASK; 188 *pic_dis = pirq_rout & ICH9_LPC_PIRQ_ROUT_IRQEN; 189 } 190 191 static void ich9_lpc_pic_irq(ICH9LPCState *lpc, int pirq_num, 192 int *pic_irq, int *pic_dis) 193 { 194 switch (pirq_num) { 195 case 0 ... 3: /* A-D */ 196 ich9_lpc_rout(lpc->d.config[ICH9_LPC_PIRQA_ROUT + pirq_num], 197 pic_irq, pic_dis); 198 return; 199 case 4 ... 7: /* E-H */ 200 ich9_lpc_rout(lpc->d.config[ICH9_LPC_PIRQE_ROUT + (pirq_num - 4)], 201 pic_irq, pic_dis); 202 return; 203 default: 204 break; 205 } 206 abort(); 207 } 208 209 /* gsi: i8259+ioapic irq 0-15, otherwise assert */ 210 static void ich9_lpc_update_pic(ICH9LPCState *lpc, int gsi) 211 { 212 int i, pic_level; 213 214 assert(gsi < ICH9_LPC_PIC_NUM_PINS); 215 216 /* The pic level is the logical OR of all the PCI irqs mapped to it */ 217 pic_level = 0; 218 for (i = 0; i < ICH9_LPC_NB_PIRQS; i++) { 219 int tmp_irq; 220 int tmp_dis; 221 ich9_lpc_pic_irq(lpc, i, &tmp_irq, &tmp_dis); 222 if (!tmp_dis && tmp_irq == gsi) { 223 pic_level |= pci_bus_get_irq_level(pci_get_bus(&lpc->d), i); 224 } 225 } 226 if (gsi == lpc->sci_gsi) { 227 pic_level |= lpc->sci_level; 228 } 229 230 qemu_set_irq(lpc->gsi[gsi], pic_level); 231 } 232 233 /* APIC mode: GSIx: PIRQ[A-H] -> GSI 16, ... no pirq shares same APIC pins. */ 234 static int ich9_pirq_to_gsi(int pirq) 235 { 236 return pirq + ICH9_LPC_PIC_NUM_PINS; 237 } 238 239 static int ich9_gsi_to_pirq(int gsi) 240 { 241 return gsi - ICH9_LPC_PIC_NUM_PINS; 242 } 243 244 /* gsi: ioapic irq 16-23, otherwise assert */ 245 static void ich9_lpc_update_apic(ICH9LPCState *lpc, int gsi) 246 { 247 int level = 0; 248 249 assert(gsi >= ICH9_LPC_PIC_NUM_PINS); 250 251 level |= pci_bus_get_irq_level(pci_get_bus(&lpc->d), ich9_gsi_to_pirq(gsi)); 252 if (gsi == lpc->sci_gsi) { 253 level |= lpc->sci_level; 254 } 255 256 qemu_set_irq(lpc->gsi[gsi], level); 257 } 258 259 static void ich9_lpc_set_irq(void *opaque, int pirq, int level) 260 { 261 ICH9LPCState *lpc = opaque; 262 int pic_irq, pic_dis; 263 264 assert(0 <= pirq); 265 assert(pirq < ICH9_LPC_NB_PIRQS); 266 267 ich9_lpc_update_apic(lpc, ich9_pirq_to_gsi(pirq)); 268 ich9_lpc_pic_irq(lpc, pirq, &pic_irq, &pic_dis); 269 ich9_lpc_update_pic(lpc, pic_irq); 270 } 271 272 /* return the pirq number (PIRQ[A-H]:0-7) corresponding to 273 * a given device irq pin. 274 */ 275 static int ich9_lpc_map_irq(PCIDevice *pci_dev, int intx) 276 { 277 BusState *bus = qdev_get_parent_bus(&pci_dev->qdev); 278 PCIBus *pci_bus = PCI_BUS(bus); 279 PCIDevice *lpc_pdev = 280 pci_bus->devices[PCI_DEVFN(ICH9_LPC_DEV, ICH9_LPC_FUNC)]; 281 ICH9LPCState *lpc = ICH9_LPC_DEVICE(lpc_pdev); 282 283 return lpc->irr[PCI_SLOT(pci_dev->devfn)][intx]; 284 } 285 286 static PCIINTxRoute ich9_route_intx_pin_to_irq(void *opaque, int pirq_pin) 287 { 288 ICH9LPCState *lpc = opaque; 289 PCIINTxRoute route; 290 int pic_irq; 291 int pic_dis; 292 293 assert(0 <= pirq_pin); 294 assert(pirq_pin < ICH9_LPC_NB_PIRQS); 295 296 route.mode = PCI_INTX_ENABLED; 297 ich9_lpc_pic_irq(lpc, pirq_pin, &pic_irq, &pic_dis); 298 if (!pic_dis) { 299 if (pic_irq < ICH9_LPC_PIC_NUM_PINS) { 300 route.irq = pic_irq; 301 } else { 302 route.mode = PCI_INTX_DISABLED; 303 route.irq = -1; 304 } 305 } else { 306 /* 307 * Strictly speaking, this is wrong. The PIRQ should be routed 308 * to *both* the I/O APIC and the PIC, on different pins. The 309 * I/O APIC has a fixed mapping to IRQ16-23, while the PIC is 310 * routed according to the PIRQx_ROUT configuration. But QEMU 311 * doesn't (yet) cope with the concept of pin numbers differing 312 * between PIC and I/O APIC, and neither does the in-kernel KVM 313 * irqchip support. So we route to the I/O APIC *only* if the 314 * routing to the PIC is disabled in the PIRQx_ROUT settings. 315 * 316 * This seems to work even if we boot a Linux guest with 'noapic' 317 * to make it use the legacy PIC, and then kexec directly into a 318 * new kernel which uses the I/O APIC. The new kernel explicitly 319 * disables the PIRQ routing even though it doesn't need to care. 320 */ 321 route.irq = ich9_pirq_to_gsi(pirq_pin); 322 } 323 324 return route; 325 } 326 327 void ich9_generate_smi(void) 328 { 329 cpu_interrupt(first_cpu, CPU_INTERRUPT_SMI); 330 } 331 332 /* Returns -1 on error, IRQ number on success */ 333 static int ich9_lpc_sci_irq(ICH9LPCState *lpc) 334 { 335 uint8_t sel = lpc->d.config[ICH9_LPC_ACPI_CTRL] & 336 ICH9_LPC_ACPI_CTRL_SCI_IRQ_SEL_MASK; 337 switch (sel) { 338 case ICH9_LPC_ACPI_CTRL_9: 339 return 9; 340 case ICH9_LPC_ACPI_CTRL_10: 341 return 10; 342 case ICH9_LPC_ACPI_CTRL_11: 343 return 11; 344 case ICH9_LPC_ACPI_CTRL_20: 345 return 20; 346 case ICH9_LPC_ACPI_CTRL_21: 347 return 21; 348 default: 349 /* reserved */ 350 qemu_log_mask(LOG_GUEST_ERROR, 351 "ICH9 LPC: SCI IRQ SEL #%u is reserved\n", sel); 352 break; 353 } 354 return -1; 355 } 356 357 static void ich9_set_sci(void *opaque, int irq_num, int level) 358 { 359 ICH9LPCState *lpc = opaque; 360 int irq; 361 362 assert(irq_num == 0); 363 level = !!level; 364 if (level == lpc->sci_level) { 365 return; 366 } 367 lpc->sci_level = level; 368 369 irq = lpc->sci_gsi; 370 if (irq < 0) { 371 return; 372 } 373 374 if (irq >= ICH9_LPC_PIC_NUM_PINS) { 375 ich9_lpc_update_apic(lpc, irq); 376 } else { 377 ich9_lpc_update_pic(lpc, irq); 378 } 379 } 380 381 static void smi_features_ok_callback(void *opaque) 382 { 383 ICH9LPCState *lpc = opaque; 384 uint64_t guest_features; 385 uint64_t guest_cpu_hotplug_features; 386 387 if (lpc->smi_features_ok) { 388 /* negotiation already complete, features locked */ 389 return; 390 } 391 392 memcpy(&guest_features, lpc->smi_guest_features_le, sizeof guest_features); 393 le64_to_cpus(&guest_features); 394 if (guest_features & ~lpc->smi_host_features) { 395 /* guest requests invalid features, leave @features_ok at zero */ 396 return; 397 } 398 399 guest_cpu_hotplug_features = guest_features & 400 (BIT_ULL(ICH9_LPC_SMI_F_CPU_HOTPLUG_BIT) | 401 BIT_ULL(ICH9_LPC_SMI_F_CPU_HOT_UNPLUG_BIT)); 402 if (!(guest_features & BIT_ULL(ICH9_LPC_SMI_F_BROADCAST_BIT)) && 403 guest_cpu_hotplug_features) { 404 /* 405 * cpu hot-[un]plug with SMI requires SMI broadcast, 406 * leave @features_ok at zero 407 */ 408 return; 409 } 410 411 if (guest_cpu_hotplug_features == 412 BIT_ULL(ICH9_LPC_SMI_F_CPU_HOT_UNPLUG_BIT)) { 413 /* cpu hot-unplug is unsupported without cpu-hotplug */ 414 return; 415 } 416 417 /* valid feature subset requested, lock it down, report success */ 418 lpc->smi_negotiated_features = guest_features; 419 lpc->smi_features_ok = 1; 420 } 421 422 static void ich9_lpc_pm_init(ICH9LPCState *lpc) 423 { 424 qemu_irq sci_irq; 425 FWCfgState *fw_cfg = fw_cfg_find(); 426 427 sci_irq = qemu_allocate_irq(ich9_set_sci, lpc, 0); 428 ich9_pm_init(PCI_DEVICE(lpc), &lpc->pm, sci_irq); 429 430 if (lpc->smi_host_features && fw_cfg) { 431 uint64_t host_features_le; 432 433 host_features_le = cpu_to_le64(lpc->smi_host_features); 434 memcpy(lpc->smi_host_features_le, &host_features_le, 435 sizeof host_features_le); 436 fw_cfg_add_file(fw_cfg, "etc/smi/supported-features", 437 lpc->smi_host_features_le, 438 sizeof lpc->smi_host_features_le); 439 440 /* The other two guest-visible fields are cleared on device reset, we 441 * just link them into fw_cfg here. 442 */ 443 fw_cfg_add_file_callback(fw_cfg, "etc/smi/requested-features", 444 NULL, NULL, NULL, 445 lpc->smi_guest_features_le, 446 sizeof lpc->smi_guest_features_le, 447 false); 448 fw_cfg_add_file_callback(fw_cfg, "etc/smi/features-ok", 449 smi_features_ok_callback, NULL, lpc, 450 &lpc->smi_features_ok, 451 sizeof lpc->smi_features_ok, 452 true); 453 } 454 } 455 456 /* APM */ 457 458 static void ich9_apm_ctrl_changed(uint32_t val, void *arg) 459 { 460 ICH9LPCState *lpc = arg; 461 462 /* ACPI specs 3.0, 4.7.2.5 */ 463 acpi_pm1_cnt_update(&lpc->pm.acpi_regs, 464 val == ICH9_APM_ACPI_ENABLE, 465 val == ICH9_APM_ACPI_DISABLE); 466 if (val == ICH9_APM_ACPI_ENABLE || val == ICH9_APM_ACPI_DISABLE) { 467 return; 468 } 469 470 /* SMI_EN = PMBASE + 30. SMI control and enable register */ 471 if (lpc->pm.smi_en & ICH9_PMIO_SMI_EN_APMC_EN) { 472 if (lpc->smi_negotiated_features & 473 (UINT64_C(1) << ICH9_LPC_SMI_F_BROADCAST_BIT)) { 474 CPUState *cs; 475 CPU_FOREACH(cs) { 476 cpu_interrupt(cs, CPU_INTERRUPT_SMI); 477 } 478 } else { 479 cpu_interrupt(current_cpu, CPU_INTERRUPT_SMI); 480 } 481 } 482 } 483 484 /* config:PMBASE */ 485 static void 486 ich9_lpc_pmbase_sci_update(ICH9LPCState *lpc) 487 { 488 uint32_t pm_io_base = pci_get_long(lpc->d.config + ICH9_LPC_PMBASE); 489 uint8_t acpi_cntl = pci_get_long(lpc->d.config + ICH9_LPC_ACPI_CTRL); 490 int new_gsi; 491 492 if (acpi_cntl & ICH9_LPC_ACPI_CTRL_ACPI_EN) { 493 pm_io_base &= ICH9_LPC_PMBASE_BASE_ADDRESS_MASK; 494 } else { 495 pm_io_base = 0; 496 } 497 498 ich9_pm_iospace_update(&lpc->pm, pm_io_base); 499 500 new_gsi = ich9_lpc_sci_irq(lpc); 501 if (new_gsi == -1) { 502 return; 503 } 504 if (lpc->sci_level && new_gsi != lpc->sci_gsi) { 505 qemu_set_irq(lpc->pm.irq, 0); 506 lpc->sci_gsi = new_gsi; 507 qemu_set_irq(lpc->pm.irq, 1); 508 } 509 lpc->sci_gsi = new_gsi; 510 } 511 512 /* config:RCBA */ 513 static void ich9_lpc_rcba_update(ICH9LPCState *lpc, uint32_t rcba_old) 514 { 515 uint32_t rcba = pci_get_long(lpc->d.config + ICH9_LPC_RCBA); 516 517 if (rcba_old & ICH9_LPC_RCBA_EN) { 518 memory_region_del_subregion(get_system_memory(), &lpc->rcrb_mem); 519 } 520 if (rcba & ICH9_LPC_RCBA_EN) { 521 memory_region_add_subregion_overlap(get_system_memory(), 522 rcba & ICH9_LPC_RCBA_BA_MASK, 523 &lpc->rcrb_mem, 1); 524 } 525 } 526 527 /* config:GEN_PMCON* */ 528 static void 529 ich9_lpc_pmcon_update(ICH9LPCState *lpc) 530 { 531 uint16_t gen_pmcon_1 = pci_get_word(lpc->d.config + ICH9_LPC_GEN_PMCON_1); 532 uint16_t wmask; 533 534 if (lpc->pm.swsmi_timer_enabled) { 535 ich9_pm_update_swsmi_timer( 536 &lpc->pm, lpc->pm.smi_en & ICH9_PMIO_SMI_EN_SWSMI_EN); 537 } 538 if (lpc->pm.periodic_timer_enabled) { 539 ich9_pm_update_periodic_timer( 540 &lpc->pm, lpc->pm.smi_en & ICH9_PMIO_SMI_EN_PERIODIC_EN); 541 } 542 543 if (gen_pmcon_1 & ICH9_LPC_GEN_PMCON_1_SMI_LOCK) { 544 wmask = pci_get_word(lpc->d.wmask + ICH9_LPC_GEN_PMCON_1); 545 wmask &= ~ICH9_LPC_GEN_PMCON_1_SMI_LOCK; 546 pci_set_word(lpc->d.wmask + ICH9_LPC_GEN_PMCON_1, wmask); 547 lpc->pm.smi_en_wmask &= ~1; 548 } 549 } 550 551 static int ich9_lpc_post_load(void *opaque, int version_id) 552 { 553 ICH9LPCState *lpc = opaque; 554 555 ich9_lpc_pmbase_sci_update(lpc); 556 ich9_lpc_rcba_update(lpc, 0 /* disabled ICH9_LPC_RCBA_EN */); 557 ich9_lpc_pmcon_update(lpc); 558 return 0; 559 } 560 561 static void ich9_lpc_config_write(PCIDevice *d, 562 uint32_t addr, uint32_t val, int len) 563 { 564 ICH9LPCState *lpc = ICH9_LPC_DEVICE(d); 565 uint32_t rcba_old = pci_get_long(d->config + ICH9_LPC_RCBA); 566 567 pci_default_write_config(d, addr, val, len); 568 if (ranges_overlap(addr, len, ICH9_LPC_PMBASE, 4) || 569 ranges_overlap(addr, len, ICH9_LPC_ACPI_CTRL, 1)) { 570 ich9_lpc_pmbase_sci_update(lpc); 571 } 572 if (ranges_overlap(addr, len, ICH9_LPC_RCBA, 4)) { 573 ich9_lpc_rcba_update(lpc, rcba_old); 574 } 575 if (ranges_overlap(addr, len, ICH9_LPC_PIRQA_ROUT, 4)) { 576 pci_bus_fire_intx_routing_notifier(pci_get_bus(&lpc->d)); 577 } 578 if (ranges_overlap(addr, len, ICH9_LPC_PIRQE_ROUT, 4)) { 579 pci_bus_fire_intx_routing_notifier(pci_get_bus(&lpc->d)); 580 } 581 if (ranges_overlap(addr, len, ICH9_LPC_GEN_PMCON_1, 8)) { 582 ich9_lpc_pmcon_update(lpc); 583 } 584 } 585 586 static void ich9_lpc_reset(DeviceState *qdev) 587 { 588 PCIDevice *d = PCI_DEVICE(qdev); 589 ICH9LPCState *lpc = ICH9_LPC_DEVICE(d); 590 uint32_t rcba_old = pci_get_long(d->config + ICH9_LPC_RCBA); 591 int i; 592 593 for (i = 0; i < 4; i++) { 594 pci_set_byte(d->config + ICH9_LPC_PIRQA_ROUT + i, 595 ICH9_LPC_PIRQ_ROUT_DEFAULT); 596 } 597 for (i = 0; i < 4; i++) { 598 pci_set_byte(d->config + ICH9_LPC_PIRQE_ROUT + i, 599 ICH9_LPC_PIRQ_ROUT_DEFAULT); 600 } 601 pci_set_byte(d->config + ICH9_LPC_ACPI_CTRL, ICH9_LPC_ACPI_CTRL_DEFAULT); 602 603 pci_set_long(d->config + ICH9_LPC_PMBASE, ICH9_LPC_PMBASE_DEFAULT); 604 pci_set_long(d->config + ICH9_LPC_RCBA, ICH9_LPC_RCBA_DEFAULT); 605 606 ich9_cc_reset(lpc); 607 608 ich9_lpc_pmbase_sci_update(lpc); 609 ich9_lpc_rcba_update(lpc, rcba_old); 610 611 lpc->sci_level = 0; 612 lpc->rst_cnt = 0; 613 614 memset(lpc->smi_guest_features_le, 0, sizeof lpc->smi_guest_features_le); 615 lpc->smi_features_ok = 0; 616 lpc->smi_negotiated_features = 0; 617 } 618 619 /* root complex register block is mapped into memory space */ 620 static const MemoryRegionOps rcrb_mmio_ops = { 621 .read = ich9_cc_read, 622 .write = ich9_cc_write, 623 .endianness = DEVICE_LITTLE_ENDIAN, 624 }; 625 626 static void ich9_lpc_machine_ready(Notifier *n, void *opaque) 627 { 628 ICH9LPCState *s = container_of(n, ICH9LPCState, machine_ready); 629 MemoryRegion *io_as = pci_address_space_io(&s->d); 630 uint8_t *pci_conf; 631 632 pci_conf = s->d.config; 633 if (memory_region_present(io_as, 0x3f8)) { 634 /* com1 */ 635 pci_conf[0x82] |= 0x01; 636 } 637 if (memory_region_present(io_as, 0x2f8)) { 638 /* com2 */ 639 pci_conf[0x82] |= 0x02; 640 } 641 if (memory_region_present(io_as, 0x378)) { 642 /* lpt */ 643 pci_conf[0x82] |= 0x04; 644 } 645 if (memory_region_present(io_as, 0x3f2)) { 646 /* floppy */ 647 pci_conf[0x82] |= 0x08; 648 } 649 } 650 651 /* reset control */ 652 static void ich9_rst_cnt_write(void *opaque, hwaddr addr, uint64_t val, 653 unsigned len) 654 { 655 ICH9LPCState *lpc = opaque; 656 657 if (val & 4) { 658 qemu_system_reset_request(SHUTDOWN_CAUSE_GUEST_RESET); 659 return; 660 } 661 lpc->rst_cnt = val & 0xA; /* keep FULL_RST (bit 3) and SYS_RST (bit 1) */ 662 } 663 664 static uint64_t ich9_rst_cnt_read(void *opaque, hwaddr addr, unsigned len) 665 { 666 ICH9LPCState *lpc = opaque; 667 668 return lpc->rst_cnt; 669 } 670 671 static const MemoryRegionOps ich9_rst_cnt_ops = { 672 .read = ich9_rst_cnt_read, 673 .write = ich9_rst_cnt_write, 674 .endianness = DEVICE_LITTLE_ENDIAN 675 }; 676 677 static void ich9_lpc_initfn(Object *obj) 678 { 679 ICH9LPCState *lpc = ICH9_LPC_DEVICE(obj); 680 681 static const uint8_t acpi_enable_cmd = ICH9_APM_ACPI_ENABLE; 682 static const uint8_t acpi_disable_cmd = ICH9_APM_ACPI_DISABLE; 683 684 object_initialize_child(obj, "rtc", &lpc->rtc, TYPE_MC146818_RTC); 685 686 qdev_init_gpio_out_named(DEVICE(lpc), lpc->gsi, ICH9_GPIO_GSI, 687 IOAPIC_NUM_PINS); 688 689 object_property_add_uint8_ptr(obj, ACPI_PM_PROP_SCI_INT, 690 &lpc->sci_gsi, OBJ_PROP_FLAG_READ); 691 object_property_add_uint8_ptr(OBJECT(lpc), ACPI_PM_PROP_ACPI_ENABLE_CMD, 692 &acpi_enable_cmd, OBJ_PROP_FLAG_READ); 693 object_property_add_uint8_ptr(OBJECT(lpc), ACPI_PM_PROP_ACPI_DISABLE_CMD, 694 &acpi_disable_cmd, OBJ_PROP_FLAG_READ); 695 object_property_add_uint64_ptr(obj, ICH9_LPC_SMI_NEGOTIATED_FEAT_PROP, 696 &lpc->smi_negotiated_features, 697 OBJ_PROP_FLAG_READ); 698 699 ich9_pm_add_properties(obj, &lpc->pm); 700 } 701 702 static void ich9_lpc_realize(PCIDevice *d, Error **errp) 703 { 704 ICH9LPCState *lpc = ICH9_LPC_DEVICE(d); 705 PCIBus *pci_bus = pci_get_bus(d); 706 ISABus *isa_bus; 707 uint32_t irq; 708 709 if ((lpc->smi_host_features & BIT_ULL(ICH9_LPC_SMI_F_CPU_HOT_UNPLUG_BIT)) && 710 !(lpc->smi_host_features & BIT_ULL(ICH9_LPC_SMI_F_CPU_HOTPLUG_BIT))) { 711 /* 712 * smi_features_ok_callback() throws an error on this. 713 * 714 * So bail out here instead of advertizing the invalid 715 * configuration and get obscure firmware failures from that. 716 */ 717 error_setg(errp, "cpu hot-unplug requires cpu hot-plug"); 718 return; 719 } 720 721 isa_bus = isa_bus_new(DEVICE(d), get_system_memory(), get_system_io(), 722 errp); 723 if (!isa_bus) { 724 return; 725 } 726 727 pci_set_long(d->wmask + ICH9_LPC_PMBASE, 728 ICH9_LPC_PMBASE_BASE_ADDRESS_MASK); 729 pci_set_byte(d->wmask + ICH9_LPC_PMBASE, 730 ICH9_LPC_ACPI_CTRL_ACPI_EN | 731 ICH9_LPC_ACPI_CTRL_SCI_IRQ_SEL_MASK); 732 733 memory_region_init_io(&lpc->rcrb_mem, OBJECT(d), &rcrb_mmio_ops, lpc, 734 "lpc-rcrb-mmio", ICH9_CC_SIZE); 735 736 ich9_cc_init(lpc); 737 apm_init(d, &lpc->apm, ich9_apm_ctrl_changed, lpc); 738 739 lpc->machine_ready.notify = ich9_lpc_machine_ready; 740 qemu_add_machine_init_done_notifier(&lpc->machine_ready); 741 742 memory_region_init_io(&lpc->rst_cnt_mem, OBJECT(d), &ich9_rst_cnt_ops, lpc, 743 "lpc-reset-control", 1); 744 memory_region_add_subregion_overlap(pci_address_space_io(d), 745 ICH9_RST_CNT_IOPORT, &lpc->rst_cnt_mem, 746 1); 747 748 isa_bus_register_input_irqs(isa_bus, lpc->gsi); 749 750 i8257_dma_init(OBJECT(d), isa_bus, 0); 751 752 /* RTC */ 753 qdev_prop_set_int32(DEVICE(&lpc->rtc), "base_year", 2000); 754 if (!qdev_realize(DEVICE(&lpc->rtc), BUS(isa_bus), errp)) { 755 return; 756 } 757 irq = object_property_get_uint(OBJECT(&lpc->rtc), "irq", &error_fatal); 758 isa_connect_gpio_out(ISA_DEVICE(&lpc->rtc), 0, irq); 759 760 pci_bus_irqs(pci_bus, ich9_lpc_set_irq, d, ICH9_LPC_NB_PIRQS); 761 pci_bus_map_irqs(pci_bus, ich9_lpc_map_irq); 762 pci_bus_set_route_irq_fn(pci_bus, ich9_route_intx_pin_to_irq); 763 764 ich9_lpc_pm_init(lpc); 765 } 766 767 static bool ich9_rst_cnt_needed(void *opaque) 768 { 769 ICH9LPCState *lpc = opaque; 770 771 return (lpc->rst_cnt != 0); 772 } 773 774 static const VMStateDescription vmstate_ich9_rst_cnt = { 775 .name = "ICH9LPC/rst_cnt", 776 .version_id = 1, 777 .minimum_version_id = 1, 778 .needed = ich9_rst_cnt_needed, 779 .fields = (const VMStateField[]) { 780 VMSTATE_UINT8(rst_cnt, ICH9LPCState), 781 VMSTATE_END_OF_LIST() 782 } 783 }; 784 785 static bool ich9_smi_feat_needed(void *opaque) 786 { 787 ICH9LPCState *lpc = opaque; 788 789 return !buffer_is_zero(lpc->smi_guest_features_le, 790 sizeof lpc->smi_guest_features_le) || 791 lpc->smi_features_ok; 792 } 793 794 static const VMStateDescription vmstate_ich9_smi_feat = { 795 .name = "ICH9LPC/smi_feat", 796 .version_id = 1, 797 .minimum_version_id = 1, 798 .needed = ich9_smi_feat_needed, 799 .fields = (const VMStateField[]) { 800 VMSTATE_UINT8_ARRAY(smi_guest_features_le, ICH9LPCState, 801 sizeof(uint64_t)), 802 VMSTATE_UINT8(smi_features_ok, ICH9LPCState), 803 VMSTATE_UINT64(smi_negotiated_features, ICH9LPCState), 804 VMSTATE_END_OF_LIST() 805 } 806 }; 807 808 static const VMStateDescription vmstate_ich9_lpc = { 809 .name = "ICH9LPC", 810 .version_id = 1, 811 .minimum_version_id = 1, 812 .post_load = ich9_lpc_post_load, 813 .fields = (const VMStateField[]) { 814 VMSTATE_PCI_DEVICE(d, ICH9LPCState), 815 VMSTATE_STRUCT(apm, ICH9LPCState, 0, vmstate_apm, APMState), 816 VMSTATE_STRUCT(pm, ICH9LPCState, 0, vmstate_ich9_pm, ICH9LPCPMRegs), 817 VMSTATE_UINT8_ARRAY(chip_config, ICH9LPCState, ICH9_CC_SIZE), 818 VMSTATE_UINT32(sci_level, ICH9LPCState), 819 VMSTATE_END_OF_LIST() 820 }, 821 .subsections = (const VMStateDescription * const []) { 822 &vmstate_ich9_rst_cnt, 823 &vmstate_ich9_smi_feat, 824 NULL 825 } 826 }; 827 828 static const Property ich9_lpc_properties[] = { 829 DEFINE_PROP_BOOL("noreboot", ICH9LPCState, pin_strap.spkr_hi, false), 830 DEFINE_PROP_BOOL("smm-compat", ICH9LPCState, pm.smm_compat, false), 831 DEFINE_PROP_BOOL("smm-enabled", ICH9LPCState, pm.smm_enabled, false), 832 DEFINE_PROP_BIT64("x-smi-broadcast", ICH9LPCState, smi_host_features, 833 ICH9_LPC_SMI_F_BROADCAST_BIT, true), 834 DEFINE_PROP_BIT64("x-smi-cpu-hotplug", ICH9LPCState, smi_host_features, 835 ICH9_LPC_SMI_F_CPU_HOTPLUG_BIT, true), 836 DEFINE_PROP_BIT64("x-smi-cpu-hotunplug", ICH9LPCState, smi_host_features, 837 ICH9_LPC_SMI_F_CPU_HOT_UNPLUG_BIT, true), 838 DEFINE_PROP_BOOL("x-smi-swsmi-timer", ICH9LPCState, 839 pm.swsmi_timer_enabled, true), 840 DEFINE_PROP_BOOL("x-smi-periodic-timer", ICH9LPCState, 841 pm.periodic_timer_enabled, true), 842 }; 843 844 static void ich9_send_gpe(AcpiDeviceIf *adev, AcpiEventStatusBits ev) 845 { 846 ICH9LPCState *s = ICH9_LPC_DEVICE(adev); 847 848 acpi_send_gpe_event(&s->pm.acpi_regs, s->pm.irq, ev); 849 } 850 851 static void build_ich9_isa_aml(AcpiDevAmlIf *adev, Aml *scope) 852 { 853 Aml *field; 854 BusState *bus = qdev_get_child_bus(DEVICE(adev), "isa.0"); 855 Aml *sb_scope = aml_scope("\\_SB"); 856 857 /* ICH9 PCI to ISA irq remapping */ 858 aml_append(scope, aml_operation_region("PIRQ", AML_PCI_CONFIG, 859 aml_int(0x60), 0x0C)); 860 /* Fields declarion has to happen *after* operation region */ 861 field = aml_field("PCI0.SF8.PIRQ", AML_BYTE_ACC, AML_NOLOCK, AML_PRESERVE); 862 aml_append(field, aml_named_field("PRQA", 8)); 863 aml_append(field, aml_named_field("PRQB", 8)); 864 aml_append(field, aml_named_field("PRQC", 8)); 865 aml_append(field, aml_named_field("PRQD", 8)); 866 aml_append(field, aml_reserved_field(0x20)); 867 aml_append(field, aml_named_field("PRQE", 8)); 868 aml_append(field, aml_named_field("PRQF", 8)); 869 aml_append(field, aml_named_field("PRQG", 8)); 870 aml_append(field, aml_named_field("PRQH", 8)); 871 aml_append(sb_scope, field); 872 aml_append(scope, sb_scope); 873 874 qbus_build_aml(bus, scope); 875 } 876 877 static void ich9_lpc_class_init(ObjectClass *klass, const void *data) 878 { 879 DeviceClass *dc = DEVICE_CLASS(klass); 880 PCIDeviceClass *k = PCI_DEVICE_CLASS(klass); 881 HotplugHandlerClass *hc = HOTPLUG_HANDLER_CLASS(klass); 882 AcpiDeviceIfClass *adevc = ACPI_DEVICE_IF_CLASS(klass); 883 AcpiDevAmlIfClass *amldevc = ACPI_DEV_AML_IF_CLASS(klass); 884 885 set_bit(DEVICE_CATEGORY_BRIDGE, dc->categories); 886 device_class_set_legacy_reset(dc, ich9_lpc_reset); 887 k->realize = ich9_lpc_realize; 888 dc->vmsd = &vmstate_ich9_lpc; 889 device_class_set_props(dc, ich9_lpc_properties); 890 k->config_write = ich9_lpc_config_write; 891 dc->desc = "ICH9 LPC bridge"; 892 k->vendor_id = PCI_VENDOR_ID_INTEL; 893 k->device_id = PCI_DEVICE_ID_INTEL_ICH9_8; 894 k->revision = ICH9_A2_LPC_REVISION; 895 k->class_id = PCI_CLASS_BRIDGE_ISA; 896 /* 897 * Reason: part of ICH9 southbridge, needs to be wired up by 898 * pc_q35_init() 899 */ 900 dc->user_creatable = false; 901 hc->pre_plug = ich9_pm_device_pre_plug_cb; 902 hc->plug = ich9_pm_device_plug_cb; 903 hc->unplug_request = ich9_pm_device_unplug_request_cb; 904 hc->unplug = ich9_pm_device_unplug_cb; 905 hc->is_hotpluggable_bus = ich9_pm_is_hotpluggable_bus; 906 adevc->ospm_status = ich9_pm_ospm_status; 907 adevc->send_event = ich9_send_gpe; 908 amldevc->build_dev_aml = build_ich9_isa_aml; 909 } 910 911 static const TypeInfo ich9_lpc_info = { 912 .name = TYPE_ICH9_LPC_DEVICE, 913 .parent = TYPE_PCI_DEVICE, 914 .instance_size = sizeof(ICH9LPCState), 915 .instance_init = ich9_lpc_initfn, 916 .class_init = ich9_lpc_class_init, 917 .interfaces = (const InterfaceInfo[]) { 918 { TYPE_HOTPLUG_HANDLER }, 919 { TYPE_ACPI_DEVICE_IF }, 920 { INTERFACE_CONVENTIONAL_PCI_DEVICE }, 921 { TYPE_ACPI_DEV_AML_IF }, 922 { } 923 } 924 }; 925 926 static void ich9_lpc_register(void) 927 { 928 type_register_static(&ich9_lpc_info); 929 } 930 931 type_init(ich9_lpc_register); 932