1c859b566SAlistair Francis /* 2c859b566SAlistair Francis * QEMU model of Xilinx I/O Module Interrupt Controller 3c859b566SAlistair Francis * 4c859b566SAlistair Francis * Copyright (c) 2013 Xilinx Inc 5c859b566SAlistair Francis * Written by Edgar E. Iglesias <edgar.iglesias@xilinx.com> 6c859b566SAlistair Francis * Written by Alistair Francis <alistair.francis@xilinx.com> 7c859b566SAlistair Francis * 8c859b566SAlistair Francis * Permission is hereby granted, free of charge, to any person obtaining a copy 9c859b566SAlistair Francis * of this software and associated documentation files (the "Software"), to deal 10c859b566SAlistair Francis * in the Software without restriction, including without limitation the rights 11c859b566SAlistair Francis * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 12c859b566SAlistair Francis * copies of the Software, and to permit persons to whom the Software is 13c859b566SAlistair Francis * furnished to do so, subject to the following conditions: 14c859b566SAlistair Francis * 15c859b566SAlistair Francis * The above copyright notice and this permission notice shall be included in 16c859b566SAlistair Francis * all copies or substantial portions of the Software. 17c859b566SAlistair Francis * 18c859b566SAlistair Francis * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 19c859b566SAlistair Francis * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 20c859b566SAlistair Francis * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 21c859b566SAlistair Francis * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 22c859b566SAlistair Francis * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 23c859b566SAlistair Francis * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN 24c859b566SAlistair Francis * THE SOFTWARE. 25c859b566SAlistair Francis */ 26c859b566SAlistair Francis 27c859b566SAlistair Francis #include "qemu/osdep.h" 28c859b566SAlistair Francis #include "hw/sysbus.h" 29c859b566SAlistair Francis #include "hw/register.h" 30c859b566SAlistair Francis #include "qemu/bitops.h" 31c859b566SAlistair Francis #include "qemu/log.h" 32*0b8fa32fSMarkus Armbruster #include "qemu/module.h" 33c859b566SAlistair Francis #include "hw/intc/xlnx-pmu-iomod-intc.h" 34c859b566SAlistair Francis 35c859b566SAlistair Francis #ifndef XLNX_PMU_IO_INTC_ERR_DEBUG 36c859b566SAlistair Francis #define XLNX_PMU_IO_INTC_ERR_DEBUG 0 37c859b566SAlistair Francis #endif 38c859b566SAlistair Francis 39c859b566SAlistair Francis #define DB_PRINT_L(lvl, fmt, args...) do {\ 40c859b566SAlistair Francis if (XLNX_PMU_IO_INTC_ERR_DEBUG >= lvl) {\ 41c859b566SAlistair Francis qemu_log(TYPE_XLNX_PMU_IO_INTC ": %s:" fmt, __func__, ## args);\ 42c859b566SAlistair Francis } \ 43c859b566SAlistair Francis } while (0) 44c859b566SAlistair Francis 45c859b566SAlistair Francis #define DB_PRINT(fmt, args...) DB_PRINT_L(1, fmt, ## args) 46c859b566SAlistair Francis 47c859b566SAlistair Francis REG32(IRQ_MODE, 0xc) 48c859b566SAlistair Francis REG32(GPO0, 0x10) 49c859b566SAlistair Francis FIELD(GPO0, MAGIC_WORD_1, 24, 8) 50c859b566SAlistair Francis FIELD(GPO0, MAGIC_WORD_2, 16, 8) 51c859b566SAlistair Francis FIELD(GPO0, FT_INJECT_FAILURE, 13, 3) 52c859b566SAlistair Francis FIELD(GPO0, DISABLE_RST_FTSM, 12, 1) 53c859b566SAlistair Francis FIELD(GPO0, RST_FTSM, 11, 1) 54c859b566SAlistair Francis FIELD(GPO0, CLR_FTSTS, 10, 1) 55c859b566SAlistair Francis FIELD(GPO0, RST_ON_SLEEP, 9, 1) 56c859b566SAlistair Francis FIELD(GPO0, DISABLE_TRACE_COMP, 8, 1) 57c859b566SAlistair Francis FIELD(GPO0, PIT3_PRESCALE, 7, 1) 58c859b566SAlistair Francis FIELD(GPO0, PIT2_PRESCALE, 5, 2) 59c859b566SAlistair Francis FIELD(GPO0, PIT1_PRESCALE, 3, 2) 60c859b566SAlistair Francis FIELD(GPO0, PIT0_PRESCALE, 1, 2) 61c859b566SAlistair Francis FIELD(GPO0, DEBUG_REMAP, 0, 1) 62c859b566SAlistair Francis REG32(GPO1, 0x14) 63c859b566SAlistair Francis FIELD(GPO1, MIO_5, 5, 1) 64c859b566SAlistair Francis FIELD(GPO1, MIO_4, 4, 1) 65c859b566SAlistair Francis FIELD(GPO1, MIO_3, 3, 1) 66c859b566SAlistair Francis FIELD(GPO1, MIO_2, 2, 1) 67c859b566SAlistair Francis FIELD(GPO1, MIO_1, 1, 1) 68c859b566SAlistair Francis FIELD(GPO1, MIO_0, 0, 1) 69c859b566SAlistair Francis REG32(GPO2, 0x18) 70c859b566SAlistair Francis FIELD(GPO2, DAP_RPU_WAKE_ACK, 9, 1) 71c859b566SAlistair Francis FIELD(GPO2, DAP_FP_WAKE_ACK, 8, 1) 72c859b566SAlistair Francis FIELD(GPO2, PS_STATUS, 7, 1) 73c859b566SAlistair Francis FIELD(GPO2, PCAP_EN, 6, 1) 74c859b566SAlistair Francis REG32(GPO3, 0x1c) 75c859b566SAlistair Francis FIELD(GPO3, PL_GPO_31, 31, 1) 76c859b566SAlistair Francis FIELD(GPO3, PL_GPO_30, 30, 1) 77c859b566SAlistair Francis FIELD(GPO3, PL_GPO_29, 29, 1) 78c859b566SAlistair Francis FIELD(GPO3, PL_GPO_28, 28, 1) 79c859b566SAlistair Francis FIELD(GPO3, PL_GPO_27, 27, 1) 80c859b566SAlistair Francis FIELD(GPO3, PL_GPO_26, 26, 1) 81c859b566SAlistair Francis FIELD(GPO3, PL_GPO_25, 25, 1) 82c859b566SAlistair Francis FIELD(GPO3, PL_GPO_24, 24, 1) 83c859b566SAlistair Francis FIELD(GPO3, PL_GPO_23, 23, 1) 84c859b566SAlistair Francis FIELD(GPO3, PL_GPO_22, 22, 1) 85c859b566SAlistair Francis FIELD(GPO3, PL_GPO_21, 21, 1) 86c859b566SAlistair Francis FIELD(GPO3, PL_GPO_20, 20, 1) 87c859b566SAlistair Francis FIELD(GPO3, PL_GPO_19, 19, 1) 88c859b566SAlistair Francis FIELD(GPO3, PL_GPO_18, 18, 1) 89c859b566SAlistair Francis FIELD(GPO3, PL_GPO_17, 17, 1) 90c859b566SAlistair Francis FIELD(GPO3, PL_GPO_16, 16, 1) 91c859b566SAlistair Francis FIELD(GPO3, PL_GPO_15, 15, 1) 92c859b566SAlistair Francis FIELD(GPO3, PL_GPO_14, 14, 1) 93c859b566SAlistair Francis FIELD(GPO3, PL_GPO_13, 13, 1) 94c859b566SAlistair Francis FIELD(GPO3, PL_GPO_12, 12, 1) 95c859b566SAlistair Francis FIELD(GPO3, PL_GPO_11, 11, 1) 96c859b566SAlistair Francis FIELD(GPO3, PL_GPO_10, 10, 1) 97c859b566SAlistair Francis FIELD(GPO3, PL_GPO_9, 9, 1) 98c859b566SAlistair Francis FIELD(GPO3, PL_GPO_8, 8, 1) 99c859b566SAlistair Francis FIELD(GPO3, PL_GPO_7, 7, 1) 100c859b566SAlistair Francis FIELD(GPO3, PL_GPO_6, 6, 1) 101c859b566SAlistair Francis FIELD(GPO3, PL_GPO_5, 5, 1) 102c859b566SAlistair Francis FIELD(GPO3, PL_GPO_4, 4, 1) 103c859b566SAlistair Francis FIELD(GPO3, PL_GPO_3, 3, 1) 104c859b566SAlistair Francis FIELD(GPO3, PL_GPO_2, 2, 1) 105c859b566SAlistair Francis FIELD(GPO3, PL_GPO_1, 1, 1) 106c859b566SAlistair Francis FIELD(GPO3, PL_GPO_0, 0, 1) 107c859b566SAlistair Francis REG32(GPI0, 0x20) 108c859b566SAlistair Francis FIELD(GPI0, RFT_ECC_FATAL_ERR, 31, 1) 109c859b566SAlistair Francis FIELD(GPI0, RFT_VOTER_ERR, 30, 1) 110c859b566SAlistair Francis FIELD(GPI0, RFT_COMPARE_ERR_23, 29, 1) 111c859b566SAlistair Francis FIELD(GPI0, RFT_COMPARE_ERR_13, 28, 1) 112c859b566SAlistair Francis FIELD(GPI0, RFT_COMPARE_ERR_12, 27, 1) 113c859b566SAlistair Francis FIELD(GPI0, RFT_LS_MISMATCH_23_B, 26, 1) 114c859b566SAlistair Francis FIELD(GPI0, RFT_LS_MISMATCH_13_B, 25, 1) 115c859b566SAlistair Francis FIELD(GPI0, RFT_LS_MISMATCH_12_B, 24, 1) 116c859b566SAlistair Francis FIELD(GPI0, RFT_MISMATCH_STATE, 23, 1) 117c859b566SAlistair Francis FIELD(GPI0, RFT_MISMATCH_CPU, 22, 1) 118c859b566SAlistair Francis FIELD(GPI0, RFT_SLEEP_RESET, 19, 1) 119c859b566SAlistair Francis FIELD(GPI0, RFT_LS_MISMATCH_23_A, 18, 1) 120c859b566SAlistair Francis FIELD(GPI0, RFT_LS_MISMATCH_13_A, 17, 1) 121c859b566SAlistair Francis FIELD(GPI0, RFT_LS_MISMATCH_12_A, 16, 1) 122c859b566SAlistair Francis FIELD(GPI0, NFT_ECC_FATAL_ERR, 15, 1) 123c859b566SAlistair Francis FIELD(GPI0, NFT_VOTER_ERR, 14, 1) 124c859b566SAlistair Francis FIELD(GPI0, NFT_COMPARE_ERR_23, 13, 1) 125c859b566SAlistair Francis FIELD(GPI0, NFT_COMPARE_ERR_13, 12, 1) 126c859b566SAlistair Francis FIELD(GPI0, NFT_COMPARE_ERR_12, 11, 1) 127c859b566SAlistair Francis FIELD(GPI0, NFT_LS_MISMATCH_23_B, 10, 1) 128c859b566SAlistair Francis FIELD(GPI0, NFT_LS_MISMATCH_13_B, 9, 1) 129c859b566SAlistair Francis FIELD(GPI0, NFT_LS_MISMATCH_12_B, 8, 1) 130c859b566SAlistair Francis FIELD(GPI0, NFT_MISMATCH_STATE, 7, 1) 131c859b566SAlistair Francis FIELD(GPI0, NFT_MISMATCH_CPU, 6, 1) 132c859b566SAlistair Francis FIELD(GPI0, NFT_SLEEP_RESET, 3, 1) 133c859b566SAlistair Francis FIELD(GPI0, NFT_LS_MISMATCH_23_A, 2, 1) 134c859b566SAlistair Francis FIELD(GPI0, NFT_LS_MISMATCH_13_A, 1, 1) 135c859b566SAlistair Francis FIELD(GPI0, NFT_LS_MISMATCH_12_A, 0, 1) 136c859b566SAlistair Francis REG32(GPI1, 0x24) 137c859b566SAlistair Francis FIELD(GPI1, APB_AIB_ERROR, 31, 1) 138c859b566SAlistair Francis FIELD(GPI1, AXI_AIB_ERROR, 30, 1) 139c859b566SAlistair Francis FIELD(GPI1, ERROR_2, 29, 1) 140c859b566SAlistair Francis FIELD(GPI1, ERROR_1, 28, 1) 141c859b566SAlistair Francis FIELD(GPI1, ACPU_3_DBG_PWRUP, 23, 1) 142c859b566SAlistair Francis FIELD(GPI1, ACPU_2_DBG_PWRUP, 22, 1) 143c859b566SAlistair Francis FIELD(GPI1, ACPU_1_DBG_PWRUP, 21, 1) 144c859b566SAlistair Francis FIELD(GPI1, ACPU_0_DBG_PWRUP, 20, 1) 145c859b566SAlistair Francis FIELD(GPI1, FPD_WAKE_GIC_PROXY, 16, 1) 146c859b566SAlistair Francis FIELD(GPI1, MIO_WAKE_5, 15, 1) 147c859b566SAlistair Francis FIELD(GPI1, MIO_WAKE_4, 14, 1) 148c859b566SAlistair Francis FIELD(GPI1, MIO_WAKE_3, 13, 1) 149c859b566SAlistair Francis FIELD(GPI1, MIO_WAKE_2, 12, 1) 150c859b566SAlistair Francis FIELD(GPI1, MIO_WAKE_1, 11, 1) 151c859b566SAlistair Francis FIELD(GPI1, MIO_WAKE_0, 10, 1) 152c859b566SAlistair Francis FIELD(GPI1, DAP_RPU_WAKE, 9, 1) 153c859b566SAlistair Francis FIELD(GPI1, DAP_FPD_WAKE, 8, 1) 154c859b566SAlistair Francis FIELD(GPI1, USB_1_WAKE, 7, 1) 155c859b566SAlistair Francis FIELD(GPI1, USB_0_WAKE, 6, 1) 156c859b566SAlistair Francis FIELD(GPI1, R5_1_WAKE, 5, 1) 157c859b566SAlistair Francis FIELD(GPI1, R5_0_WAKE, 4, 1) 158c859b566SAlistair Francis FIELD(GPI1, ACPU_3_WAKE, 3, 1) 159c859b566SAlistair Francis FIELD(GPI1, ACPU_2_WAKE, 2, 1) 160c859b566SAlistair Francis FIELD(GPI1, ACPU_1_WAKE, 1, 1) 161c859b566SAlistair Francis FIELD(GPI1, ACPU_0_WAKE, 0, 1) 162c859b566SAlistair Francis REG32(GPI2, 0x28) 163c859b566SAlistair Francis FIELD(GPI2, VCC_INT_FP_DISCONNECT, 31, 1) 164c859b566SAlistair Francis FIELD(GPI2, VCC_INT_DISCONNECT, 30, 1) 165c859b566SAlistair Francis FIELD(GPI2, VCC_AUX_DISCONNECT, 29, 1) 166c859b566SAlistair Francis FIELD(GPI2, DBG_ACPU3_RST_REQ, 23, 1) 167c859b566SAlistair Francis FIELD(GPI2, DBG_ACPU2_RST_REQ, 22, 1) 168c859b566SAlistair Francis FIELD(GPI2, DBG_ACPU1_RST_REQ, 21, 1) 169c859b566SAlistair Francis FIELD(GPI2, DBG_ACPU0_RST_REQ, 20, 1) 170c859b566SAlistair Francis FIELD(GPI2, CP_ACPU3_RST_REQ, 19, 1) 171c859b566SAlistair Francis FIELD(GPI2, CP_ACPU2_RST_REQ, 18, 1) 172c859b566SAlistair Francis FIELD(GPI2, CP_ACPU1_RST_REQ, 17, 1) 173c859b566SAlistair Francis FIELD(GPI2, CP_ACPU0_RST_REQ, 16, 1) 174c859b566SAlistair Francis FIELD(GPI2, DBG_RCPU1_RST_REQ, 9, 1) 175c859b566SAlistair Francis FIELD(GPI2, DBG_RCPU0_RST_REQ, 8, 1) 176c859b566SAlistair Francis FIELD(GPI2, R5_1_SLEEP, 5, 1) 177c859b566SAlistair Francis FIELD(GPI2, R5_0_SLEEP, 4, 1) 178c859b566SAlistair Francis FIELD(GPI2, ACPU_3_SLEEP, 3, 1) 179c859b566SAlistair Francis FIELD(GPI2, ACPU_2_SLEEP, 2, 1) 180c859b566SAlistair Francis FIELD(GPI2, ACPU_1_SLEEP, 1, 1) 181c859b566SAlistair Francis FIELD(GPI2, ACPU_0_SLEEP, 0, 1) 182c859b566SAlistair Francis REG32(GPI3, 0x2c) 183c859b566SAlistair Francis FIELD(GPI3, PL_GPI_31, 31, 1) 184c859b566SAlistair Francis FIELD(GPI3, PL_GPI_30, 30, 1) 185c859b566SAlistair Francis FIELD(GPI3, PL_GPI_29, 29, 1) 186c859b566SAlistair Francis FIELD(GPI3, PL_GPI_28, 28, 1) 187c859b566SAlistair Francis FIELD(GPI3, PL_GPI_27, 27, 1) 188c859b566SAlistair Francis FIELD(GPI3, PL_GPI_26, 26, 1) 189c859b566SAlistair Francis FIELD(GPI3, PL_GPI_25, 25, 1) 190c859b566SAlistair Francis FIELD(GPI3, PL_GPI_24, 24, 1) 191c859b566SAlistair Francis FIELD(GPI3, PL_GPI_23, 23, 1) 192c859b566SAlistair Francis FIELD(GPI3, PL_GPI_22, 22, 1) 193c859b566SAlistair Francis FIELD(GPI3, PL_GPI_21, 21, 1) 194c859b566SAlistair Francis FIELD(GPI3, PL_GPI_20, 20, 1) 195c859b566SAlistair Francis FIELD(GPI3, PL_GPI_19, 19, 1) 196c859b566SAlistair Francis FIELD(GPI3, PL_GPI_18, 18, 1) 197c859b566SAlistair Francis FIELD(GPI3, PL_GPI_17, 17, 1) 198c859b566SAlistair Francis FIELD(GPI3, PL_GPI_16, 16, 1) 199c859b566SAlistair Francis FIELD(GPI3, PL_GPI_15, 15, 1) 200c859b566SAlistair Francis FIELD(GPI3, PL_GPI_14, 14, 1) 201c859b566SAlistair Francis FIELD(GPI3, PL_GPI_13, 13, 1) 202c859b566SAlistair Francis FIELD(GPI3, PL_GPI_12, 12, 1) 203c859b566SAlistair Francis FIELD(GPI3, PL_GPI_11, 11, 1) 204c859b566SAlistair Francis FIELD(GPI3, PL_GPI_10, 10, 1) 205c859b566SAlistair Francis FIELD(GPI3, PL_GPI_9, 9, 1) 206c859b566SAlistair Francis FIELD(GPI3, PL_GPI_8, 8, 1) 207c859b566SAlistair Francis FIELD(GPI3, PL_GPI_7, 7, 1) 208c859b566SAlistair Francis FIELD(GPI3, PL_GPI_6, 6, 1) 209c859b566SAlistair Francis FIELD(GPI3, PL_GPI_5, 5, 1) 210c859b566SAlistair Francis FIELD(GPI3, PL_GPI_4, 4, 1) 211c859b566SAlistair Francis FIELD(GPI3, PL_GPI_3, 3, 1) 212c859b566SAlistair Francis FIELD(GPI3, PL_GPI_2, 2, 1) 213c859b566SAlistair Francis FIELD(GPI3, PL_GPI_1, 1, 1) 214c859b566SAlistair Francis FIELD(GPI3, PL_GPI_0, 0, 1) 215c859b566SAlistair Francis REG32(IRQ_STATUS, 0x30) 216c859b566SAlistair Francis FIELD(IRQ_STATUS, CSU_PMU_SEC_LOCK, 31, 1) 217c859b566SAlistair Francis FIELD(IRQ_STATUS, INV_ADDR, 29, 1) 218c859b566SAlistair Francis FIELD(IRQ_STATUS, PWR_DN_REQ, 28, 1) 219c859b566SAlistair Francis FIELD(IRQ_STATUS, PWR_UP_REQ, 27, 1) 220c859b566SAlistair Francis FIELD(IRQ_STATUS, SW_RST_REQ, 26, 1) 221c859b566SAlistair Francis FIELD(IRQ_STATUS, HW_RST_REQ, 25, 1) 222c859b566SAlistair Francis FIELD(IRQ_STATUS, ISO_REQ, 24, 1) 223c859b566SAlistair Francis FIELD(IRQ_STATUS, FW_REQ, 23, 1) 224c859b566SAlistair Francis FIELD(IRQ_STATUS, IPI3, 22, 1) 225c859b566SAlistair Francis FIELD(IRQ_STATUS, IPI2, 21, 1) 226c859b566SAlistair Francis FIELD(IRQ_STATUS, IPI1, 20, 1) 227c859b566SAlistair Francis FIELD(IRQ_STATUS, IPI0, 19, 1) 228c859b566SAlistair Francis FIELD(IRQ_STATUS, RTC_ALARM, 18, 1) 229c859b566SAlistair Francis FIELD(IRQ_STATUS, RTC_EVERY_SECOND, 17, 1) 230c859b566SAlistair Francis FIELD(IRQ_STATUS, CORRECTABLE_ECC, 16, 1) 231c859b566SAlistair Francis FIELD(IRQ_STATUS, GPI3, 14, 1) 232c859b566SAlistair Francis FIELD(IRQ_STATUS, GPI2, 13, 1) 233c859b566SAlistair Francis FIELD(IRQ_STATUS, GPI1, 12, 1) 234c859b566SAlistair Francis FIELD(IRQ_STATUS, GPI0, 11, 1) 235c859b566SAlistair Francis FIELD(IRQ_STATUS, PIT3, 6, 1) 236c859b566SAlistair Francis FIELD(IRQ_STATUS, PIT2, 5, 1) 237c859b566SAlistair Francis FIELD(IRQ_STATUS, PIT1, 4, 1) 238c859b566SAlistair Francis FIELD(IRQ_STATUS, PIT0, 3, 1) 239c859b566SAlistair Francis REG32(IRQ_PENDING, 0x34) 240c859b566SAlistair Francis FIELD(IRQ_PENDING, CSU_PMU_SEC_LOCK, 31, 1) 241c859b566SAlistair Francis FIELD(IRQ_PENDING, INV_ADDR, 29, 1) 242c859b566SAlistair Francis FIELD(IRQ_PENDING, PWR_DN_REQ, 28, 1) 243c859b566SAlistair Francis FIELD(IRQ_PENDING, PWR_UP_REQ, 27, 1) 244c859b566SAlistair Francis FIELD(IRQ_PENDING, SW_RST_REQ, 26, 1) 245c859b566SAlistair Francis FIELD(IRQ_PENDING, HW_RST_REQ, 25, 1) 246c859b566SAlistair Francis FIELD(IRQ_PENDING, ISO_REQ, 24, 1) 247c859b566SAlistair Francis FIELD(IRQ_PENDING, FW_REQ, 23, 1) 248c859b566SAlistair Francis FIELD(IRQ_PENDING, IPI3, 22, 1) 249c859b566SAlistair Francis FIELD(IRQ_PENDING, IPI2, 21, 1) 250c859b566SAlistair Francis FIELD(IRQ_PENDING, IPI1, 20, 1) 251c859b566SAlistair Francis FIELD(IRQ_PENDING, IPI0, 19, 1) 252c859b566SAlistair Francis FIELD(IRQ_PENDING, RTC_ALARM, 18, 1) 253c859b566SAlistair Francis FIELD(IRQ_PENDING, RTC_EVERY_SECOND, 17, 1) 254c859b566SAlistair Francis FIELD(IRQ_PENDING, CORRECTABLE_ECC, 16, 1) 255c859b566SAlistair Francis FIELD(IRQ_PENDING, GPI3, 14, 1) 256c859b566SAlistair Francis FIELD(IRQ_PENDING, GPI2, 13, 1) 257c859b566SAlistair Francis FIELD(IRQ_PENDING, GPI1, 12, 1) 258c859b566SAlistair Francis FIELD(IRQ_PENDING, GPI0, 11, 1) 259c859b566SAlistair Francis FIELD(IRQ_PENDING, PIT3, 6, 1) 260c859b566SAlistair Francis FIELD(IRQ_PENDING, PIT2, 5, 1) 261c859b566SAlistair Francis FIELD(IRQ_PENDING, PIT1, 4, 1) 262c859b566SAlistair Francis FIELD(IRQ_PENDING, PIT0, 3, 1) 263c859b566SAlistair Francis REG32(IRQ_ENABLE, 0x38) 264c859b566SAlistair Francis FIELD(IRQ_ENABLE, CSU_PMU_SEC_LOCK, 31, 1) 265c859b566SAlistair Francis FIELD(IRQ_ENABLE, INV_ADDR, 29, 1) 266c859b566SAlistair Francis FIELD(IRQ_ENABLE, PWR_DN_REQ, 28, 1) 267c859b566SAlistair Francis FIELD(IRQ_ENABLE, PWR_UP_REQ, 27, 1) 268c859b566SAlistair Francis FIELD(IRQ_ENABLE, SW_RST_REQ, 26, 1) 269c859b566SAlistair Francis FIELD(IRQ_ENABLE, HW_RST_REQ, 25, 1) 270c859b566SAlistair Francis FIELD(IRQ_ENABLE, ISO_REQ, 24, 1) 271c859b566SAlistair Francis FIELD(IRQ_ENABLE, FW_REQ, 23, 1) 272c859b566SAlistair Francis FIELD(IRQ_ENABLE, IPI3, 22, 1) 273c859b566SAlistair Francis FIELD(IRQ_ENABLE, IPI2, 21, 1) 274c859b566SAlistair Francis FIELD(IRQ_ENABLE, IPI1, 20, 1) 275c859b566SAlistair Francis FIELD(IRQ_ENABLE, IPI0, 19, 1) 276c859b566SAlistair Francis FIELD(IRQ_ENABLE, RTC_ALARM, 18, 1) 277c859b566SAlistair Francis FIELD(IRQ_ENABLE, RTC_EVERY_SECOND, 17, 1) 278c859b566SAlistair Francis FIELD(IRQ_ENABLE, CORRECTABLE_ECC, 16, 1) 279c859b566SAlistair Francis FIELD(IRQ_ENABLE, GPI3, 14, 1) 280c859b566SAlistair Francis FIELD(IRQ_ENABLE, GPI2, 13, 1) 281c859b566SAlistair Francis FIELD(IRQ_ENABLE, GPI1, 12, 1) 282c859b566SAlistair Francis FIELD(IRQ_ENABLE, GPI0, 11, 1) 283c859b566SAlistair Francis FIELD(IRQ_ENABLE, PIT3, 6, 1) 284c859b566SAlistair Francis FIELD(IRQ_ENABLE, PIT2, 5, 1) 285c859b566SAlistair Francis FIELD(IRQ_ENABLE, PIT1, 4, 1) 286c859b566SAlistair Francis FIELD(IRQ_ENABLE, PIT0, 3, 1) 287c859b566SAlistair Francis REG32(IRQ_ACK, 0x3c) 288c859b566SAlistair Francis FIELD(IRQ_ACK, CSU_PMU_SEC_LOCK, 31, 1) 289c859b566SAlistair Francis FIELD(IRQ_ACK, INV_ADDR, 29, 1) 290c859b566SAlistair Francis FIELD(IRQ_ACK, PWR_DN_REQ, 28, 1) 291c859b566SAlistair Francis FIELD(IRQ_ACK, PWR_UP_REQ, 27, 1) 292c859b566SAlistair Francis FIELD(IRQ_ACK, SW_RST_REQ, 26, 1) 293c859b566SAlistair Francis FIELD(IRQ_ACK, HW_RST_REQ, 25, 1) 294c859b566SAlistair Francis FIELD(IRQ_ACK, ISO_REQ, 24, 1) 295c859b566SAlistair Francis FIELD(IRQ_ACK, FW_REQ, 23, 1) 296c859b566SAlistair Francis FIELD(IRQ_ACK, IPI3, 22, 1) 297c859b566SAlistair Francis FIELD(IRQ_ACK, IPI2, 21, 1) 298c859b566SAlistair Francis FIELD(IRQ_ACK, IPI1, 20, 1) 299c859b566SAlistair Francis FIELD(IRQ_ACK, IPI0, 19, 1) 300c859b566SAlistair Francis FIELD(IRQ_ACK, RTC_ALARM, 18, 1) 301c859b566SAlistair Francis FIELD(IRQ_ACK, RTC_EVERY_SECOND, 17, 1) 302c859b566SAlistair Francis FIELD(IRQ_ACK, CORRECTABLE_ECC, 16, 1) 303c859b566SAlistair Francis FIELD(IRQ_ACK, GPI3, 14, 1) 304c859b566SAlistair Francis FIELD(IRQ_ACK, GPI2, 13, 1) 305c859b566SAlistair Francis FIELD(IRQ_ACK, GPI1, 12, 1) 306c859b566SAlistair Francis FIELD(IRQ_ACK, GPI0, 11, 1) 307c859b566SAlistair Francis FIELD(IRQ_ACK, PIT3, 6, 1) 308c859b566SAlistair Francis FIELD(IRQ_ACK, PIT2, 5, 1) 309c859b566SAlistair Francis FIELD(IRQ_ACK, PIT1, 4, 1) 310c859b566SAlistair Francis FIELD(IRQ_ACK, PIT0, 3, 1) 311c859b566SAlistair Francis REG32(PIT0_PRELOAD, 0x40) 312c859b566SAlistair Francis REG32(PIT0_COUNTER, 0x44) 313c859b566SAlistair Francis REG32(PIT0_CONTROL, 0x48) 314c859b566SAlistair Francis FIELD(PIT0_CONTROL, PRELOAD, 1, 1) 315c859b566SAlistair Francis FIELD(PIT0_CONTROL, EN, 0, 1) 316c859b566SAlistair Francis REG32(PIT1_PRELOAD, 0x50) 317c859b566SAlistair Francis REG32(PIT1_COUNTER, 0x54) 318c859b566SAlistair Francis REG32(PIT1_CONTROL, 0x58) 319c859b566SAlistair Francis FIELD(PIT1_CONTROL, PRELOAD, 1, 1) 320c859b566SAlistair Francis FIELD(PIT1_CONTROL, EN, 0, 1) 321c859b566SAlistair Francis REG32(PIT2_PRELOAD, 0x60) 322c859b566SAlistair Francis REG32(PIT2_COUNTER, 0x64) 323c859b566SAlistair Francis REG32(PIT2_CONTROL, 0x68) 324c859b566SAlistair Francis FIELD(PIT2_CONTROL, PRELOAD, 1, 1) 325c859b566SAlistair Francis FIELD(PIT2_CONTROL, EN, 0, 1) 326c859b566SAlistair Francis REG32(PIT3_PRELOAD, 0x70) 327c859b566SAlistair Francis REG32(PIT3_COUNTER, 0x74) 328c859b566SAlistair Francis REG32(PIT3_CONTROL, 0x78) 329c859b566SAlistair Francis FIELD(PIT3_CONTROL, PRELOAD, 1, 1) 330c859b566SAlistair Francis FIELD(PIT3_CONTROL, EN, 0, 1) 331c859b566SAlistair Francis 332c859b566SAlistair Francis static void xlnx_pmu_io_irq_update(XlnxPMUIOIntc *s) 333c859b566SAlistair Francis { 334c859b566SAlistair Francis bool irq_out; 335c859b566SAlistair Francis 336c859b566SAlistair Francis s->regs[R_IRQ_PENDING] = s->regs[R_IRQ_STATUS] & s->regs[R_IRQ_ENABLE]; 337c859b566SAlistair Francis irq_out = !!s->regs[R_IRQ_PENDING]; 338c859b566SAlistair Francis 339c859b566SAlistair Francis DB_PRINT("Setting IRQ output = %d\n", irq_out); 340c859b566SAlistair Francis 341c859b566SAlistair Francis qemu_set_irq(s->parent_irq, irq_out); 342c859b566SAlistair Francis } 343c859b566SAlistair Francis 344c859b566SAlistair Francis static void xlnx_pmu_io_irq_enable_postw(RegisterInfo *reg, uint64_t val64) 345c859b566SAlistair Francis { 346c859b566SAlistair Francis XlnxPMUIOIntc *s = XLNX_PMU_IO_INTC(reg->opaque); 347c859b566SAlistair Francis 348c859b566SAlistair Francis xlnx_pmu_io_irq_update(s); 349c859b566SAlistair Francis } 350c859b566SAlistair Francis 351c859b566SAlistair Francis static void xlnx_pmu_io_irq_ack_postw(RegisterInfo *reg, uint64_t val64) 352c859b566SAlistair Francis { 353c859b566SAlistair Francis XlnxPMUIOIntc *s = XLNX_PMU_IO_INTC(reg->opaque); 354c859b566SAlistair Francis uint32_t val = val64; 355c859b566SAlistair Francis 356c859b566SAlistair Francis /* Only clear */ 357c859b566SAlistair Francis val &= s->regs[R_IRQ_STATUS]; 358c859b566SAlistair Francis s->regs[R_IRQ_STATUS] ^= val; 359c859b566SAlistair Francis 360c859b566SAlistair Francis /* Active level triggered interrupts stay high. */ 361c859b566SAlistair Francis s->regs[R_IRQ_STATUS] |= s->irq_raw & ~s->cfg.level_edge; 362c859b566SAlistair Francis 363c859b566SAlistair Francis xlnx_pmu_io_irq_update(s); 364c859b566SAlistair Francis } 365c859b566SAlistair Francis 366c859b566SAlistair Francis static const RegisterAccessInfo xlnx_pmu_io_intc_regs_info[] = { 367c859b566SAlistair Francis { .name = "IRQ_MODE", .addr = A_IRQ_MODE, 368c859b566SAlistair Francis .rsvd = 0xffffffff, 369c859b566SAlistair Francis },{ .name = "GPO0", .addr = A_GPO0, 370c859b566SAlistair Francis },{ .name = "GPO1", .addr = A_GPO1, 371c859b566SAlistair Francis .rsvd = 0xffffffc0, 372c859b566SAlistair Francis },{ .name = "GPO2", .addr = A_GPO2, 373c859b566SAlistair Francis .rsvd = 0xfffffc3f, 374c859b566SAlistair Francis },{ .name = "GPO3", .addr = A_GPO3, 375c859b566SAlistair Francis },{ .name = "GPI0", .addr = A_GPI0, 376c859b566SAlistair Francis .rsvd = 0x300030, 377c859b566SAlistair Francis .ro = 0xffcfffcf, 378c859b566SAlistair Francis },{ .name = "GPI1", .addr = A_GPI1, 379c859b566SAlistair Francis .rsvd = 0xf0e0000, 380c859b566SAlistair Francis .ro = 0xf0f1ffff, 381c859b566SAlistair Francis },{ .name = "GPI2", .addr = A_GPI2, 382c859b566SAlistair Francis .rsvd = 0x1f00fcc0, 383c859b566SAlistair Francis .ro = 0xe0ff033f, 384c859b566SAlistair Francis },{ .name = "GPI3", .addr = A_GPI3, 385c859b566SAlistair Francis .ro = 0xffffffff, 386c859b566SAlistair Francis },{ .name = "IRQ_STATUS", .addr = A_IRQ_STATUS, 387c859b566SAlistair Francis .rsvd = 0x40008787, 388c859b566SAlistair Francis .ro = 0xbfff7878, 389c859b566SAlistair Francis },{ .name = "IRQ_PENDING", .addr = A_IRQ_PENDING, 390c859b566SAlistair Francis .rsvd = 0x40008787, 391c859b566SAlistair Francis .ro = 0xdfff7ff8, 392c859b566SAlistair Francis },{ .name = "IRQ_ENABLE", .addr = A_IRQ_ENABLE, 393c859b566SAlistair Francis .rsvd = 0x40008787, 394c859b566SAlistair Francis .ro = 0x7800, 395c859b566SAlistair Francis .post_write = xlnx_pmu_io_irq_enable_postw, 396c859b566SAlistair Francis },{ .name = "IRQ_ACK", .addr = A_IRQ_ACK, 397c859b566SAlistair Francis .rsvd = 0x40008787, 398c859b566SAlistair Francis .post_write = xlnx_pmu_io_irq_ack_postw, 399c859b566SAlistair Francis },{ .name = "PIT0_PRELOAD", .addr = A_PIT0_PRELOAD, 400c859b566SAlistair Francis .ro = 0xffffffff, 401c859b566SAlistair Francis },{ .name = "PIT0_COUNTER", .addr = A_PIT0_COUNTER, 402c859b566SAlistair Francis .ro = 0xffffffff, 403c859b566SAlistair Francis },{ .name = "PIT0_CONTROL", .addr = A_PIT0_CONTROL, 404c859b566SAlistair Francis .rsvd = 0xfffffffc, 405c859b566SAlistair Francis },{ .name = "PIT1_PRELOAD", .addr = A_PIT1_PRELOAD, 406c859b566SAlistair Francis .ro = 0xffffffff, 407c859b566SAlistair Francis },{ .name = "PIT1_COUNTER", .addr = A_PIT1_COUNTER, 408c859b566SAlistair Francis .ro = 0xffffffff, 409c859b566SAlistair Francis },{ .name = "PIT1_CONTROL", .addr = A_PIT1_CONTROL, 410c859b566SAlistair Francis .rsvd = 0xfffffffc, 411c859b566SAlistair Francis },{ .name = "PIT2_PRELOAD", .addr = A_PIT2_PRELOAD, 412c859b566SAlistair Francis .ro = 0xffffffff, 413c859b566SAlistair Francis },{ .name = "PIT2_COUNTER", .addr = A_PIT2_COUNTER, 414c859b566SAlistair Francis .ro = 0xffffffff, 415c859b566SAlistair Francis },{ .name = "PIT2_CONTROL", .addr = A_PIT2_CONTROL, 416c859b566SAlistair Francis .rsvd = 0xfffffffc, 417c859b566SAlistair Francis },{ .name = "PIT3_PRELOAD", .addr = A_PIT3_PRELOAD, 418c859b566SAlistair Francis .ro = 0xffffffff, 419c859b566SAlistair Francis },{ .name = "PIT3_COUNTER", .addr = A_PIT3_COUNTER, 420c859b566SAlistair Francis .ro = 0xffffffff, 421c859b566SAlistair Francis },{ .name = "PIT3_CONTROL", .addr = A_PIT3_CONTROL, 422c859b566SAlistair Francis .rsvd = 0xfffffffc, 423c859b566SAlistair Francis } 424c859b566SAlistair Francis }; 425c859b566SAlistair Francis 426c859b566SAlistair Francis static void irq_handler(void *opaque, int irq, int level) 427c859b566SAlistair Francis { 428c859b566SAlistair Francis XlnxPMUIOIntc *s = XLNX_PMU_IO_INTC(opaque); 429c859b566SAlistair Francis uint32_t mask = 1 << irq; 430c859b566SAlistair Francis uint32_t prev = s->irq_raw; 431c859b566SAlistair Francis uint32_t temp; 432c859b566SAlistair Francis 433c859b566SAlistair Francis s->irq_raw &= ~mask; 434c859b566SAlistair Francis s->irq_raw |= (!!level) << irq; 435c859b566SAlistair Francis 436c859b566SAlistair Francis /* Turn active-low into active-high. */ 437c859b566SAlistair Francis s->irq_raw ^= (~s->cfg.positive); 438c859b566SAlistair Francis s->irq_raw &= mask; 439c859b566SAlistair Francis 440c859b566SAlistair Francis if (s->cfg.level_edge & mask) { 441c859b566SAlistair Francis /* Edge triggered. */ 442c859b566SAlistair Francis temp = (prev ^ s->irq_raw) & s->irq_raw; 443c859b566SAlistair Francis } else { 444c859b566SAlistair Francis /* Level triggered. */ 445c859b566SAlistair Francis temp = s->irq_raw; 446c859b566SAlistair Francis } 447c859b566SAlistair Francis s->regs[R_IRQ_STATUS] |= temp; 448c859b566SAlistair Francis 449c859b566SAlistair Francis xlnx_pmu_io_irq_update(s); 450c859b566SAlistair Francis } 451c859b566SAlistair Francis 452c859b566SAlistair Francis static void xlnx_pmu_io_intc_reset(DeviceState *dev) 453c859b566SAlistair Francis { 454c859b566SAlistair Francis XlnxPMUIOIntc *s = XLNX_PMU_IO_INTC(dev); 455c859b566SAlistair Francis unsigned int i; 456c859b566SAlistair Francis 457c859b566SAlistair Francis for (i = 0; i < ARRAY_SIZE(s->regs_info); ++i) { 458c859b566SAlistair Francis register_reset(&s->regs_info[i]); 459c859b566SAlistair Francis } 460c859b566SAlistair Francis 461c859b566SAlistair Francis xlnx_pmu_io_irq_update(s); 462c859b566SAlistair Francis } 463c859b566SAlistair Francis 464c859b566SAlistair Francis static const MemoryRegionOps xlnx_pmu_io_intc_ops = { 465c859b566SAlistair Francis .read = register_read_memory, 466c859b566SAlistair Francis .write = register_write_memory, 467c859b566SAlistair Francis .endianness = DEVICE_LITTLE_ENDIAN, 468c859b566SAlistair Francis .valid = { 469c859b566SAlistair Francis .min_access_size = 4, 470c859b566SAlistair Francis .max_access_size = 4, 471c859b566SAlistair Francis }, 472c859b566SAlistair Francis }; 473c859b566SAlistair Francis 474c859b566SAlistair Francis static Property xlnx_pmu_io_intc_properties[] = { 475c859b566SAlistair Francis DEFINE_PROP_UINT32("intc-intr-size", XlnxPMUIOIntc, cfg.intr_size, 0), 476c859b566SAlistair Francis DEFINE_PROP_UINT32("intc-level-edge", XlnxPMUIOIntc, cfg.level_edge, 0), 477c859b566SAlistair Francis DEFINE_PROP_UINT32("intc-positive", XlnxPMUIOIntc, cfg.positive, 0), 478c859b566SAlistair Francis DEFINE_PROP_END_OF_LIST(), 479c859b566SAlistair Francis }; 480c859b566SAlistair Francis 481c859b566SAlistair Francis static void xlnx_pmu_io_intc_realize(DeviceState *dev, Error **errp) 482c859b566SAlistair Francis { 483c859b566SAlistair Francis XlnxPMUIOIntc *s = XLNX_PMU_IO_INTC(dev); 484c859b566SAlistair Francis 485c859b566SAlistair Francis /* Internal interrupts are edge triggered */ 486c859b566SAlistair Francis s->cfg.level_edge <<= 16; 487c859b566SAlistair Francis s->cfg.level_edge |= 0xffff; 488c859b566SAlistair Francis 489c859b566SAlistair Francis /* Internal interrupts are positive. */ 490c859b566SAlistair Francis s->cfg.positive <<= 16; 491c859b566SAlistair Francis s->cfg.positive |= 0xffff; 492c859b566SAlistair Francis 493c859b566SAlistair Francis /* Max 16 external interrupts. */ 494c859b566SAlistair Francis assert(s->cfg.intr_size <= 16); 495c859b566SAlistair Francis 496c859b566SAlistair Francis qdev_init_gpio_in(dev, irq_handler, 16 + s->cfg.intr_size); 497c859b566SAlistair Francis } 498c859b566SAlistair Francis 499c859b566SAlistair Francis static void xlnx_pmu_io_intc_init(Object *obj) 500c859b566SAlistair Francis { 501c859b566SAlistair Francis XlnxPMUIOIntc *s = XLNX_PMU_IO_INTC(obj); 502c859b566SAlistair Francis SysBusDevice *sbd = SYS_BUS_DEVICE(obj); 503c859b566SAlistair Francis RegisterInfoArray *reg_array; 504c859b566SAlistair Francis 505c859b566SAlistair Francis memory_region_init(&s->iomem, obj, TYPE_XLNX_PMU_IO_INTC, 506c859b566SAlistair Francis XLNXPMUIOINTC_R_MAX * 4); 507c859b566SAlistair Francis reg_array = 508c859b566SAlistair Francis register_init_block32(DEVICE(obj), xlnx_pmu_io_intc_regs_info, 509c859b566SAlistair Francis ARRAY_SIZE(xlnx_pmu_io_intc_regs_info), 510c859b566SAlistair Francis s->regs_info, s->regs, 511c859b566SAlistair Francis &xlnx_pmu_io_intc_ops, 512c859b566SAlistair Francis XLNX_PMU_IO_INTC_ERR_DEBUG, 513c859b566SAlistair Francis XLNXPMUIOINTC_R_MAX * 4); 514c859b566SAlistair Francis memory_region_add_subregion(&s->iomem, 515c859b566SAlistair Francis 0x0, 516c859b566SAlistair Francis ®_array->mem); 517c859b566SAlistair Francis sysbus_init_mmio(sbd, &s->iomem); 518c859b566SAlistair Francis 519c859b566SAlistair Francis sysbus_init_irq(sbd, &s->parent_irq); 520c859b566SAlistair Francis } 521c859b566SAlistair Francis 522c859b566SAlistair Francis static const VMStateDescription vmstate_xlnx_pmu_io_intc = { 523c859b566SAlistair Francis .name = TYPE_XLNX_PMU_IO_INTC, 524c859b566SAlistair Francis .version_id = 1, 525c859b566SAlistair Francis .minimum_version_id = 1, 526c859b566SAlistair Francis .fields = (VMStateField[]) { 527c859b566SAlistair Francis VMSTATE_UINT32_ARRAY(regs, XlnxPMUIOIntc, XLNXPMUIOINTC_R_MAX), 528c859b566SAlistair Francis VMSTATE_END_OF_LIST(), 529c859b566SAlistair Francis } 530c859b566SAlistair Francis }; 531c859b566SAlistair Francis 532c859b566SAlistair Francis static void xlnx_pmu_io_intc_class_init(ObjectClass *klass, void *data) 533c859b566SAlistair Francis { 534c859b566SAlistair Francis DeviceClass *dc = DEVICE_CLASS(klass); 535c859b566SAlistair Francis 536c859b566SAlistair Francis dc->reset = xlnx_pmu_io_intc_reset; 537c859b566SAlistair Francis dc->realize = xlnx_pmu_io_intc_realize; 538c859b566SAlistair Francis dc->vmsd = &vmstate_xlnx_pmu_io_intc; 539c859b566SAlistair Francis dc->props = xlnx_pmu_io_intc_properties; 540c859b566SAlistair Francis } 541c859b566SAlistair Francis 542c859b566SAlistair Francis static const TypeInfo xlnx_pmu_io_intc_info = { 543c859b566SAlistair Francis .name = TYPE_XLNX_PMU_IO_INTC, 544c859b566SAlistair Francis .parent = TYPE_SYS_BUS_DEVICE, 545c859b566SAlistair Francis .instance_size = sizeof(XlnxPMUIOIntc), 546c859b566SAlistair Francis .class_init = xlnx_pmu_io_intc_class_init, 547c859b566SAlistair Francis .instance_init = xlnx_pmu_io_intc_init, 548c859b566SAlistair Francis }; 549c859b566SAlistair Francis 550c859b566SAlistair Francis static void xlnx_pmu_io_intc_register_types(void) 551c859b566SAlistair Francis { 552c859b566SAlistair Francis type_register_static(&xlnx_pmu_io_intc_info); 553c859b566SAlistair Francis } 554c859b566SAlistair Francis 555c859b566SAlistair Francis type_init(xlnx_pmu_io_intc_register_types) 556