1 /* 2 * QEMU PowerPC pSeries Logical Partition (aka sPAPR) hardware System Emulator 3 * 4 * PAPR Virtualized Interrupt System, aka ICS/ICP aka xics 5 * 6 * Copyright (c) 2010,2011 David Gibson, IBM Corporation. 7 * 8 * Permission is hereby granted, free of charge, to any person obtaining a copy 9 * of this software and associated documentation files (the "Software"), to deal 10 * in the Software without restriction, including without limitation the rights 11 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 12 * copies of the Software, and to permit persons to whom the Software is 13 * furnished to do so, subject to the following conditions: 14 * 15 * The above copyright notice and this permission notice shall be included in 16 * all copies or substantial portions of the Software. 17 * 18 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 19 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 20 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 21 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 22 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 23 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN 24 * THE SOFTWARE. 25 * 26 */ 27 28 #include "qemu/osdep.h" 29 #include "cpu.h" 30 #include "hw/hw.h" 31 #include "trace.h" 32 #include "qemu/timer.h" 33 #include "hw/ppc/spapr.h" 34 #include "hw/ppc/xics.h" 35 #include "qapi/visitor.h" 36 #include "qapi/error.h" 37 38 /* 39 * Guest interfaces 40 */ 41 42 static target_ulong h_cppr(PowerPCCPU *cpu, sPAPRMachineState *spapr, 43 target_ulong opcode, target_ulong *args) 44 { 45 CPUState *cs = CPU(cpu); 46 target_ulong cppr = args[0]; 47 48 icp_set_cppr(spapr->icp, cs->cpu_index, cppr); 49 return H_SUCCESS; 50 } 51 52 static target_ulong h_ipi(PowerPCCPU *cpu, sPAPRMachineState *spapr, 53 target_ulong opcode, target_ulong *args) 54 { 55 target_ulong server = xics_get_cpu_index_by_dt_id(args[0]); 56 target_ulong mfrr = args[1]; 57 58 if (server >= spapr->icp->nr_servers) { 59 return H_PARAMETER; 60 } 61 62 icp_set_mfrr(spapr->icp, server, mfrr); 63 return H_SUCCESS; 64 } 65 66 static target_ulong h_xirr(PowerPCCPU *cpu, sPAPRMachineState *spapr, 67 target_ulong opcode, target_ulong *args) 68 { 69 CPUState *cs = CPU(cpu); 70 uint32_t xirr = icp_accept(spapr->icp->ss + cs->cpu_index); 71 72 args[0] = xirr; 73 return H_SUCCESS; 74 } 75 76 static target_ulong h_xirr_x(PowerPCCPU *cpu, sPAPRMachineState *spapr, 77 target_ulong opcode, target_ulong *args) 78 { 79 CPUState *cs = CPU(cpu); 80 ICPState *ss = &spapr->icp->ss[cs->cpu_index]; 81 uint32_t xirr = icp_accept(ss); 82 83 args[0] = xirr; 84 args[1] = cpu_get_host_ticks(); 85 return H_SUCCESS; 86 } 87 88 static target_ulong h_eoi(PowerPCCPU *cpu, sPAPRMachineState *spapr, 89 target_ulong opcode, target_ulong *args) 90 { 91 CPUState *cs = CPU(cpu); 92 target_ulong xirr = args[0]; 93 94 icp_eoi(spapr->icp, cs->cpu_index, xirr); 95 return H_SUCCESS; 96 } 97 98 static target_ulong h_ipoll(PowerPCCPU *cpu, sPAPRMachineState *spapr, 99 target_ulong opcode, target_ulong *args) 100 { 101 CPUState *cs = CPU(cpu); 102 ICPState *ss = &spapr->icp->ss[cs->cpu_index]; 103 104 args[0] = ss->xirr; 105 args[1] = ss->mfrr; 106 107 return H_SUCCESS; 108 } 109 110 static void rtas_set_xive(PowerPCCPU *cpu, sPAPRMachineState *spapr, 111 uint32_t token, 112 uint32_t nargs, target_ulong args, 113 uint32_t nret, target_ulong rets) 114 { 115 ICSState *ics = spapr->icp->ics; 116 uint32_t nr, server, priority; 117 118 if ((nargs != 3) || (nret != 1)) { 119 rtas_st(rets, 0, RTAS_OUT_PARAM_ERROR); 120 return; 121 } 122 123 nr = rtas_ld(args, 0); 124 server = xics_get_cpu_index_by_dt_id(rtas_ld(args, 1)); 125 priority = rtas_ld(args, 2); 126 127 if (!ics_valid_irq(ics, nr) || (server >= ics->icp->nr_servers) 128 || (priority > 0xff)) { 129 rtas_st(rets, 0, RTAS_OUT_PARAM_ERROR); 130 return; 131 } 132 133 ics_write_xive(ics, nr, server, priority, priority); 134 135 rtas_st(rets, 0, RTAS_OUT_SUCCESS); 136 } 137 138 static void rtas_get_xive(PowerPCCPU *cpu, sPAPRMachineState *spapr, 139 uint32_t token, 140 uint32_t nargs, target_ulong args, 141 uint32_t nret, target_ulong rets) 142 { 143 ICSState *ics = spapr->icp->ics; 144 uint32_t nr; 145 146 if ((nargs != 1) || (nret != 3)) { 147 rtas_st(rets, 0, RTAS_OUT_PARAM_ERROR); 148 return; 149 } 150 151 nr = rtas_ld(args, 0); 152 153 if (!ics_valid_irq(ics, nr)) { 154 rtas_st(rets, 0, RTAS_OUT_PARAM_ERROR); 155 return; 156 } 157 158 rtas_st(rets, 0, RTAS_OUT_SUCCESS); 159 rtas_st(rets, 1, ics->irqs[nr - ics->offset].server); 160 rtas_st(rets, 2, ics->irqs[nr - ics->offset].priority); 161 } 162 163 static void rtas_int_off(PowerPCCPU *cpu, sPAPRMachineState *spapr, 164 uint32_t token, 165 uint32_t nargs, target_ulong args, 166 uint32_t nret, target_ulong rets) 167 { 168 ICSState *ics = spapr->icp->ics; 169 uint32_t nr; 170 171 if ((nargs != 1) || (nret != 1)) { 172 rtas_st(rets, 0, RTAS_OUT_PARAM_ERROR); 173 return; 174 } 175 176 nr = rtas_ld(args, 0); 177 178 if (!ics_valid_irq(ics, nr)) { 179 rtas_st(rets, 0, RTAS_OUT_PARAM_ERROR); 180 return; 181 } 182 183 ics_write_xive(ics, nr, ics->irqs[nr - ics->offset].server, 0xff, 184 ics->irqs[nr - ics->offset].priority); 185 186 rtas_st(rets, 0, RTAS_OUT_SUCCESS); 187 } 188 189 static void rtas_int_on(PowerPCCPU *cpu, sPAPRMachineState *spapr, 190 uint32_t token, 191 uint32_t nargs, target_ulong args, 192 uint32_t nret, target_ulong rets) 193 { 194 ICSState *ics = spapr->icp->ics; 195 uint32_t nr; 196 197 if ((nargs != 1) || (nret != 1)) { 198 rtas_st(rets, 0, RTAS_OUT_PARAM_ERROR); 199 return; 200 } 201 202 nr = rtas_ld(args, 0); 203 204 if (!ics_valid_irq(ics, nr)) { 205 rtas_st(rets, 0, RTAS_OUT_PARAM_ERROR); 206 return; 207 } 208 209 ics_write_xive(ics, nr, ics->irqs[nr - ics->offset].server, 210 ics->irqs[nr - ics->offset].saved_priority, 211 ics->irqs[nr - ics->offset].saved_priority); 212 213 rtas_st(rets, 0, RTAS_OUT_SUCCESS); 214 } 215 216 static void xics_spapr_set_nr_irqs(XICSState *icp, uint32_t nr_irqs, 217 Error **errp) 218 { 219 icp->nr_irqs = icp->ics->nr_irqs = nr_irqs; 220 } 221 222 static void xics_spapr_set_nr_servers(XICSState *icp, uint32_t nr_servers, 223 Error **errp) 224 { 225 int i; 226 227 icp->nr_servers = nr_servers; 228 229 icp->ss = g_malloc0(icp->nr_servers * sizeof(ICPState)); 230 for (i = 0; i < icp->nr_servers; i++) { 231 char buffer[32]; 232 object_initialize(&icp->ss[i], sizeof(icp->ss[i]), TYPE_ICP); 233 snprintf(buffer, sizeof(buffer), "icp[%d]", i); 234 object_property_add_child(OBJECT(icp), buffer, OBJECT(&icp->ss[i]), 235 errp); 236 } 237 } 238 239 static void xics_spapr_realize(DeviceState *dev, Error **errp) 240 { 241 XICSState *icp = XICS_SPAPR(dev); 242 Error *error = NULL; 243 int i; 244 245 if (!icp->nr_servers) { 246 error_setg(errp, "Number of servers needs to be greater 0"); 247 return; 248 } 249 250 /* Registration of global state belongs into realize */ 251 spapr_rtas_register(RTAS_IBM_SET_XIVE, "ibm,set-xive", rtas_set_xive); 252 spapr_rtas_register(RTAS_IBM_GET_XIVE, "ibm,get-xive", rtas_get_xive); 253 spapr_rtas_register(RTAS_IBM_INT_OFF, "ibm,int-off", rtas_int_off); 254 spapr_rtas_register(RTAS_IBM_INT_ON, "ibm,int-on", rtas_int_on); 255 256 spapr_register_hypercall(H_CPPR, h_cppr); 257 spapr_register_hypercall(H_IPI, h_ipi); 258 spapr_register_hypercall(H_XIRR, h_xirr); 259 spapr_register_hypercall(H_XIRR_X, h_xirr_x); 260 spapr_register_hypercall(H_EOI, h_eoi); 261 spapr_register_hypercall(H_IPOLL, h_ipoll); 262 263 object_property_set_bool(OBJECT(icp->ics), true, "realized", &error); 264 if (error) { 265 error_propagate(errp, error); 266 return; 267 } 268 269 for (i = 0; i < icp->nr_servers; i++) { 270 object_property_set_bool(OBJECT(&icp->ss[i]), true, "realized", &error); 271 if (error) { 272 error_propagate(errp, error); 273 return; 274 } 275 } 276 } 277 278 static void xics_spapr_initfn(Object *obj) 279 { 280 XICSState *xics = XICS_SPAPR(obj); 281 282 xics->ics = ICS(object_new(TYPE_ICS)); 283 object_property_add_child(obj, "ics", OBJECT(xics->ics), NULL); 284 xics->ics->icp = xics; 285 } 286 287 static void xics_spapr_class_init(ObjectClass *oc, void *data) 288 { 289 DeviceClass *dc = DEVICE_CLASS(oc); 290 XICSStateClass *xsc = XICS_SPAPR_CLASS(oc); 291 292 dc->realize = xics_spapr_realize; 293 xsc->set_nr_irqs = xics_spapr_set_nr_irqs; 294 xsc->set_nr_servers = xics_spapr_set_nr_servers; 295 } 296 297 static const TypeInfo xics_spapr_info = { 298 .name = TYPE_XICS_SPAPR, 299 .parent = TYPE_XICS_COMMON, 300 .instance_size = sizeof(XICSState), 301 .class_size = sizeof(XICSStateClass), 302 .class_init = xics_spapr_class_init, 303 .instance_init = xics_spapr_initfn, 304 }; 305 306 #define ICS_IRQ_FREE(ics, srcno) \ 307 (!((ics)->irqs[(srcno)].flags & (XICS_FLAGS_IRQ_MASK))) 308 309 static int ics_find_free_block(ICSState *ics, int num, int alignnum) 310 { 311 int first, i; 312 313 for (first = 0; first < ics->nr_irqs; first += alignnum) { 314 if (num > (ics->nr_irqs - first)) { 315 return -1; 316 } 317 for (i = first; i < first + num; ++i) { 318 if (!ICS_IRQ_FREE(ics, i)) { 319 break; 320 } 321 } 322 if (i == (first + num)) { 323 return first; 324 } 325 } 326 327 return -1; 328 } 329 330 int xics_spapr_alloc(XICSState *icp, int src, int irq_hint, bool lsi, 331 Error **errp) 332 { 333 ICSState *ics = &icp->ics[src]; 334 int irq; 335 336 if (irq_hint) { 337 assert(src == xics_find_source(icp, irq_hint)); 338 if (!ICS_IRQ_FREE(ics, irq_hint - ics->offset)) { 339 error_setg(errp, "can't allocate IRQ %d: already in use", irq_hint); 340 return -1; 341 } 342 irq = irq_hint; 343 } else { 344 irq = ics_find_free_block(ics, 1, 1); 345 if (irq < 0) { 346 error_setg(errp, "can't allocate IRQ: no IRQ left"); 347 return -1; 348 } 349 irq += ics->offset; 350 } 351 352 ics_set_irq_type(ics, irq - ics->offset, lsi); 353 trace_xics_alloc(src, irq); 354 355 return irq; 356 } 357 358 /* 359 * Allocate block of consecutive IRQs, and return the number of the first IRQ in 360 * the block. If align==true, aligns the first IRQ number to num. 361 */ 362 int xics_spapr_alloc_block(XICSState *icp, int src, int num, bool lsi, 363 bool align, Error **errp) 364 { 365 int i, first = -1; 366 ICSState *ics = &icp->ics[src]; 367 368 assert(src == 0); 369 /* 370 * MSIMesage::data is used for storing VIRQ so 371 * it has to be aligned to num to support multiple 372 * MSI vectors. MSI-X is not affected by this. 373 * The hint is used for the first IRQ, the rest should 374 * be allocated continuously. 375 */ 376 if (align) { 377 assert((num == 1) || (num == 2) || (num == 4) || 378 (num == 8) || (num == 16) || (num == 32)); 379 first = ics_find_free_block(ics, num, num); 380 } else { 381 first = ics_find_free_block(ics, num, 1); 382 } 383 if (first < 0) { 384 error_setg(errp, "can't find a free %d-IRQ block", num); 385 return -1; 386 } 387 388 if (first >= 0) { 389 for (i = first; i < first + num; ++i) { 390 ics_set_irq_type(ics, i, lsi); 391 } 392 } 393 first += ics->offset; 394 395 trace_xics_alloc_block(src, first, num, lsi, align); 396 397 return first; 398 } 399 400 static void ics_free(ICSState *ics, int srcno, int num) 401 { 402 int i; 403 404 for (i = srcno; i < srcno + num; ++i) { 405 if (ICS_IRQ_FREE(ics, i)) { 406 trace_xics_ics_free_warn(ics - ics->icp->ics, i + ics->offset); 407 } 408 memset(&ics->irqs[i], 0, sizeof(ICSIRQState)); 409 } 410 } 411 412 void xics_spapr_free(XICSState *icp, int irq, int num) 413 { 414 int src = xics_find_source(icp, irq); 415 416 if (src >= 0) { 417 ICSState *ics = &icp->ics[src]; 418 419 /* FIXME: implement multiple sources */ 420 assert(src == 0); 421 422 trace_xics_ics_free(ics - icp->ics, irq, num); 423 ics_free(ics, irq - ics->offset, num); 424 } 425 } 426 427 static void xics_spapr_register_types(void) 428 { 429 type_register_static(&xics_spapr_info); 430 } 431 432 type_init(xics_spapr_register_types) 433