1 /* 2 * QEMU Sparc SLAVIO interrupt controller emulation 3 * 4 * Copyright (c) 2003-2005 Fabrice Bellard 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a copy 7 * of this software and associated documentation files (the "Software"), to deal 8 * in the Software without restriction, including without limitation the rights 9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 10 * copies of the Software, and to permit persons to whom the Software is 11 * furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice shall be included in 14 * all copies or substantial portions of the Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN 22 * THE SOFTWARE. 23 */ 24 #include "hw.h" 25 #include "sun4m.h" 26 #include "console.h" 27 28 //#define DEBUG_IRQ_COUNT 29 //#define DEBUG_IRQ 30 31 #ifdef DEBUG_IRQ 32 #define DPRINTF(fmt, args...) \ 33 do { printf("IRQ: " fmt , ##args); } while (0) 34 #else 35 #define DPRINTF(fmt, args...) 36 #endif 37 38 /* 39 * Registers of interrupt controller in sun4m. 40 * 41 * This is the interrupt controller part of chip STP2001 (Slave I/O), also 42 * produced as NCR89C105. See 43 * http://www.ibiblio.org/pub/historic-linux/early-ports/Sparc/NCR/NCR89C105.txt 44 * 45 * There is a system master controller and one for each cpu. 46 * 47 */ 48 49 #define MAX_CPUS 16 50 #define MAX_PILS 16 51 52 typedef struct SLAVIO_INTCTLState { 53 uint32_t intreg_pending[MAX_CPUS]; 54 uint32_t intregm_pending; 55 uint32_t intregm_disabled; 56 uint32_t target_cpu; 57 #ifdef DEBUG_IRQ_COUNT 58 uint64_t irq_count[32]; 59 #endif 60 qemu_irq *cpu_irqs[MAX_CPUS]; 61 const uint32_t *intbit_to_level; 62 uint32_t cputimer_bit; 63 uint32_t pil_out[MAX_CPUS]; 64 } SLAVIO_INTCTLState; 65 66 #define INTCTL_MAXADDR 0xf 67 #define INTCTL_SIZE (INTCTL_MAXADDR + 1) 68 #define INTCTLM_MAXADDR 0x13 69 #define INTCTLM_SIZE (INTCTLM_MAXADDR + 1) 70 #define INTCTLM_MASK 0x1f 71 #define MASTER_IRQ_MASK ~0x0fa2007f 72 #define MASTER_DISABLE 0x80000000 73 #define CPU_IRQ_MASK 0xfffe0000 74 #define CPU_IRQ_INT15_IN 0x0004000 75 #define CPU_IRQ_INT15_MASK 0x80000000 76 77 static void slavio_check_interrupts(void *opaque); 78 79 // per-cpu interrupt controller 80 static uint32_t slavio_intctl_mem_readl(void *opaque, target_phys_addr_t addr) 81 { 82 SLAVIO_INTCTLState *s = opaque; 83 uint32_t saddr, ret; 84 int cpu; 85 86 cpu = (addr & (MAX_CPUS - 1) * TARGET_PAGE_SIZE) >> 12; 87 saddr = (addr & INTCTL_MAXADDR) >> 2; 88 switch (saddr) { 89 case 0: 90 ret = s->intreg_pending[cpu]; 91 break; 92 default: 93 ret = 0; 94 break; 95 } 96 DPRINTF("read cpu %d reg 0x" TARGET_FMT_plx " = %x\n", cpu, addr, ret); 97 98 return ret; 99 } 100 101 static void slavio_intctl_mem_writel(void *opaque, target_phys_addr_t addr, uint32_t val) 102 { 103 SLAVIO_INTCTLState *s = opaque; 104 uint32_t saddr; 105 int cpu; 106 107 cpu = (addr & (MAX_CPUS - 1) * TARGET_PAGE_SIZE) >> 12; 108 saddr = (addr & INTCTL_MAXADDR) >> 2; 109 DPRINTF("write cpu %d reg 0x" TARGET_FMT_plx " = %x\n", cpu, addr, val); 110 switch (saddr) { 111 case 1: // clear pending softints 112 if (val & CPU_IRQ_INT15_IN) 113 val |= CPU_IRQ_INT15_MASK; 114 val &= CPU_IRQ_MASK; 115 s->intreg_pending[cpu] &= ~val; 116 slavio_check_interrupts(s); 117 DPRINTF("Cleared cpu %d irq mask %x, curmask %x\n", cpu, val, s->intreg_pending[cpu]); 118 break; 119 case 2: // set softint 120 val &= CPU_IRQ_MASK; 121 s->intreg_pending[cpu] |= val; 122 slavio_check_interrupts(s); 123 DPRINTF("Set cpu %d irq mask %x, curmask %x\n", cpu, val, s->intreg_pending[cpu]); 124 break; 125 default: 126 break; 127 } 128 } 129 130 static CPUReadMemoryFunc *slavio_intctl_mem_read[3] = { 131 slavio_intctl_mem_readl, 132 slavio_intctl_mem_readl, 133 slavio_intctl_mem_readl, 134 }; 135 136 static CPUWriteMemoryFunc *slavio_intctl_mem_write[3] = { 137 slavio_intctl_mem_writel, 138 slavio_intctl_mem_writel, 139 slavio_intctl_mem_writel, 140 }; 141 142 // master system interrupt controller 143 static uint32_t slavio_intctlm_mem_readl(void *opaque, target_phys_addr_t addr) 144 { 145 SLAVIO_INTCTLState *s = opaque; 146 uint32_t saddr, ret; 147 148 saddr = (addr & INTCTLM_MASK) >> 2; 149 switch (saddr) { 150 case 0: 151 ret = s->intregm_pending & ~MASTER_DISABLE; 152 break; 153 case 1: 154 ret = s->intregm_disabled & MASTER_IRQ_MASK; 155 break; 156 case 4: 157 ret = s->target_cpu; 158 break; 159 default: 160 ret = 0; 161 break; 162 } 163 DPRINTF("read system reg 0x" TARGET_FMT_plx " = %x\n", addr, ret); 164 165 return ret; 166 } 167 168 static void slavio_intctlm_mem_writel(void *opaque, target_phys_addr_t addr, uint32_t val) 169 { 170 SLAVIO_INTCTLState *s = opaque; 171 uint32_t saddr; 172 173 saddr = (addr & INTCTLM_MASK) >> 2; 174 DPRINTF("write system reg 0x" TARGET_FMT_plx " = %x\n", addr, val); 175 switch (saddr) { 176 case 2: // clear (enable) 177 // Force clear unused bits 178 val &= MASTER_IRQ_MASK; 179 s->intregm_disabled &= ~val; 180 DPRINTF("Enabled master irq mask %x, curmask %x\n", val, s->intregm_disabled); 181 slavio_check_interrupts(s); 182 break; 183 case 3: // set (disable, clear pending) 184 // Force clear unused bits 185 val &= MASTER_IRQ_MASK; 186 s->intregm_disabled |= val; 187 s->intregm_pending &= ~val; 188 slavio_check_interrupts(s); 189 DPRINTF("Disabled master irq mask %x, curmask %x\n", val, s->intregm_disabled); 190 break; 191 case 4: 192 s->target_cpu = val & (MAX_CPUS - 1); 193 slavio_check_interrupts(s); 194 DPRINTF("Set master irq cpu %d\n", s->target_cpu); 195 break; 196 default: 197 break; 198 } 199 } 200 201 static CPUReadMemoryFunc *slavio_intctlm_mem_read[3] = { 202 slavio_intctlm_mem_readl, 203 slavio_intctlm_mem_readl, 204 slavio_intctlm_mem_readl, 205 }; 206 207 static CPUWriteMemoryFunc *slavio_intctlm_mem_write[3] = { 208 slavio_intctlm_mem_writel, 209 slavio_intctlm_mem_writel, 210 slavio_intctlm_mem_writel, 211 }; 212 213 void slavio_pic_info(void *opaque) 214 { 215 SLAVIO_INTCTLState *s = opaque; 216 int i; 217 218 for (i = 0; i < MAX_CPUS; i++) { 219 term_printf("per-cpu %d: pending 0x%08x\n", i, s->intreg_pending[i]); 220 } 221 term_printf("master: pending 0x%08x, disabled 0x%08x\n", s->intregm_pending, s->intregm_disabled); 222 } 223 224 void slavio_irq_info(void *opaque) 225 { 226 #ifndef DEBUG_IRQ_COUNT 227 term_printf("irq statistic code not compiled.\n"); 228 #else 229 SLAVIO_INTCTLState *s = opaque; 230 int i; 231 int64_t count; 232 233 term_printf("IRQ statistics:\n"); 234 for (i = 0; i < 32; i++) { 235 count = s->irq_count[i]; 236 if (count > 0) 237 term_printf("%2d: %" PRId64 "\n", i, count); 238 } 239 #endif 240 } 241 242 static void slavio_check_interrupts(void *opaque) 243 { 244 SLAVIO_INTCTLState *s = opaque; 245 uint32_t pending = s->intregm_pending, pil_pending; 246 unsigned int i, j; 247 248 pending &= ~s->intregm_disabled; 249 250 DPRINTF("pending %x disabled %x\n", pending, s->intregm_disabled); 251 for (i = 0; i < MAX_CPUS; i++) { 252 pil_pending = 0; 253 if (pending && !(s->intregm_disabled & MASTER_DISABLE) && 254 (i == s->target_cpu)) { 255 for (j = 0; j < 32; j++) { 256 if (pending & (1 << j)) 257 pil_pending |= 1 << s->intbit_to_level[j]; 258 } 259 } 260 pil_pending |= (s->intreg_pending[i] & CPU_IRQ_MASK) >> 16; 261 262 for (j = 0; j < MAX_PILS; j++) { 263 if (pil_pending & (1 << j)) { 264 if (!(s->pil_out[i] & (1 << j))) 265 qemu_irq_raise(s->cpu_irqs[i][j]); 266 } else { 267 if (s->pil_out[i] & (1 << j)) 268 qemu_irq_lower(s->cpu_irqs[i][j]); 269 } 270 } 271 s->pil_out[i] = pil_pending; 272 } 273 } 274 275 /* 276 * "irq" here is the bit number in the system interrupt register to 277 * separate serial and keyboard interrupts sharing a level. 278 */ 279 static void slavio_set_irq(void *opaque, int irq, int level) 280 { 281 SLAVIO_INTCTLState *s = opaque; 282 uint32_t mask = 1 << irq; 283 uint32_t pil = s->intbit_to_level[irq]; 284 285 DPRINTF("Set cpu %d irq %d -> pil %d level %d\n", s->target_cpu, irq, pil, 286 level); 287 if (pil > 0) { 288 if (level) { 289 #ifdef DEBUG_IRQ_COUNT 290 s->irq_count[pil]++; 291 #endif 292 s->intregm_pending |= mask; 293 s->intreg_pending[s->target_cpu] |= 1 << pil; 294 } else { 295 s->intregm_pending &= ~mask; 296 s->intreg_pending[s->target_cpu] &= ~(1 << pil); 297 } 298 slavio_check_interrupts(s); 299 } 300 } 301 302 static void slavio_set_timer_irq_cpu(void *opaque, int cpu, int level) 303 { 304 SLAVIO_INTCTLState *s = opaque; 305 306 DPRINTF("Set cpu %d local timer level %d\n", cpu, level); 307 308 if (level) 309 s->intreg_pending[cpu] |= s->cputimer_bit; 310 else 311 s->intreg_pending[cpu] &= ~s->cputimer_bit; 312 313 slavio_check_interrupts(s); 314 } 315 316 static void slavio_intctl_save(QEMUFile *f, void *opaque) 317 { 318 SLAVIO_INTCTLState *s = opaque; 319 int i; 320 321 for (i = 0; i < MAX_CPUS; i++) { 322 qemu_put_be32s(f, &s->intreg_pending[i]); 323 } 324 qemu_put_be32s(f, &s->intregm_pending); 325 qemu_put_be32s(f, &s->intregm_disabled); 326 qemu_put_be32s(f, &s->target_cpu); 327 } 328 329 static int slavio_intctl_load(QEMUFile *f, void *opaque, int version_id) 330 { 331 SLAVIO_INTCTLState *s = opaque; 332 int i; 333 334 if (version_id != 1) 335 return -EINVAL; 336 337 for (i = 0; i < MAX_CPUS; i++) { 338 qemu_get_be32s(f, &s->intreg_pending[i]); 339 } 340 qemu_get_be32s(f, &s->intregm_pending); 341 qemu_get_be32s(f, &s->intregm_disabled); 342 qemu_get_be32s(f, &s->target_cpu); 343 slavio_check_interrupts(s); 344 return 0; 345 } 346 347 static void slavio_intctl_reset(void *opaque) 348 { 349 SLAVIO_INTCTLState *s = opaque; 350 int i; 351 352 for (i = 0; i < MAX_CPUS; i++) { 353 s->intreg_pending[i] = 0; 354 } 355 s->intregm_disabled = ~MASTER_IRQ_MASK; 356 s->intregm_pending = 0; 357 s->target_cpu = 0; 358 slavio_check_interrupts(s); 359 } 360 361 void *slavio_intctl_init(target_phys_addr_t addr, target_phys_addr_t addrg, 362 const uint32_t *intbit_to_level, 363 qemu_irq **irq, qemu_irq **cpu_irq, 364 qemu_irq **parent_irq, unsigned int cputimer) 365 { 366 int slavio_intctl_io_memory, slavio_intctlm_io_memory, i; 367 SLAVIO_INTCTLState *s; 368 369 s = qemu_mallocz(sizeof(SLAVIO_INTCTLState)); 370 if (!s) 371 return NULL; 372 373 s->intbit_to_level = intbit_to_level; 374 for (i = 0; i < MAX_CPUS; i++) { 375 slavio_intctl_io_memory = cpu_register_io_memory(0, slavio_intctl_mem_read, slavio_intctl_mem_write, s); 376 cpu_register_physical_memory(addr + i * TARGET_PAGE_SIZE, INTCTL_SIZE, 377 slavio_intctl_io_memory); 378 s->cpu_irqs[i] = parent_irq[i]; 379 } 380 381 slavio_intctlm_io_memory = cpu_register_io_memory(0, slavio_intctlm_mem_read, slavio_intctlm_mem_write, s); 382 cpu_register_physical_memory(addrg, INTCTLM_SIZE, slavio_intctlm_io_memory); 383 384 register_savevm("slavio_intctl", addr, 1, slavio_intctl_save, slavio_intctl_load, s); 385 qemu_register_reset(slavio_intctl_reset, s); 386 *irq = qemu_allocate_irqs(slavio_set_irq, s, 32); 387 388 *cpu_irq = qemu_allocate_irqs(slavio_set_timer_irq_cpu, s, MAX_CPUS); 389 s->cputimer_bit = 1 << s->intbit_to_level[cputimer]; 390 slavio_intctl_reset(s); 391 return s; 392 } 393 394