1 /*
2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
4 * for more details.
5 *
6 * Copyright (C) 2012 MIPS Technologies, Inc. All rights reserved.
7 * Authors: Sanjay Lal <sanjayl@kymasys.com>
8 *
9 * Copyright (C) 2016 Imagination Technologies
10 */
11
12 #include "qemu/osdep.h"
13 #include "qemu/log.h"
14 #include "qemu/module.h"
15 #include "qapi/error.h"
16 #include "hw/sysbus.h"
17 #include "system/memory.h"
18 #include "system/kvm.h"
19 #include "system/reset.h"
20 #include "kvm_mips.h"
21 #include "hw/intc/mips_gic.h"
22 #include "hw/irq.h"
23 #include "hw/qdev-properties.h"
24
mips_gic_set_vp_irq(MIPSGICState * gic,int vp,int pin)25 static void mips_gic_set_vp_irq(MIPSGICState *gic, int vp, int pin)
26 {
27 int ored_level = 0;
28 int i;
29
30 /* ORing pending registers sharing same pin */
31 for (i = 0; i < gic->num_irq; i++) {
32 if ((gic->irq_state[i].map_pin & GIC_MAP_MSK) == pin &&
33 gic->irq_state[i].map_vp == vp &&
34 gic->irq_state[i].enabled) {
35 ored_level |= gic->irq_state[i].pending;
36 }
37 if (ored_level) {
38 /* no need to iterate all interrupts */
39 break;
40 }
41 }
42 if (((gic->vps[vp].compare_map & GIC_MAP_MSK) == pin) &&
43 (gic->vps[vp].mask & GIC_VP_MASK_CMP_MSK)) {
44 /* ORing with local pending register (count/compare) */
45 ored_level |= (gic->vps[vp].pend & GIC_VP_MASK_CMP_MSK) >>
46 GIC_VP_MASK_CMP_SHF;
47 }
48 if (kvm_enabled()) {
49 kvm_mips_set_ipi_interrupt(env_archcpu(gic->vps[vp].env),
50 pin + GIC_CPU_PIN_OFFSET,
51 ored_level);
52 } else {
53 qemu_set_irq(gic->vps[vp].env->irq[pin + GIC_CPU_PIN_OFFSET],
54 ored_level);
55 }
56 }
57
gic_update_pin_for_irq(MIPSGICState * gic,int n_IRQ)58 static void gic_update_pin_for_irq(MIPSGICState *gic, int n_IRQ)
59 {
60 int vp = gic->irq_state[n_IRQ].map_vp;
61 int pin = gic->irq_state[n_IRQ].map_pin & GIC_MAP_MSK;
62
63 if (vp < 0 || vp >= gic->num_vps) {
64 return;
65 }
66 mips_gic_set_vp_irq(gic, vp, pin);
67 }
68
gic_set_irq(void * opaque,int n_IRQ,int level)69 static void gic_set_irq(void *opaque, int n_IRQ, int level)
70 {
71 MIPSGICState *gic = (MIPSGICState *) opaque;
72
73 gic->irq_state[n_IRQ].pending = (uint8_t) level;
74 if (!gic->irq_state[n_IRQ].enabled) {
75 /* GIC interrupt source disabled */
76 return;
77 }
78 gic_update_pin_for_irq(gic, n_IRQ);
79 }
80
81 #define OFFSET_CHECK(c) \
82 do { \
83 if (!(c)) { \
84 goto bad_offset; \
85 } \
86 } while (0)
87
88 /* GIC Read VP Local/Other Registers */
gic_read_vp(MIPSGICState * gic,uint32_t vp_index,hwaddr addr,unsigned size)89 static uint64_t gic_read_vp(MIPSGICState *gic, uint32_t vp_index, hwaddr addr,
90 unsigned size)
91 {
92 switch (addr) {
93 case GIC_VP_CTL_OFS:
94 return gic->vps[vp_index].ctl;
95 case GIC_VP_PEND_OFS:
96 mips_gictimer_get_sh_count(gic->gic_timer);
97 return gic->vps[vp_index].pend;
98 case GIC_VP_MASK_OFS:
99 return gic->vps[vp_index].mask;
100 case GIC_VP_COMPARE_MAP_OFS:
101 return gic->vps[vp_index].compare_map;
102 case GIC_VP_OTHER_ADDR_OFS:
103 return gic->vps[vp_index].other_addr;
104 case GIC_VP_IDENT_OFS:
105 return vp_index;
106 case GIC_VP_COMPARE_LO_OFS:
107 return mips_gictimer_get_vp_compare(gic->gic_timer, vp_index);
108 case GIC_VP_COMPARE_HI_OFS:
109 return 0;
110 default:
111 qemu_log_mask(LOG_UNIMP, "Read %d bytes at GIC offset LOCAL/OTHER 0x%"
112 PRIx64 "\n", size, addr);
113 break;
114 }
115 return 0;
116 }
117
gic_read(void * opaque,hwaddr addr,unsigned size)118 static uint64_t gic_read(void *opaque, hwaddr addr, unsigned size)
119 {
120 MIPSGICState *gic = (MIPSGICState *) opaque;
121 uint32_t vp_index = current_cpu->cpu_index;
122 uint64_t ret = 0;
123 int i, base, irq_src;
124 uint32_t other_index;
125
126 switch (addr) {
127 case GIC_SH_CONFIG_OFS:
128 ret = gic->sh_config | (mips_gictimer_get_countstop(gic->gic_timer) <<
129 GIC_SH_CONFIG_COUNTSTOP_SHF);
130 break;
131 case GIC_SH_COUNTERLO_OFS:
132 ret = mips_gictimer_get_sh_count(gic->gic_timer);
133 break;
134 case GIC_SH_COUNTERHI_OFS:
135 ret = 0;
136 break;
137 case GIC_SH_PEND_OFS ... GIC_SH_PEND_LAST_OFS:
138 /* each bit represents pending status for an interrupt pin */
139 base = (addr - GIC_SH_PEND_OFS) * 8;
140 OFFSET_CHECK((base + size * 8) <= gic->num_irq);
141 for (i = 0; i < size * 8; i++) {
142 ret |= (uint64_t) (gic->irq_state[base + i].pending) << i;
143 }
144 break;
145 case GIC_SH_MASK_OFS ... GIC_SH_MASK_LAST_OFS:
146 /* each bit represents status for an interrupt pin */
147 base = (addr - GIC_SH_MASK_OFS) * 8;
148 OFFSET_CHECK((base + size * 8) <= gic->num_irq);
149 for (i = 0; i < size * 8; i++) {
150 ret |= (uint64_t) (gic->irq_state[base + i].enabled) << i;
151 }
152 break;
153 case GIC_SH_MAP0_PIN_OFS ... GIC_SH_MAP255_PIN_OFS:
154 /* 32 bits per a pin */
155 irq_src = (addr - GIC_SH_MAP0_PIN_OFS) / 4;
156 OFFSET_CHECK(irq_src < gic->num_irq);
157 ret = gic->irq_state[irq_src].map_pin;
158 break;
159 case GIC_SH_MAP0_VP_OFS ... GIC_SH_MAP255_VP_LAST_OFS:
160 /* up to 32 bytes per a pin */
161 irq_src = (addr - GIC_SH_MAP0_VP_OFS) / 32;
162 OFFSET_CHECK(irq_src < gic->num_irq);
163 if ((gic->irq_state[irq_src].map_vp) >= 0) {
164 ret = (uint64_t) 1 << (gic->irq_state[irq_src].map_vp);
165 } else {
166 ret = 0;
167 }
168 break;
169 /* VP-Local Register */
170 case VP_LOCAL_SECTION_OFS ... (VP_LOCAL_SECTION_OFS + GIC_VL_BRK_GROUP):
171 ret = gic_read_vp(gic, vp_index, addr - VP_LOCAL_SECTION_OFS, size);
172 break;
173 /* VP-Other Register */
174 case VP_OTHER_SECTION_OFS ... (VP_OTHER_SECTION_OFS + GIC_VL_BRK_GROUP):
175 other_index = gic->vps[vp_index].other_addr;
176 ret = gic_read_vp(gic, other_index, addr - VP_OTHER_SECTION_OFS, size);
177 break;
178 /* User-Mode Visible section */
179 case USM_VISIBLE_SECTION_OFS + GIC_USER_MODE_COUNTERLO:
180 ret = mips_gictimer_get_sh_count(gic->gic_timer);
181 break;
182 case USM_VISIBLE_SECTION_OFS + GIC_USER_MODE_COUNTERHI:
183 ret = 0;
184 break;
185 default:
186 qemu_log_mask(LOG_UNIMP, "Read %d bytes at GIC offset 0x%" PRIx64 "\n",
187 size, addr);
188 break;
189 }
190 return ret;
191 bad_offset:
192 qemu_log_mask(LOG_GUEST_ERROR, "Wrong GIC offset at 0x%" PRIx64 "\n", addr);
193 return 0;
194 }
195
gic_timer_expire_cb(void * opaque,uint32_t vp_index)196 static void gic_timer_expire_cb(void *opaque, uint32_t vp_index)
197 {
198 MIPSGICState *gic = opaque;
199
200 gic->vps[vp_index].pend |= (1 << GIC_LOCAL_INT_COMPARE);
201 if (gic->vps[vp_index].pend &
202 (gic->vps[vp_index].mask & GIC_VP_MASK_CMP_MSK)) {
203 if (gic->vps[vp_index].compare_map & GIC_MAP_TO_PIN_MSK) {
204 /* it is safe to set the irq high regardless of other GIC IRQs */
205 uint32_t pin = (gic->vps[vp_index].compare_map & GIC_MAP_MSK);
206 qemu_irq_raise(gic->vps[vp_index].env->irq
207 [pin + GIC_CPU_PIN_OFFSET]);
208 }
209 }
210 }
211
gic_timer_store_vp_compare(MIPSGICState * gic,uint32_t vp_index,uint64_t compare)212 static void gic_timer_store_vp_compare(MIPSGICState *gic, uint32_t vp_index,
213 uint64_t compare)
214 {
215 gic->vps[vp_index].pend &= ~(1 << GIC_LOCAL_INT_COMPARE);
216 if (gic->vps[vp_index].compare_map & GIC_MAP_TO_PIN_MSK) {
217 uint32_t pin = (gic->vps[vp_index].compare_map & GIC_MAP_MSK);
218 mips_gic_set_vp_irq(gic, vp_index, pin);
219 }
220 mips_gictimer_store_vp_compare(gic->gic_timer, vp_index, compare);
221 }
222
223 /* GIC Write VP Local/Other Registers */
gic_write_vp(MIPSGICState * gic,uint32_t vp_index,hwaddr addr,uint64_t data,unsigned size)224 static void gic_write_vp(MIPSGICState *gic, uint32_t vp_index, hwaddr addr,
225 uint64_t data, unsigned size)
226 {
227 switch (addr) {
228 case GIC_VP_CTL_OFS:
229 /* EIC isn't supported */
230 break;
231 case GIC_VP_RMASK_OFS:
232 gic->vps[vp_index].mask &= ~(data & GIC_VP_SET_RESET_MSK) &
233 GIC_VP_SET_RESET_MSK;
234 break;
235 case GIC_VP_SMASK_OFS:
236 gic->vps[vp_index].mask |= data & GIC_VP_SET_RESET_MSK;
237 break;
238 case GIC_VP_COMPARE_MAP_OFS:
239 /* EIC isn't supported */
240 OFFSET_CHECK((data & GIC_MAP_MSK) <= GIC_CPU_INT_MAX);
241 gic->vps[vp_index].compare_map = data & GIC_MAP_TO_PIN_REG_MSK;
242 break;
243 case GIC_VP_OTHER_ADDR_OFS:
244 OFFSET_CHECK(data < gic->num_vps);
245 gic->vps[vp_index].other_addr = data;
246 break;
247 case GIC_VP_COMPARE_LO_OFS:
248 gic_timer_store_vp_compare(gic, vp_index, data);
249 break;
250 default:
251 qemu_log_mask(LOG_UNIMP, "Write %d bytes at GIC offset LOCAL/OTHER "
252 "0x%" PRIx64" 0x%08" PRIx64 "\n", size, addr, data);
253 break;
254 }
255 return;
256 bad_offset:
257 qemu_log_mask(LOG_GUEST_ERROR, "Wrong GIC offset at 0x%" PRIx64 "\n", addr);
258 }
259
gic_write(void * opaque,hwaddr addr,uint64_t data,unsigned size)260 static void gic_write(void *opaque, hwaddr addr, uint64_t data, unsigned size)
261 {
262 int intr;
263 MIPSGICState *gic = (MIPSGICState *) opaque;
264 uint32_t vp_index = current_cpu->cpu_index;
265 int i, base, irq_src;
266 uint32_t other_index;
267
268 switch (addr) {
269 case GIC_SH_CONFIG_OFS:
270 {
271 uint32_t pre_cntstop = mips_gictimer_get_countstop(gic->gic_timer);
272 uint32_t new_cntstop = (data & GIC_SH_CONFIG_COUNTSTOP_MSK) >>
273 GIC_SH_CONFIG_COUNTSTOP_SHF;
274 if (pre_cntstop != new_cntstop) {
275 if (new_cntstop == 1) {
276 mips_gictimer_stop_count(gic->gic_timer);
277 } else {
278 mips_gictimer_start_count(gic->gic_timer);
279 }
280 }
281 }
282 break;
283 case GIC_SH_COUNTERLO_OFS:
284 if (mips_gictimer_get_countstop(gic->gic_timer)) {
285 mips_gictimer_store_sh_count(gic->gic_timer, data);
286 }
287 break;
288 case GIC_SH_RMASK_OFS ... GIC_SH_RMASK_LAST_OFS:
289 /* up to 64 bits per a pin */
290 base = (addr - GIC_SH_RMASK_OFS) * 8;
291 OFFSET_CHECK((base + size * 8) <= gic->num_irq);
292 for (i = 0; i < size * 8; i++) {
293 gic->irq_state[base + i].enabled &= !((data >> i) & 1);
294 gic_update_pin_for_irq(gic, base + i);
295 }
296 break;
297 case GIC_SH_WEDGE_OFS:
298 /* Figure out which VP/HW Interrupt this maps to */
299 intr = data & ~GIC_SH_WEDGE_RW_MSK;
300 /* Mask/Enabled Checks */
301 OFFSET_CHECK(intr < gic->num_irq);
302 if (data & GIC_SH_WEDGE_RW_MSK) {
303 gic_set_irq(gic, intr, 1);
304 } else {
305 gic_set_irq(gic, intr, 0);
306 }
307 break;
308 case GIC_SH_SMASK_OFS ... GIC_SH_SMASK_LAST_OFS:
309 /* up to 64 bits per a pin */
310 base = (addr - GIC_SH_SMASK_OFS) * 8;
311 OFFSET_CHECK((base + size * 8) <= gic->num_irq);
312 for (i = 0; i < size * 8; i++) {
313 gic->irq_state[base + i].enabled |= (data >> i) & 1;
314 gic_update_pin_for_irq(gic, base + i);
315 }
316 break;
317 case GIC_SH_MAP0_PIN_OFS ... GIC_SH_MAP255_PIN_OFS:
318 /* 32 bits per a pin */
319 irq_src = (addr - GIC_SH_MAP0_PIN_OFS) / 4;
320 OFFSET_CHECK(irq_src < gic->num_irq);
321 /* EIC isn't supported */
322 OFFSET_CHECK((data & GIC_MAP_MSK) <= GIC_CPU_INT_MAX);
323 gic->irq_state[irq_src].map_pin = data & GIC_MAP_TO_PIN_REG_MSK;
324 break;
325 case GIC_SH_MAP0_VP_OFS ... GIC_SH_MAP255_VP_LAST_OFS:
326 /* up to 32 bytes per a pin */
327 irq_src = (addr - GIC_SH_MAP0_VP_OFS) / 32;
328 OFFSET_CHECK(irq_src < gic->num_irq);
329 data = data ? ctz64(data) : -1;
330 OFFSET_CHECK(data < gic->num_vps);
331 gic->irq_state[irq_src].map_vp = data;
332 break;
333 case VP_LOCAL_SECTION_OFS ... (VP_LOCAL_SECTION_OFS + GIC_VL_BRK_GROUP):
334 gic_write_vp(gic, vp_index, addr - VP_LOCAL_SECTION_OFS, data, size);
335 break;
336 case VP_OTHER_SECTION_OFS ... (VP_OTHER_SECTION_OFS + GIC_VL_BRK_GROUP):
337 other_index = gic->vps[vp_index].other_addr;
338 gic_write_vp(gic, other_index, addr - VP_OTHER_SECTION_OFS, data, size);
339 break;
340 case USM_VISIBLE_SECTION_OFS + GIC_USER_MODE_COUNTERLO:
341 case USM_VISIBLE_SECTION_OFS + GIC_USER_MODE_COUNTERHI:
342 /* do nothing. Read-only section */
343 break;
344 default:
345 qemu_log_mask(LOG_UNIMP, "Write %d bytes at GIC offset 0x%" PRIx64
346 " 0x%08" PRIx64 "\n", size, addr, data);
347 break;
348 }
349 return;
350 bad_offset:
351 qemu_log_mask(LOG_GUEST_ERROR, "Wrong GIC offset at 0x%" PRIx64 "\n", addr);
352 }
353
gic_reset(void * opaque)354 static void gic_reset(void *opaque)
355 {
356 int i;
357 MIPSGICState *gic = (MIPSGICState *) opaque;
358 int numintrs = (gic->num_irq / 8) - 1;
359
360 gic->sh_config = /* COUNTSTOP = 0 it is accessible via MIPSGICTimer*/
361 /* CounterHi not implemented */
362 (0 << GIC_SH_CONFIG_COUNTBITS_SHF) |
363 (numintrs << GIC_SH_CONFIG_NUMINTRS_SHF) |
364 (gic->num_vps << GIC_SH_CONFIG_PVPS_SHF);
365 for (i = 0; i < gic->num_vps; i++) {
366 gic->vps[i].ctl = 0x0;
367 gic->vps[i].pend = 0x0;
368 /* PERFCNT, TIMER and WD not implemented */
369 gic->vps[i].mask = 0x32;
370 gic->vps[i].compare_map = GIC_MAP_TO_PIN_MSK;
371 mips_gictimer_store_vp_compare(gic->gic_timer, i, 0xffffffff);
372 gic->vps[i].other_addr = 0x0;
373 }
374 for (i = 0; i < gic->num_irq; i++) {
375 gic->irq_state[i].enabled = 0;
376 gic->irq_state[i].pending = 0;
377 gic->irq_state[i].map_pin = GIC_MAP_TO_PIN_MSK;
378 gic->irq_state[i].map_vp = -1;
379 }
380 mips_gictimer_store_sh_count(gic->gic_timer, 0);
381 /* COUNTSTOP = 0 */
382 mips_gictimer_start_count(gic->gic_timer);
383 }
384
385 static const MemoryRegionOps gic_ops = {
386 .read = gic_read,
387 .write = gic_write,
388 .endianness = DEVICE_NATIVE_ENDIAN,
389 .impl = {
390 .max_access_size = 8,
391 },
392 };
393
mips_gic_init(Object * obj)394 static void mips_gic_init(Object *obj)
395 {
396 SysBusDevice *sbd = SYS_BUS_DEVICE(obj);
397 MIPSGICState *s = MIPS_GIC(obj);
398
399 memory_region_init_io(&s->mr, OBJECT(s), &gic_ops, s,
400 "mips-gic", GIC_ADDRSPACE_SZ);
401 sysbus_init_mmio(sbd, &s->mr);
402 qemu_register_reset(gic_reset, s);
403 }
404
mips_gic_realize(DeviceState * dev,Error ** errp)405 static void mips_gic_realize(DeviceState *dev, Error **errp)
406 {
407 MIPSGICState *s = MIPS_GIC(dev);
408 CPUState *cs = first_cpu;
409 int i;
410
411 if (s->num_vps > GIC_MAX_VPS) {
412 error_setg(errp, "Exceeded maximum CPUs %d", s->num_vps);
413 return;
414 }
415 if ((s->num_irq > GIC_MAX_INTRS) || (s->num_irq % 8) || (s->num_irq <= 0)) {
416 error_setg(errp, "GIC supports up to %d external interrupts in "
417 "multiples of 8 : %d", GIC_MAX_INTRS, s->num_irq);
418 return;
419 }
420 s->vps = g_new(MIPSGICVPState, s->num_vps);
421 s->irq_state = g_new(MIPSGICIRQState, s->num_irq);
422 /* Register the env for all VPs with the GIC */
423 for (i = 0; i < s->num_vps; i++) {
424 if (cs != NULL) {
425 s->vps[i].env = cpu_env(cs);
426 cs = CPU_NEXT(cs);
427 } else {
428 error_setg(errp,
429 "Unable to initialize GIC, CPUState for CPU#%d not valid.", i);
430 return;
431 }
432 }
433 s->gic_timer = mips_gictimer_init(s, s->num_vps, gic_timer_expire_cb);
434 qdev_init_gpio_in(dev, gic_set_irq, s->num_irq);
435 for (i = 0; i < s->num_irq; i++) {
436 s->irq_state[i].irq = qdev_get_gpio_in(dev, i);
437 }
438 }
439
440 static const Property mips_gic_properties[] = {
441 DEFINE_PROP_UINT32("num-vp", MIPSGICState, num_vps, 1),
442 DEFINE_PROP_UINT32("num-irq", MIPSGICState, num_irq, 256),
443 };
444
mips_gic_class_init(ObjectClass * klass,const void * data)445 static void mips_gic_class_init(ObjectClass *klass, const void *data)
446 {
447 DeviceClass *dc = DEVICE_CLASS(klass);
448
449 device_class_set_props(dc, mips_gic_properties);
450 dc->realize = mips_gic_realize;
451 }
452
453 static const TypeInfo mips_gic_info = {
454 .name = TYPE_MIPS_GIC,
455 .parent = TYPE_SYS_BUS_DEVICE,
456 .instance_size = sizeof(MIPSGICState),
457 .instance_init = mips_gic_init,
458 .class_init = mips_gic_class_init,
459 };
460
mips_gic_register_types(void)461 static void mips_gic_register_types(void)
462 {
463 type_register_static(&mips_gic_info);
464 }
465
466 type_init(mips_gic_register_types)
467