1 /* SPDX-License-Identifier: GPL-2.0-or-later */ 2 /* 3 * Loongson ipi interrupt support 4 * 5 * Copyright (C) 2021 Loongson Technology Corporation Limited 6 */ 7 8 #include "qemu/osdep.h" 9 #include "hw/intc/loongson_ipi.h" 10 #include "hw/qdev-properties.h" 11 #include "qapi/error.h" 12 #include "target/mips/cpu.h" 13 14 static AddressSpace *get_iocsr_as(CPUState *cpu) 15 { 16 if (ase_lcsr_available(&MIPS_CPU(cpu)->env)) { 17 return &MIPS_CPU(cpu)->env.iocsr.as; 18 } 19 20 return NULL; 21 } 22 23 static int loongson_cpu_by_arch_id(LoongsonIPICommonState *lics, 24 int64_t arch_id, int *index, CPUState **pcs) 25 { 26 CPUState *cs; 27 28 cs = cpu_by_arch_id(arch_id); 29 if (cs == NULL) { 30 return MEMTX_ERROR; 31 } 32 33 if (index) { 34 *index = cs->cpu_index; 35 } 36 37 if (pcs) { 38 *pcs = cs; 39 } 40 41 return MEMTX_OK; 42 } 43 44 static const MemoryRegionOps loongson_ipi_core_ops = { 45 .read_with_attrs = loongson_ipi_core_readl, 46 .write_with_attrs = loongson_ipi_core_writel, 47 .impl.min_access_size = 4, 48 .impl.max_access_size = 4, 49 .valid.min_access_size = 4, 50 .valid.max_access_size = 8, 51 .endianness = DEVICE_LITTLE_ENDIAN, 52 }; 53 54 static void loongson_ipi_realize(DeviceState *dev, Error **errp) 55 { 56 LoongsonIPICommonState *sc = LOONGSON_IPI_COMMON(dev); 57 LoongsonIPIState *s = LOONGSON_IPI(dev); 58 LoongsonIPIClass *lic = LOONGSON_IPI_GET_CLASS(dev); 59 SysBusDevice *sbd = SYS_BUS_DEVICE(dev); 60 Error *local_err = NULL; 61 int i; 62 63 lic->parent_realize(dev, &local_err); 64 if (local_err) { 65 error_propagate(errp, local_err); 66 return; 67 } 68 69 if (sc->num_cpu == 0) { 70 error_setg(errp, "num-cpu must be at least 1"); 71 return; 72 } 73 74 sc->cpu = g_new0(IPICore, sc->num_cpu); 75 for (i = 0; i < sc->num_cpu; i++) { 76 sc->cpu[i].ipi = sc; 77 qdev_init_gpio_out(dev, &sc->cpu[i].irq, 1); 78 } 79 80 s->ipi_mmio_mem = g_new0(MemoryRegion, sc->num_cpu); 81 for (i = 0; i < sc->num_cpu; i++) { 82 g_autofree char *name = g_strdup_printf("loongson_ipi_cpu%d_mmio", i); 83 84 memory_region_init_io(&s->ipi_mmio_mem[i], OBJECT(dev), 85 &loongson_ipi_core_ops, &sc->cpu[i], name, 0x48); 86 sysbus_init_mmio(sbd, &s->ipi_mmio_mem[i]); 87 } 88 } 89 90 static void loongson_ipi_unrealize(DeviceState *dev) 91 { 92 LoongsonIPIState *s = LOONGSON_IPI(dev); 93 LoongsonIPIClass *k = LOONGSON_IPI_GET_CLASS(dev); 94 95 g_free(s->ipi_mmio_mem); 96 97 k->parent_unrealize(dev); 98 } 99 100 static const Property loongson_ipi_properties[] = { 101 DEFINE_PROP_UINT32("num-cpu", LoongsonIPICommonState, num_cpu, 1), 102 }; 103 104 static void loongson_ipi_class_init(ObjectClass *klass, void *data) 105 { 106 DeviceClass *dc = DEVICE_CLASS(klass); 107 LoongsonIPIClass *lic = LOONGSON_IPI_CLASS(klass); 108 LoongsonIPICommonClass *licc = LOONGSON_IPI_COMMON_CLASS(klass); 109 110 device_class_set_parent_realize(dc, loongson_ipi_realize, 111 &lic->parent_realize); 112 device_class_set_parent_unrealize(dc, loongson_ipi_unrealize, 113 &lic->parent_unrealize); 114 device_class_set_props(dc, loongson_ipi_properties); 115 licc->get_iocsr_as = get_iocsr_as; 116 licc->cpu_by_arch_id = loongson_cpu_by_arch_id; 117 } 118 119 static const TypeInfo loongson_ipi_types[] = { 120 { 121 .name = TYPE_LOONGSON_IPI, 122 .parent = TYPE_LOONGSON_IPI_COMMON, 123 .instance_size = sizeof(LoongsonIPIState), 124 .class_size = sizeof(LoongsonIPIClass), 125 .class_init = loongson_ipi_class_init, 126 } 127 }; 128 129 DEFINE_TYPES(loongson_ipi_types) 130