1 /* SPDX-License-Identifier: GPL-2.0-or-later */ 2 /* 3 * Loongson 3A5000 ext interrupt controller emulation 4 * 5 * Copyright (C) 2021 Loongson Technology Corporation Limited 6 */ 7 8 #include "qemu/osdep.h" 9 #include "qemu/module.h" 10 #include "qemu/log.h" 11 #include "qapi/error.h" 12 #include "hw/irq.h" 13 #include "hw/loongarch/virt.h" 14 #include "exec/address-spaces.h" 15 #include "hw/intc/loongarch_extioi.h" 16 #include "trace.h" 17 18 19 static void extioi_update_irq(LoongArchExtIOICommonState *s, int irq, int level) 20 { 21 int ipnum, cpu, found, irq_index, irq_mask; 22 23 ipnum = s->sw_ipmap[irq / 32]; 24 cpu = s->sw_coremap[irq]; 25 irq_index = irq / 32; 26 irq_mask = 1 << (irq & 0x1f); 27 28 if (level) { 29 /* if not enable return false */ 30 if (((s->enable[irq_index]) & irq_mask) == 0) { 31 return; 32 } 33 s->cpu[cpu].coreisr[irq_index] |= irq_mask; 34 found = find_first_bit(s->cpu[cpu].sw_isr[ipnum], EXTIOI_IRQS); 35 set_bit(irq, s->cpu[cpu].sw_isr[ipnum]); 36 if (found < EXTIOI_IRQS) { 37 /* other irq is handling, need not update parent irq level */ 38 return; 39 } 40 } else { 41 s->cpu[cpu].coreisr[irq_index] &= ~irq_mask; 42 clear_bit(irq, s->cpu[cpu].sw_isr[ipnum]); 43 found = find_first_bit(s->cpu[cpu].sw_isr[ipnum], EXTIOI_IRQS); 44 if (found < EXTIOI_IRQS) { 45 /* other irq is handling, need not update parent irq level */ 46 return; 47 } 48 } 49 qemu_set_irq(s->cpu[cpu].parent_irq[ipnum], level); 50 } 51 52 static void extioi_setirq(void *opaque, int irq, int level) 53 { 54 LoongArchExtIOICommonState *s = LOONGARCH_EXTIOI_COMMON(opaque); 55 trace_loongarch_extioi_setirq(irq, level); 56 if (level) { 57 set_bit32(irq, s->isr); 58 } else { 59 clear_bit32(irq, s->isr); 60 } 61 extioi_update_irq(s, irq, level); 62 } 63 64 static MemTxResult extioi_readw(void *opaque, hwaddr addr, uint64_t *data, 65 unsigned size, MemTxAttrs attrs) 66 { 67 LoongArchExtIOICommonState *s = LOONGARCH_EXTIOI_COMMON(opaque); 68 unsigned long offset = addr & 0xffff; 69 uint32_t index, cpu; 70 71 switch (offset) { 72 case EXTIOI_NODETYPE_START ... EXTIOI_NODETYPE_END - 1: 73 index = (offset - EXTIOI_NODETYPE_START) >> 2; 74 *data = s->nodetype[index]; 75 break; 76 case EXTIOI_IPMAP_START ... EXTIOI_IPMAP_END - 1: 77 index = (offset - EXTIOI_IPMAP_START) >> 2; 78 *data = s->ipmap[index]; 79 break; 80 case EXTIOI_ENABLE_START ... EXTIOI_ENABLE_END - 1: 81 index = (offset - EXTIOI_ENABLE_START) >> 2; 82 *data = s->enable[index]; 83 break; 84 case EXTIOI_BOUNCE_START ... EXTIOI_BOUNCE_END - 1: 85 index = (offset - EXTIOI_BOUNCE_START) >> 2; 86 *data = s->bounce[index]; 87 break; 88 case EXTIOI_COREISR_START ... EXTIOI_COREISR_END - 1: 89 index = (offset - EXTIOI_COREISR_START) >> 2; 90 /* using attrs to get current cpu index */ 91 cpu = attrs.requester_id; 92 *data = s->cpu[cpu].coreisr[index]; 93 break; 94 case EXTIOI_COREMAP_START ... EXTIOI_COREMAP_END - 1: 95 index = (offset - EXTIOI_COREMAP_START) >> 2; 96 *data = s->coremap[index]; 97 break; 98 default: 99 break; 100 } 101 102 trace_loongarch_extioi_readw(addr, *data); 103 return MEMTX_OK; 104 } 105 106 static inline void extioi_enable_irq(LoongArchExtIOICommonState *s, int index,\ 107 uint32_t mask, int level) 108 { 109 uint32_t val; 110 int irq; 111 112 val = mask & s->isr[index]; 113 irq = ctz32(val); 114 while (irq != 32) { 115 /* 116 * enable bit change from 0 to 1, 117 * need to update irq by pending bits 118 */ 119 extioi_update_irq(s, irq + index * 32, level); 120 val &= ~(1 << irq); 121 irq = ctz32(val); 122 } 123 } 124 125 static inline void extioi_update_sw_coremap(LoongArchExtIOICommonState *s, 126 int irq, uint64_t val, bool notify) 127 { 128 int i, cpu; 129 130 /* 131 * loongarch only support little endian, 132 * so we paresd the value with little endian. 133 */ 134 val = cpu_to_le64(val); 135 136 for (i = 0; i < 4; i++) { 137 cpu = val & 0xff; 138 val = val >> 8; 139 140 if (!(s->status & BIT(EXTIOI_ENABLE_CPU_ENCODE))) { 141 cpu = ctz32(cpu); 142 cpu = (cpu >= 4) ? 0 : cpu; 143 } 144 145 if (s->sw_coremap[irq + i] == cpu) { 146 continue; 147 } 148 149 if (notify && test_bit32(irq + i, s->isr)) { 150 /* 151 * lower irq at old cpu and raise irq at new cpu 152 */ 153 extioi_update_irq(s, irq + i, 0); 154 s->sw_coremap[irq + i] = cpu; 155 extioi_update_irq(s, irq + i, 1); 156 } else { 157 s->sw_coremap[irq + i] = cpu; 158 } 159 } 160 } 161 162 static inline void extioi_update_sw_ipmap(LoongArchExtIOICommonState *s, 163 int index, uint64_t val) 164 { 165 int i; 166 uint8_t ipnum; 167 168 /* 169 * loongarch only support little endian, 170 * so we paresd the value with little endian. 171 */ 172 val = cpu_to_le64(val); 173 for (i = 0; i < 4; i++) { 174 ipnum = val & 0xff; 175 ipnum = ctz32(ipnum); 176 ipnum = (ipnum >= 4) ? 0 : ipnum; 177 s->sw_ipmap[index * 4 + i] = ipnum; 178 val = val >> 8; 179 } 180 } 181 182 static MemTxResult extioi_writew(void *opaque, hwaddr addr, 183 uint64_t val, unsigned size, 184 MemTxAttrs attrs) 185 { 186 LoongArchExtIOICommonState *s = LOONGARCH_EXTIOI_COMMON(opaque); 187 int cpu, index, old_data, irq; 188 uint32_t offset; 189 190 trace_loongarch_extioi_writew(addr, val); 191 offset = addr & 0xffff; 192 193 switch (offset) { 194 case EXTIOI_NODETYPE_START ... EXTIOI_NODETYPE_END - 1: 195 index = (offset - EXTIOI_NODETYPE_START) >> 2; 196 s->nodetype[index] = val; 197 break; 198 case EXTIOI_IPMAP_START ... EXTIOI_IPMAP_END - 1: 199 /* 200 * ipmap cannot be set at runtime, can be set only at the beginning 201 * of intr driver, need not update upper irq level 202 */ 203 index = (offset - EXTIOI_IPMAP_START) >> 2; 204 s->ipmap[index] = val; 205 extioi_update_sw_ipmap(s, index, val); 206 break; 207 case EXTIOI_ENABLE_START ... EXTIOI_ENABLE_END - 1: 208 index = (offset - EXTIOI_ENABLE_START) >> 2; 209 old_data = s->enable[index]; 210 s->enable[index] = val; 211 212 /* unmask irq */ 213 val = s->enable[index] & ~old_data; 214 extioi_enable_irq(s, index, val, 1); 215 216 /* mask irq */ 217 val = ~s->enable[index] & old_data; 218 extioi_enable_irq(s, index, val, 0); 219 break; 220 case EXTIOI_BOUNCE_START ... EXTIOI_BOUNCE_END - 1: 221 /* do not emulate hw bounced irq routing */ 222 index = (offset - EXTIOI_BOUNCE_START) >> 2; 223 s->bounce[index] = val; 224 break; 225 case EXTIOI_COREISR_START ... EXTIOI_COREISR_END - 1: 226 index = (offset - EXTIOI_COREISR_START) >> 2; 227 /* using attrs to get current cpu index */ 228 cpu = attrs.requester_id; 229 old_data = s->cpu[cpu].coreisr[index]; 230 s->cpu[cpu].coreisr[index] = old_data & ~val; 231 /* write 1 to clear interrupt */ 232 old_data &= val; 233 irq = ctz32(old_data); 234 while (irq != 32) { 235 extioi_update_irq(s, irq + index * 32, 0); 236 old_data &= ~(1 << irq); 237 irq = ctz32(old_data); 238 } 239 break; 240 case EXTIOI_COREMAP_START ... EXTIOI_COREMAP_END - 1: 241 irq = offset - EXTIOI_COREMAP_START; 242 index = irq / 4; 243 s->coremap[index] = val; 244 245 extioi_update_sw_coremap(s, irq, val, true); 246 break; 247 default: 248 break; 249 } 250 return MEMTX_OK; 251 } 252 253 static const MemoryRegionOps extioi_ops = { 254 .read_with_attrs = extioi_readw, 255 .write_with_attrs = extioi_writew, 256 .impl.min_access_size = 4, 257 .impl.max_access_size = 4, 258 .valid.min_access_size = 4, 259 .valid.max_access_size = 8, 260 .endianness = DEVICE_LITTLE_ENDIAN, 261 }; 262 263 static MemTxResult extioi_virt_readw(void *opaque, hwaddr addr, uint64_t *data, 264 unsigned size, MemTxAttrs attrs) 265 { 266 LoongArchExtIOICommonState *s = LOONGARCH_EXTIOI_COMMON(opaque); 267 268 switch (addr) { 269 case EXTIOI_VIRT_FEATURES: 270 *data = s->features; 271 break; 272 case EXTIOI_VIRT_CONFIG: 273 *data = s->status; 274 break; 275 default: 276 g_assert_not_reached(); 277 } 278 279 return MEMTX_OK; 280 } 281 282 static MemTxResult extioi_virt_writew(void *opaque, hwaddr addr, 283 uint64_t val, unsigned size, 284 MemTxAttrs attrs) 285 { 286 LoongArchExtIOICommonState *s = LOONGARCH_EXTIOI_COMMON(opaque); 287 288 switch (addr) { 289 case EXTIOI_VIRT_FEATURES: 290 return MEMTX_ACCESS_ERROR; 291 292 case EXTIOI_VIRT_CONFIG: 293 /* 294 * extioi features can only be set at disabled status 295 */ 296 if ((s->status & BIT(EXTIOI_ENABLE)) && val) { 297 return MEMTX_ACCESS_ERROR; 298 } 299 300 s->status = val & s->features; 301 break; 302 default: 303 g_assert_not_reached(); 304 } 305 return MEMTX_OK; 306 } 307 308 static const MemoryRegionOps extioi_virt_ops = { 309 .read_with_attrs = extioi_virt_readw, 310 .write_with_attrs = extioi_virt_writew, 311 .impl.min_access_size = 4, 312 .impl.max_access_size = 4, 313 .valid.min_access_size = 4, 314 .valid.max_access_size = 8, 315 .endianness = DEVICE_LITTLE_ENDIAN, 316 }; 317 318 static void loongarch_extioi_realize(DeviceState *dev, Error **errp) 319 { 320 LoongArchExtIOICommonState *s = LOONGARCH_EXTIOI_COMMON(dev); 321 LoongArchExtIOIClass *lec = LOONGARCH_EXTIOI_GET_CLASS(dev); 322 SysBusDevice *sbd = SYS_BUS_DEVICE(dev); 323 Error *local_err = NULL; 324 int i, pin; 325 326 lec->parent_realize(dev, &local_err); 327 if (local_err) { 328 error_propagate(errp, local_err); 329 return; 330 } 331 332 for (i = 0; i < EXTIOI_IRQS; i++) { 333 sysbus_init_irq(sbd, &s->irq[i]); 334 } 335 336 qdev_init_gpio_in(dev, extioi_setirq, EXTIOI_IRQS); 337 memory_region_init_io(&s->extioi_system_mem, OBJECT(s), &extioi_ops, 338 s, "extioi_system_mem", 0x900); 339 sysbus_init_mmio(sbd, &s->extioi_system_mem); 340 341 if (s->features & BIT(EXTIOI_HAS_VIRT_EXTENSION)) { 342 memory_region_init_io(&s->virt_extend, OBJECT(s), &extioi_virt_ops, 343 s, "extioi_virt", EXTIOI_VIRT_SIZE); 344 sysbus_init_mmio(sbd, &s->virt_extend); 345 s->features |= EXTIOI_VIRT_HAS_FEATURES; 346 } else { 347 s->status |= BIT(EXTIOI_ENABLE); 348 } 349 350 s->cpu = g_new0(ExtIOICore, s->num_cpu); 351 if (s->cpu == NULL) { 352 error_setg(errp, "Memory allocation for ExtIOICore faile"); 353 return; 354 } 355 356 for (i = 0; i < s->num_cpu; i++) { 357 for (pin = 0; pin < LS3A_INTC_IP; pin++) { 358 qdev_init_gpio_out(dev, &s->cpu[i].parent_irq[pin], 1); 359 } 360 } 361 } 362 363 static void loongarch_extioi_unrealize(DeviceState *dev) 364 { 365 LoongArchExtIOICommonState *s = LOONGARCH_EXTIOI_COMMON(dev); 366 367 g_free(s->cpu); 368 } 369 370 static void loongarch_extioi_reset(DeviceState *d) 371 { 372 LoongArchExtIOICommonState *s = LOONGARCH_EXTIOI_COMMON(d); 373 374 s->status = 0; 375 } 376 377 static int vmstate_extioi_post_load(void *opaque, int version_id) 378 { 379 LoongArchExtIOICommonState *s = LOONGARCH_EXTIOI_COMMON(opaque); 380 int i, start_irq; 381 382 for (i = 0; i < (EXTIOI_IRQS / 4); i++) { 383 start_irq = i * 4; 384 extioi_update_sw_coremap(s, start_irq, s->coremap[i], false); 385 } 386 387 for (i = 0; i < (EXTIOI_IRQS_IPMAP_SIZE / 4); i++) { 388 extioi_update_sw_ipmap(s, i, s->ipmap[i]); 389 } 390 391 return 0; 392 } 393 394 static void loongarch_extioi_class_init(ObjectClass *klass, void *data) 395 { 396 DeviceClass *dc = DEVICE_CLASS(klass); 397 LoongArchExtIOIClass *lec = LOONGARCH_EXTIOI_CLASS(klass); 398 LoongArchExtIOICommonClass *lecc = LOONGARCH_EXTIOI_COMMON_CLASS(klass); 399 400 device_class_set_parent_realize(dc, loongarch_extioi_realize, 401 &lec->parent_realize); 402 device_class_set_parent_unrealize(dc, loongarch_extioi_unrealize, 403 &lec->parent_unrealize); 404 device_class_set_legacy_reset(dc, loongarch_extioi_reset); 405 lecc->post_load = vmstate_extioi_post_load; 406 } 407 408 static const TypeInfo loongarch_extioi_types[] = { 409 { 410 .name = TYPE_LOONGARCH_EXTIOI, 411 .parent = TYPE_LOONGARCH_EXTIOI_COMMON, 412 .instance_size = sizeof(LoongArchExtIOIState), 413 .class_size = sizeof(LoongArchExtIOIClass), 414 .class_init = loongarch_extioi_class_init, 415 } 416 }; 417 418 DEFINE_TYPES(loongarch_extioi_types) 419