xref: /qemu/hw/intc/ioapic_internal.h (revision 94c5a606379ddd04beecdb11fb34b51b4b28c7f2)
1244ac3afSJan Kiszka /*
2244ac3afSJan Kiszka  *  IOAPIC emulation logic - internal interfaces
3244ac3afSJan Kiszka  *
4244ac3afSJan Kiszka  *  Copyright (c) 2004-2005 Fabrice Bellard
5244ac3afSJan Kiszka  *  Copyright (c) 2009      Xiantao Zhang, Intel
6244ac3afSJan Kiszka  *  Copyright (c) 2011 Jan Kiszka, Siemens AG
7244ac3afSJan Kiszka  *
8244ac3afSJan Kiszka  * This library is free software; you can redistribute it and/or
9244ac3afSJan Kiszka  * modify it under the terms of the GNU Lesser General Public
10244ac3afSJan Kiszka  * License as published by the Free Software Foundation; either
1161f3c91aSChetan Pant  * version 2.1 of the License, or (at your option) any later version.
12244ac3afSJan Kiszka  *
13244ac3afSJan Kiszka  * This library is distributed in the hope that it will be useful,
14244ac3afSJan Kiszka  * but WITHOUT ANY WARRANTY; without even the implied warranty of
15244ac3afSJan Kiszka  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
16244ac3afSJan Kiszka  * Lesser General Public License for more details.
17244ac3afSJan Kiszka  *
18244ac3afSJan Kiszka  * You should have received a copy of the GNU Lesser General Public
19244ac3afSJan Kiszka  * License along with this library; if not, see <http://www.gnu.org/licenses/>.
20244ac3afSJan Kiszka  */
21244ac3afSJan Kiszka 
22244ac3afSJan Kiszka #ifndef QEMU_IOAPIC_INTERNAL_H
23244ac3afSJan Kiszka #define QEMU_IOAPIC_INTERNAL_H
24244ac3afSJan Kiszka 
25022c62cbSPaolo Bonzini #include "exec/memory.h"
2683c9f4caSPaolo Bonzini #include "hw/sysbus.h"
27e3d9c925SPeter Xu #include "qemu/notify.h"
28db1015e9SEduardo Habkost #include "qom/object.h"
29244ac3afSJan Kiszka 
30*94c5a606SGerd Hoffmann #define MAX_IOAPICS                     2
31244ac3afSJan Kiszka 
32244ac3afSJan Kiszka #define IOAPIC_LVT_DEST_SHIFT           56
33cb135f59SPeter Xu #define IOAPIC_LVT_DEST_IDX_SHIFT       48
34244ac3afSJan Kiszka #define IOAPIC_LVT_MASKED_SHIFT         16
35244ac3afSJan Kiszka #define IOAPIC_LVT_TRIGGER_MODE_SHIFT   15
36244ac3afSJan Kiszka #define IOAPIC_LVT_REMOTE_IRR_SHIFT     14
37244ac3afSJan Kiszka #define IOAPIC_LVT_POLARITY_SHIFT       13
38244ac3afSJan Kiszka #define IOAPIC_LVT_DELIV_STATUS_SHIFT   12
39244ac3afSJan Kiszka #define IOAPIC_LVT_DEST_MODE_SHIFT      11
40244ac3afSJan Kiszka #define IOAPIC_LVT_DELIV_MODE_SHIFT     8
41244ac3afSJan Kiszka 
42244ac3afSJan Kiszka #define IOAPIC_LVT_MASKED               (1 << IOAPIC_LVT_MASKED_SHIFT)
43af599407SPavel Butsykin #define IOAPIC_LVT_TRIGGER_MODE         (1 << IOAPIC_LVT_TRIGGER_MODE_SHIFT)
44244ac3afSJan Kiszka #define IOAPIC_LVT_REMOTE_IRR           (1 << IOAPIC_LVT_REMOTE_IRR_SHIFT)
45af599407SPavel Butsykin #define IOAPIC_LVT_POLARITY             (1 << IOAPIC_LVT_POLARITY_SHIFT)
46af599407SPavel Butsykin #define IOAPIC_LVT_DELIV_STATUS         (1 << IOAPIC_LVT_DELIV_STATUS_SHIFT)
47af599407SPavel Butsykin #define IOAPIC_LVT_DEST_MODE            (1 << IOAPIC_LVT_DEST_MODE_SHIFT)
48af599407SPavel Butsykin #define IOAPIC_LVT_DELIV_MODE           (7 << IOAPIC_LVT_DELIV_MODE_SHIFT)
49244ac3afSJan Kiszka 
50479c2a1cSPeter Xu /* Bits that are read-only for IOAPIC entry */
51479c2a1cSPeter Xu #define IOAPIC_RO_BITS                  (IOAPIC_LVT_REMOTE_IRR | \
52479c2a1cSPeter Xu                                          IOAPIC_LVT_DELIV_STATUS)
53479c2a1cSPeter Xu #define IOAPIC_RW_BITS                  (~(uint64_t)IOAPIC_RO_BITS)
54479c2a1cSPeter Xu 
55244ac3afSJan Kiszka #define IOAPIC_TRIGGER_EDGE             0
56244ac3afSJan Kiszka #define IOAPIC_TRIGGER_LEVEL            1
57244ac3afSJan Kiszka 
58244ac3afSJan Kiszka /*io{apic,sapic} delivery mode*/
59244ac3afSJan Kiszka #define IOAPIC_DM_FIXED                 0x0
60244ac3afSJan Kiszka #define IOAPIC_DM_LOWEST_PRIORITY       0x1
61244ac3afSJan Kiszka #define IOAPIC_DM_PMI                   0x2
62244ac3afSJan Kiszka #define IOAPIC_DM_NMI                   0x4
63244ac3afSJan Kiszka #define IOAPIC_DM_INIT                  0x5
64244ac3afSJan Kiszka #define IOAPIC_DM_SIPI                  0x6
65244ac3afSJan Kiszka #define IOAPIC_DM_EXTINT                0x7
66244ac3afSJan Kiszka #define IOAPIC_DM_MASK                  0x7
67244ac3afSJan Kiszka 
68244ac3afSJan Kiszka #define IOAPIC_VECTOR_MASK              0xff
69244ac3afSJan Kiszka 
70244ac3afSJan Kiszka #define IOAPIC_IOREGSEL                 0x00
71244ac3afSJan Kiszka #define IOAPIC_IOWIN                    0x10
7220fd4b7bSPeter Xu #define IOAPIC_EOI                      0x40
73244ac3afSJan Kiszka 
74244ac3afSJan Kiszka #define IOAPIC_REG_ID                   0x00
75244ac3afSJan Kiszka #define IOAPIC_REG_VER                  0x01
76244ac3afSJan Kiszka #define IOAPIC_REG_ARB                  0x02
77244ac3afSJan Kiszka #define IOAPIC_REG_REDTBL_BASE          0x10
78244ac3afSJan Kiszka #define IOAPIC_ID                       0x00
79244ac3afSJan Kiszka 
80244ac3afSJan Kiszka #define IOAPIC_ID_SHIFT                 24
81244ac3afSJan Kiszka #define IOAPIC_ID_MASK                  0xf
82244ac3afSJan Kiszka 
83244ac3afSJan Kiszka #define IOAPIC_VER_ENTRIES_SHIFT        16
84244ac3afSJan Kiszka 
85244ac3afSJan Kiszka 
86999e12bbSAnthony Liguori #define TYPE_IOAPIC_COMMON "ioapic-common"
87a489d195SEduardo Habkost OBJECT_DECLARE_TYPE(IOAPICCommonState, IOAPICCommonClass, IOAPIC_COMMON)
88999e12bbSAnthony Liguori 
89db1015e9SEduardo Habkost struct IOAPICCommonClass {
90999e12bbSAnthony Liguori     SysBusDeviceClass parent_class;
91db0f8888Sxiaoqiang zhao 
92db0f8888Sxiaoqiang zhao     DeviceRealize realize;
93958a01daSVitaly Kuznetsov     DeviceUnrealize unrealize;
94999e12bbSAnthony Liguori     void (*pre_save)(IOAPICCommonState *s);
95999e12bbSAnthony Liguori     void (*post_load)(IOAPICCommonState *s);
96db1015e9SEduardo Habkost };
97999e12bbSAnthony Liguori 
98244ac3afSJan Kiszka struct IOAPICCommonState {
99244ac3afSJan Kiszka     SysBusDevice busdev;
100244ac3afSJan Kiszka     MemoryRegion io_memory;
101244ac3afSJan Kiszka     uint8_t id;
102244ac3afSJan Kiszka     uint8_t ioregsel;
103244ac3afSJan Kiszka     uint32_t irr;
104244ac3afSJan Kiszka     uint64_t ioredtbl[IOAPIC_NUM_PINS];
105e3d9c925SPeter Xu     Notifier machine_done;
10620fd4b7bSPeter Xu     uint8_t version;
107cce5405eSPeter Xu     uint64_t irq_count[IOAPIC_NUM_PINS];
108cce5405eSPeter Xu     int irq_level[IOAPIC_NUM_PINS];
109958a01daSVitaly Kuznetsov     int irq_eoi[IOAPIC_NUM_PINS];
110958a01daSVitaly Kuznetsov     QEMUTimer *delayed_ioapic_service_timer;
111244ac3afSJan Kiszka };
112244ac3afSJan Kiszka 
113244ac3afSJan Kiszka void ioapic_reset_common(DeviceState *dev);
114244ac3afSJan Kiszka 
115d665d696SPavel Butsykin void ioapic_print_redtbl(Monitor *mon, IOAPICCommonState *s);
116cce5405eSPeter Xu void ioapic_stat_update_irq(IOAPICCommonState *s, int irq, int level);
117d665d696SPavel Butsykin 
118175de524SMarkus Armbruster #endif /* QEMU_IOAPIC_INTERNAL_H */
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