1 /* 2 * ioapic.c IOAPIC emulation logic 3 * 4 * Copyright (c) 2004-2005 Fabrice Bellard 5 * 6 * Split the ioapic logic from apic.c 7 * Xiantao Zhang <xiantao.zhang@intel.com> 8 * 9 * This library is free software; you can redistribute it and/or 10 * modify it under the terms of the GNU Lesser General Public 11 * License as published by the Free Software Foundation; either 12 * version 2 of the License, or (at your option) any later version. 13 * 14 * This library is distributed in the hope that it will be useful, 15 * but WITHOUT ANY WARRANTY; without even the implied warranty of 16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 17 * Lesser General Public License for more details. 18 * 19 * You should have received a copy of the GNU Lesser General Public 20 * License along with this library; if not, see <http://www.gnu.org/licenses/>. 21 */ 22 23 #include "qemu/osdep.h" 24 #include "monitor/monitor.h" 25 #include "hw/hw.h" 26 #include "hw/i386/pc.h" 27 #include "hw/i386/apic.h" 28 #include "hw/i386/ioapic.h" 29 #include "hw/i386/ioapic_internal.h" 30 #include "include/hw/pci/msi.h" 31 #include "sysemu/kvm.h" 32 #include "target-i386/cpu.h" 33 #include "hw/i386/apic-msidef.h" 34 #include "hw/i386/x86-iommu.h" 35 36 //#define DEBUG_IOAPIC 37 38 #ifdef DEBUG_IOAPIC 39 #define DPRINTF(fmt, ...) \ 40 do { printf("ioapic: " fmt , ## __VA_ARGS__); } while (0) 41 #else 42 #define DPRINTF(fmt, ...) 43 #endif 44 45 #define APIC_DELIVERY_MODE_SHIFT 8 46 #define APIC_POLARITY_SHIFT 14 47 #define APIC_TRIG_MODE_SHIFT 15 48 49 static IOAPICCommonState *ioapics[MAX_IOAPICS]; 50 51 /* global variable from ioapic_common.c */ 52 extern int ioapic_no; 53 54 struct ioapic_entry_info { 55 /* fields parsed from IOAPIC entries */ 56 uint8_t masked; 57 uint8_t trig_mode; 58 uint16_t dest_idx; 59 uint8_t dest_mode; 60 uint8_t delivery_mode; 61 uint8_t vector; 62 63 /* MSI message generated from above parsed fields */ 64 uint32_t addr; 65 uint32_t data; 66 }; 67 68 static void ioapic_entry_parse(uint64_t entry, struct ioapic_entry_info *info) 69 { 70 memset(info, 0, sizeof(*info)); 71 info->masked = (entry >> IOAPIC_LVT_MASKED_SHIFT) & 1; 72 info->trig_mode = (entry >> IOAPIC_LVT_TRIGGER_MODE_SHIFT) & 1; 73 /* 74 * By default, this would be dest_id[8] + reserved[8]. When IR 75 * is enabled, this would be interrupt_index[15] + 76 * interrupt_format[1]. This field never means anything, but 77 * only used to generate corresponding MSI. 78 */ 79 info->dest_idx = (entry >> IOAPIC_LVT_DEST_IDX_SHIFT) & 0xffff; 80 info->dest_mode = (entry >> IOAPIC_LVT_DEST_MODE_SHIFT) & 1; 81 info->delivery_mode = (entry >> IOAPIC_LVT_DELIV_MODE_SHIFT) \ 82 & IOAPIC_DM_MASK; 83 if (info->delivery_mode == IOAPIC_DM_EXTINT) { 84 info->vector = pic_read_irq(isa_pic); 85 } else { 86 info->vector = entry & IOAPIC_VECTOR_MASK; 87 } 88 89 info->addr = APIC_DEFAULT_ADDRESS | \ 90 (info->dest_idx << MSI_ADDR_DEST_IDX_SHIFT) | \ 91 (info->dest_mode << MSI_ADDR_DEST_MODE_SHIFT); 92 info->data = (info->vector << MSI_DATA_VECTOR_SHIFT) | \ 93 (info->trig_mode << MSI_DATA_TRIGGER_SHIFT) | \ 94 (info->delivery_mode << MSI_DATA_DELIVERY_MODE_SHIFT); 95 } 96 97 static void ioapic_service(IOAPICCommonState *s) 98 { 99 AddressSpace *ioapic_as = PC_MACHINE(qdev_get_machine())->ioapic_as; 100 struct ioapic_entry_info info; 101 uint8_t i; 102 uint32_t mask; 103 uint64_t entry; 104 105 for (i = 0; i < IOAPIC_NUM_PINS; i++) { 106 mask = 1 << i; 107 if (s->irr & mask) { 108 int coalesce = 0; 109 110 entry = s->ioredtbl[i]; 111 ioapic_entry_parse(entry, &info); 112 if (!info.masked) { 113 if (info.trig_mode == IOAPIC_TRIGGER_EDGE) { 114 s->irr &= ~mask; 115 } else { 116 coalesce = s->ioredtbl[i] & IOAPIC_LVT_REMOTE_IRR; 117 s->ioredtbl[i] |= IOAPIC_LVT_REMOTE_IRR; 118 } 119 120 if (coalesce) { 121 /* We are level triggered interrupts, and the 122 * guest should be still working on previous one, 123 * so skip it. */ 124 continue; 125 } 126 127 #ifdef CONFIG_KVM 128 if (kvm_irqchip_is_split()) { 129 if (info.trig_mode == IOAPIC_TRIGGER_EDGE) { 130 kvm_set_irq(kvm_state, i, 1); 131 kvm_set_irq(kvm_state, i, 0); 132 } else { 133 kvm_set_irq(kvm_state, i, 1); 134 } 135 continue; 136 } 137 #endif 138 139 /* No matter whether IR is enabled, we translate 140 * the IOAPIC message into a MSI one, and its 141 * address space will decide whether we need a 142 * translation. */ 143 stl_le_phys(ioapic_as, info.addr, info.data); 144 } 145 } 146 } 147 } 148 149 static void ioapic_set_irq(void *opaque, int vector, int level) 150 { 151 IOAPICCommonState *s = opaque; 152 153 /* ISA IRQs map to GSI 1-1 except for IRQ0 which maps 154 * to GSI 2. GSI maps to ioapic 1-1. This is not 155 * the cleanest way of doing it but it should work. */ 156 157 DPRINTF("%s: %s vec %x\n", __func__, level ? "raise" : "lower", vector); 158 if (vector == 0) { 159 vector = 2; 160 } 161 if (vector >= 0 && vector < IOAPIC_NUM_PINS) { 162 uint32_t mask = 1 << vector; 163 uint64_t entry = s->ioredtbl[vector]; 164 165 if (((entry >> IOAPIC_LVT_TRIGGER_MODE_SHIFT) & 1) == 166 IOAPIC_TRIGGER_LEVEL) { 167 /* level triggered */ 168 if (level) { 169 s->irr |= mask; 170 if (!(entry & IOAPIC_LVT_REMOTE_IRR)) { 171 ioapic_service(s); 172 } 173 } else { 174 s->irr &= ~mask; 175 } 176 } else { 177 /* According to the 82093AA manual, we must ignore edge requests 178 * if the input pin is masked. */ 179 if (level && !(entry & IOAPIC_LVT_MASKED)) { 180 s->irr |= mask; 181 ioapic_service(s); 182 } 183 } 184 } 185 } 186 187 static void ioapic_update_kvm_routes(IOAPICCommonState *s) 188 { 189 #ifdef CONFIG_KVM 190 int i; 191 192 if (kvm_irqchip_is_split()) { 193 for (i = 0; i < IOAPIC_NUM_PINS; i++) { 194 MSIMessage msg; 195 struct ioapic_entry_info info; 196 ioapic_entry_parse(s->ioredtbl[i], &info); 197 msg.address = info.addr; 198 msg.data = info.data; 199 kvm_irqchip_update_msi_route(kvm_state, i, msg, NULL); 200 } 201 kvm_irqchip_commit_routes(kvm_state); 202 } 203 #endif 204 } 205 206 #ifdef CONFIG_KVM 207 static void ioapic_iec_notifier(void *private, bool global, 208 uint32_t index, uint32_t mask) 209 { 210 IOAPICCommonState *s = (IOAPICCommonState *)private; 211 /* For simplicity, we just update all the routes */ 212 ioapic_update_kvm_routes(s); 213 } 214 #endif 215 216 void ioapic_eoi_broadcast(int vector) 217 { 218 IOAPICCommonState *s; 219 uint64_t entry; 220 int i, n; 221 222 for (i = 0; i < MAX_IOAPICS; i++) { 223 s = ioapics[i]; 224 if (!s) { 225 continue; 226 } 227 for (n = 0; n < IOAPIC_NUM_PINS; n++) { 228 entry = s->ioredtbl[n]; 229 if ((entry & IOAPIC_LVT_REMOTE_IRR) 230 && (entry & IOAPIC_VECTOR_MASK) == vector) { 231 s->ioredtbl[n] = entry & ~IOAPIC_LVT_REMOTE_IRR; 232 if (!(entry & IOAPIC_LVT_MASKED) && (s->irr & (1 << n))) { 233 ioapic_service(s); 234 } 235 } 236 } 237 } 238 } 239 240 void ioapic_dump_state(Monitor *mon, const QDict *qdict) 241 { 242 int i; 243 244 for (i = 0; i < MAX_IOAPICS; i++) { 245 if (ioapics[i] != 0) { 246 ioapic_print_redtbl(mon, ioapics[i]); 247 } 248 } 249 } 250 251 static uint64_t 252 ioapic_mem_read(void *opaque, hwaddr addr, unsigned int size) 253 { 254 IOAPICCommonState *s = opaque; 255 int index; 256 uint32_t val = 0; 257 258 switch (addr & 0xff) { 259 case IOAPIC_IOREGSEL: 260 val = s->ioregsel; 261 break; 262 case IOAPIC_IOWIN: 263 if (size != 4) { 264 break; 265 } 266 switch (s->ioregsel) { 267 case IOAPIC_REG_ID: 268 case IOAPIC_REG_ARB: 269 val = s->id << IOAPIC_ID_SHIFT; 270 break; 271 case IOAPIC_REG_VER: 272 val = IOAPIC_VERSION | 273 ((IOAPIC_NUM_PINS - 1) << IOAPIC_VER_ENTRIES_SHIFT); 274 break; 275 default: 276 index = (s->ioregsel - IOAPIC_REG_REDTBL_BASE) >> 1; 277 if (index >= 0 && index < IOAPIC_NUM_PINS) { 278 if (s->ioregsel & 1) { 279 val = s->ioredtbl[index] >> 32; 280 } else { 281 val = s->ioredtbl[index] & 0xffffffff; 282 } 283 } 284 } 285 DPRINTF("read: %08x = %08x\n", s->ioregsel, val); 286 break; 287 } 288 return val; 289 } 290 291 /* 292 * This is to satisfy the hack in Linux kernel. One hack of it is to 293 * simulate clearing the Remote IRR bit of IOAPIC entry using the 294 * following: 295 * 296 * "For IO-APIC's with EOI register, we use that to do an explicit EOI. 297 * Otherwise, we simulate the EOI message manually by changing the trigger 298 * mode to edge and then back to level, with RTE being masked during 299 * this." 300 * 301 * (See linux kernel __eoi_ioapic_pin() comment in commit c0205701) 302 * 303 * This is based on the assumption that, Remote IRR bit will be 304 * cleared by IOAPIC hardware when configured as edge-triggered 305 * interrupts. 306 * 307 * Without this, level-triggered interrupts in IR mode might fail to 308 * work correctly. 309 */ 310 static inline void 311 ioapic_fix_edge_remote_irr(uint64_t *entry) 312 { 313 if (!(*entry & IOAPIC_LVT_TRIGGER_MODE)) { 314 /* Edge-triggered interrupts, make sure remote IRR is zero */ 315 *entry &= ~((uint64_t)IOAPIC_LVT_REMOTE_IRR); 316 } 317 } 318 319 static void 320 ioapic_mem_write(void *opaque, hwaddr addr, uint64_t val, 321 unsigned int size) 322 { 323 IOAPICCommonState *s = opaque; 324 int index; 325 326 switch (addr & 0xff) { 327 case IOAPIC_IOREGSEL: 328 s->ioregsel = val; 329 break; 330 case IOAPIC_IOWIN: 331 if (size != 4) { 332 break; 333 } 334 DPRINTF("write: %08x = %08" PRIx64 "\n", s->ioregsel, val); 335 switch (s->ioregsel) { 336 case IOAPIC_REG_ID: 337 s->id = (val >> IOAPIC_ID_SHIFT) & IOAPIC_ID_MASK; 338 break; 339 case IOAPIC_REG_VER: 340 case IOAPIC_REG_ARB: 341 break; 342 default: 343 index = (s->ioregsel - IOAPIC_REG_REDTBL_BASE) >> 1; 344 if (index >= 0 && index < IOAPIC_NUM_PINS) { 345 uint64_t ro_bits = s->ioredtbl[index] & IOAPIC_RO_BITS; 346 if (s->ioregsel & 1) { 347 s->ioredtbl[index] &= 0xffffffff; 348 s->ioredtbl[index] |= (uint64_t)val << 32; 349 } else { 350 s->ioredtbl[index] &= ~0xffffffffULL; 351 s->ioredtbl[index] |= val; 352 } 353 /* restore RO bits */ 354 s->ioredtbl[index] &= IOAPIC_RW_BITS; 355 s->ioredtbl[index] |= ro_bits; 356 ioapic_fix_edge_remote_irr(&s->ioredtbl[index]); 357 ioapic_service(s); 358 } 359 } 360 break; 361 } 362 363 ioapic_update_kvm_routes(s); 364 } 365 366 static const MemoryRegionOps ioapic_io_ops = { 367 .read = ioapic_mem_read, 368 .write = ioapic_mem_write, 369 .endianness = DEVICE_NATIVE_ENDIAN, 370 }; 371 372 static void ioapic_machine_done_notify(Notifier *notifier, void *data) 373 { 374 #ifdef CONFIG_KVM 375 IOAPICCommonState *s = container_of(notifier, IOAPICCommonState, 376 machine_done); 377 378 if (kvm_irqchip_is_split()) { 379 X86IOMMUState *iommu = x86_iommu_get_default(); 380 if (iommu) { 381 /* Register this IOAPIC with IOMMU IEC notifier, so that 382 * when there are IR invalidates, we can be notified to 383 * update kernel IR cache. */ 384 x86_iommu_iec_register_notifier(iommu, ioapic_iec_notifier, s); 385 } 386 } 387 #endif 388 } 389 390 static void ioapic_realize(DeviceState *dev, Error **errp) 391 { 392 IOAPICCommonState *s = IOAPIC_COMMON(dev); 393 394 memory_region_init_io(&s->io_memory, OBJECT(s), &ioapic_io_ops, s, 395 "ioapic", 0x1000); 396 397 qdev_init_gpio_in(dev, ioapic_set_irq, IOAPIC_NUM_PINS); 398 399 ioapics[ioapic_no] = s; 400 s->machine_done.notify = ioapic_machine_done_notify; 401 qemu_add_machine_init_done_notifier(&s->machine_done); 402 } 403 404 static void ioapic_class_init(ObjectClass *klass, void *data) 405 { 406 IOAPICCommonClass *k = IOAPIC_COMMON_CLASS(klass); 407 DeviceClass *dc = DEVICE_CLASS(klass); 408 409 k->realize = ioapic_realize; 410 dc->reset = ioapic_reset_common; 411 } 412 413 static const TypeInfo ioapic_info = { 414 .name = "ioapic", 415 .parent = TYPE_IOAPIC_COMMON, 416 .instance_size = sizeof(IOAPICCommonState), 417 .class_init = ioapic_class_init, 418 }; 419 420 static void ioapic_register_types(void) 421 { 422 type_register_static(&ioapic_info); 423 } 424 425 type_init(ioapic_register_types) 426