1610626afSaliguori /* 2610626afSaliguori * ioapic.c IOAPIC emulation logic 3610626afSaliguori * 4610626afSaliguori * Copyright (c) 2004-2005 Fabrice Bellard 5610626afSaliguori * 6610626afSaliguori * Split the ioapic logic from apic.c 7610626afSaliguori * Xiantao Zhang <xiantao.zhang@intel.com> 8610626afSaliguori * 9610626afSaliguori * This library is free software; you can redistribute it and/or 10610626afSaliguori * modify it under the terms of the GNU Lesser General Public 11610626afSaliguori * License as published by the Free Software Foundation; either 12610626afSaliguori * version 2 of the License, or (at your option) any later version. 13610626afSaliguori * 14610626afSaliguori * This library is distributed in the hope that it will be useful, 15610626afSaliguori * but WITHOUT ANY WARRANTY; without even the implied warranty of 16610626afSaliguori * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 17610626afSaliguori * Lesser General Public License for more details. 18610626afSaliguori * 19610626afSaliguori * You should have received a copy of the GNU Lesser General Public 208167ee88SBlue Swirl * License along with this library; if not, see <http://www.gnu.org/licenses/>. 21610626afSaliguori */ 22610626afSaliguori 23b6a0aa05SPeter Maydell #include "qemu/osdep.h" 2411ab69d6SMarkus Armbruster #include "qapi/error.h" 256bde8fd6SPavel Butsykin #include "monitor/monitor.h" 2683c9f4caSPaolo Bonzini #include "hw/hw.h" 270d09e41aSPaolo Bonzini #include "hw/i386/pc.h" 28d613f8ccSPaolo Bonzini #include "hw/i386/apic.h" 290d09e41aSPaolo Bonzini #include "hw/i386/ioapic.h" 300d09e41aSPaolo Bonzini #include "hw/i386/ioapic_internal.h" 31455e17a1SMichael S. Tsirkin #include "hw/pci/msi.h" 3215eafc2eSPaolo Bonzini #include "sysemu/kvm.h" 33cb135f59SPeter Xu #include "hw/i386/apic-msidef.h" 34e3d9c925SPeter Xu #include "hw/i386/x86-iommu.h" 35e5074b38SPeter Xu #include "trace.h" 36610626afSaliguori 3715eafc2eSPaolo Bonzini #define APIC_DELIVERY_MODE_SHIFT 8 3815eafc2eSPaolo Bonzini #define APIC_POLARITY_SHIFT 14 3915eafc2eSPaolo Bonzini #define APIC_TRIG_MODE_SHIFT 15 4015eafc2eSPaolo Bonzini 41244ac3afSJan Kiszka static IOAPICCommonState *ioapics[MAX_IOAPICS]; 420280b571SJan Kiszka 43db0f8888Sxiaoqiang zhao /* global variable from ioapic_common.c */ 44db0f8888Sxiaoqiang zhao extern int ioapic_no; 45db0f8888Sxiaoqiang zhao 46c15fa0beSPeter Xu struct ioapic_entry_info { 47c15fa0beSPeter Xu /* fields parsed from IOAPIC entries */ 48c15fa0beSPeter Xu uint8_t masked; 49c15fa0beSPeter Xu uint8_t trig_mode; 50c15fa0beSPeter Xu uint16_t dest_idx; 51c15fa0beSPeter Xu uint8_t dest_mode; 52c15fa0beSPeter Xu uint8_t delivery_mode; 53c15fa0beSPeter Xu uint8_t vector; 54c15fa0beSPeter Xu 55c15fa0beSPeter Xu /* MSI message generated from above parsed fields */ 56c15fa0beSPeter Xu uint32_t addr; 57c15fa0beSPeter Xu uint32_t data; 58c15fa0beSPeter Xu }; 59c15fa0beSPeter Xu 60c15fa0beSPeter Xu static void ioapic_entry_parse(uint64_t entry, struct ioapic_entry_info *info) 61c15fa0beSPeter Xu { 62c15fa0beSPeter Xu memset(info, 0, sizeof(*info)); 63c15fa0beSPeter Xu info->masked = (entry >> IOAPIC_LVT_MASKED_SHIFT) & 1; 64c15fa0beSPeter Xu info->trig_mode = (entry >> IOAPIC_LVT_TRIGGER_MODE_SHIFT) & 1; 65c15fa0beSPeter Xu /* 66c15fa0beSPeter Xu * By default, this would be dest_id[8] + reserved[8]. When IR 67c15fa0beSPeter Xu * is enabled, this would be interrupt_index[15] + 68c15fa0beSPeter Xu * interrupt_format[1]. This field never means anything, but 69c15fa0beSPeter Xu * only used to generate corresponding MSI. 70c15fa0beSPeter Xu */ 71c15fa0beSPeter Xu info->dest_idx = (entry >> IOAPIC_LVT_DEST_IDX_SHIFT) & 0xffff; 72c15fa0beSPeter Xu info->dest_mode = (entry >> IOAPIC_LVT_DEST_MODE_SHIFT) & 1; 73c15fa0beSPeter Xu info->delivery_mode = (entry >> IOAPIC_LVT_DELIV_MODE_SHIFT) \ 74c15fa0beSPeter Xu & IOAPIC_DM_MASK; 75c15fa0beSPeter Xu if (info->delivery_mode == IOAPIC_DM_EXTINT) { 76c15fa0beSPeter Xu info->vector = pic_read_irq(isa_pic); 77c15fa0beSPeter Xu } else { 78c15fa0beSPeter Xu info->vector = entry & IOAPIC_VECTOR_MASK; 79c15fa0beSPeter Xu } 80c15fa0beSPeter Xu 81c15fa0beSPeter Xu info->addr = APIC_DEFAULT_ADDRESS | \ 82c15fa0beSPeter Xu (info->dest_idx << MSI_ADDR_DEST_IDX_SHIFT) | \ 83c15fa0beSPeter Xu (info->dest_mode << MSI_ADDR_DEST_MODE_SHIFT); 84c15fa0beSPeter Xu info->data = (info->vector << MSI_DATA_VECTOR_SHIFT) | \ 85c15fa0beSPeter Xu (info->trig_mode << MSI_DATA_TRIGGER_SHIFT) | \ 86c15fa0beSPeter Xu (info->delivery_mode << MSI_DATA_DELIVERY_MODE_SHIFT); 87c15fa0beSPeter Xu } 88c15fa0beSPeter Xu 89244ac3afSJan Kiszka static void ioapic_service(IOAPICCommonState *s) 90610626afSaliguori { 91cb135f59SPeter Xu AddressSpace *ioapic_as = PC_MACHINE(qdev_get_machine())->ioapic_as; 92c15fa0beSPeter Xu struct ioapic_entry_info info; 93610626afSaliguori uint8_t i; 94610626afSaliguori uint32_t mask; 95610626afSaliguori uint64_t entry; 96610626afSaliguori 97610626afSaliguori for (i = 0; i < IOAPIC_NUM_PINS; i++) { 98610626afSaliguori mask = 1 << i; 99610626afSaliguori if (s->irr & mask) { 10015eafc2eSPaolo Bonzini int coalesce = 0; 10115eafc2eSPaolo Bonzini 102610626afSaliguori entry = s->ioredtbl[i]; 103c15fa0beSPeter Xu ioapic_entry_parse(entry, &info); 104c15fa0beSPeter Xu if (!info.masked) { 105c15fa0beSPeter Xu if (info.trig_mode == IOAPIC_TRIGGER_EDGE) { 106610626afSaliguori s->irr &= ~mask; 1070280b571SJan Kiszka } else { 10815eafc2eSPaolo Bonzini coalesce = s->ioredtbl[i] & IOAPIC_LVT_REMOTE_IRR; 109e5074b38SPeter Xu trace_ioapic_set_remote_irr(i); 1100280b571SJan Kiszka s->ioredtbl[i] |= IOAPIC_LVT_REMOTE_IRR; 1110280b571SJan Kiszka } 112c15fa0beSPeter Xu 113f99b86b9SPeter Xu if (coalesce) { 114f99b86b9SPeter Xu /* We are level triggered interrupts, and the 115f99b86b9SPeter Xu * guest should be still working on previous one, 116f99b86b9SPeter Xu * so skip it. */ 117f99b86b9SPeter Xu continue; 118f99b86b9SPeter Xu } 119f99b86b9SPeter Xu 12015eafc2eSPaolo Bonzini #ifdef CONFIG_KVM 12115eafc2eSPaolo Bonzini if (kvm_irqchip_is_split()) { 122c15fa0beSPeter Xu if (info.trig_mode == IOAPIC_TRIGGER_EDGE) { 12315eafc2eSPaolo Bonzini kvm_set_irq(kvm_state, i, 1); 12415eafc2eSPaolo Bonzini kvm_set_irq(kvm_state, i, 0); 12515eafc2eSPaolo Bonzini } else { 12615eafc2eSPaolo Bonzini kvm_set_irq(kvm_state, i, 1); 12715eafc2eSPaolo Bonzini } 12815eafc2eSPaolo Bonzini continue; 12915eafc2eSPaolo Bonzini } 13015eafc2eSPaolo Bonzini #endif 131f99b86b9SPeter Xu 132cb135f59SPeter Xu /* No matter whether IR is enabled, we translate 133cb135f59SPeter Xu * the IOAPIC message into a MSI one, and its 134cb135f59SPeter Xu * address space will decide whether we need a 135cb135f59SPeter Xu * translation. */ 136c15fa0beSPeter Xu stl_le_phys(ioapic_as, info.addr, info.data); 137610626afSaliguori } 138610626afSaliguori } 139610626afSaliguori } 140610626afSaliguori } 141610626afSaliguori 142*958a01daSVitaly Kuznetsov #define SUCCESSIVE_IRQ_MAX_COUNT 10000 143*958a01daSVitaly Kuznetsov 144*958a01daSVitaly Kuznetsov static void delayed_ioapic_service_cb(void *opaque) 145*958a01daSVitaly Kuznetsov { 146*958a01daSVitaly Kuznetsov IOAPICCommonState *s = opaque; 147*958a01daSVitaly Kuznetsov 148*958a01daSVitaly Kuznetsov ioapic_service(s); 149*958a01daSVitaly Kuznetsov } 150*958a01daSVitaly Kuznetsov 1517d0500c4SBlue Swirl static void ioapic_set_irq(void *opaque, int vector, int level) 152610626afSaliguori { 153244ac3afSJan Kiszka IOAPICCommonState *s = opaque; 154610626afSaliguori 155610626afSaliguori /* ISA IRQs map to GSI 1-1 except for IRQ0 which maps 156610626afSaliguori * to GSI 2. GSI maps to ioapic 1-1. This is not 157610626afSaliguori * the cleanest way of doing it but it should work. */ 158610626afSaliguori 159a2e6ffabSDr. David Alan Gilbert trace_ioapic_set_irq(vector, level); 160cce5405eSPeter Xu ioapic_stat_update_irq(s, vector, level); 1611f5e71a8SJan Kiszka if (vector == 0) { 162610626afSaliguori vector = 2; 1631f5e71a8SJan Kiszka } 164960a479fSPaolo Bonzini if (vector < IOAPIC_NUM_PINS) { 165610626afSaliguori uint32_t mask = 1 << vector; 166610626afSaliguori uint64_t entry = s->ioredtbl[vector]; 167610626afSaliguori 1681f5e71a8SJan Kiszka if (((entry >> IOAPIC_LVT_TRIGGER_MODE_SHIFT) & 1) == 1691f5e71a8SJan Kiszka IOAPIC_TRIGGER_LEVEL) { 170610626afSaliguori /* level triggered */ 171610626afSaliguori if (level) { 172610626afSaliguori s->irr |= mask; 173c5955a56SPaolo Bonzini if (!(entry & IOAPIC_LVT_REMOTE_IRR)) { 174610626afSaliguori ioapic_service(s); 175c5955a56SPaolo Bonzini } 176610626afSaliguori } else { 177610626afSaliguori s->irr &= ~mask; 178610626afSaliguori } 179610626afSaliguori } else { 18047f7be39SJan Kiszka /* According to the 82093AA manual, we must ignore edge requests 18147f7be39SJan Kiszka * if the input pin is masked. */ 18247f7be39SJan Kiszka if (level && !(entry & IOAPIC_LVT_MASKED)) { 183610626afSaliguori s->irr |= mask; 184610626afSaliguori ioapic_service(s); 185610626afSaliguori } 186610626afSaliguori } 187610626afSaliguori } 188610626afSaliguori } 189610626afSaliguori 19015eafc2eSPaolo Bonzini static void ioapic_update_kvm_routes(IOAPICCommonState *s) 19115eafc2eSPaolo Bonzini { 19215eafc2eSPaolo Bonzini #ifdef CONFIG_KVM 19315eafc2eSPaolo Bonzini int i; 19415eafc2eSPaolo Bonzini 19515eafc2eSPaolo Bonzini if (kvm_irqchip_is_split()) { 19615eafc2eSPaolo Bonzini for (i = 0; i < IOAPIC_NUM_PINS; i++) { 19715eafc2eSPaolo Bonzini MSIMessage msg; 198c15fa0beSPeter Xu struct ioapic_entry_info info; 199c15fa0beSPeter Xu ioapic_entry_parse(s->ioredtbl[i], &info); 200c15fa0beSPeter Xu msg.address = info.addr; 201c15fa0beSPeter Xu msg.data = info.data; 20215eafc2eSPaolo Bonzini kvm_irqchip_update_msi_route(kvm_state, i, msg, NULL); 20315eafc2eSPaolo Bonzini } 20415eafc2eSPaolo Bonzini kvm_irqchip_commit_routes(kvm_state); 20515eafc2eSPaolo Bonzini } 20615eafc2eSPaolo Bonzini #endif 20715eafc2eSPaolo Bonzini } 20815eafc2eSPaolo Bonzini 209e3d9c925SPeter Xu #ifdef CONFIG_KVM 210e3d9c925SPeter Xu static void ioapic_iec_notifier(void *private, bool global, 211e3d9c925SPeter Xu uint32_t index, uint32_t mask) 212e3d9c925SPeter Xu { 213e3d9c925SPeter Xu IOAPICCommonState *s = (IOAPICCommonState *)private; 214e3d9c925SPeter Xu /* For simplicity, we just update all the routes */ 215e3d9c925SPeter Xu ioapic_update_kvm_routes(s); 216e3d9c925SPeter Xu } 217e3d9c925SPeter Xu #endif 218e3d9c925SPeter Xu 2190280b571SJan Kiszka void ioapic_eoi_broadcast(int vector) 2200280b571SJan Kiszka { 221244ac3afSJan Kiszka IOAPICCommonState *s; 2220280b571SJan Kiszka uint64_t entry; 2230280b571SJan Kiszka int i, n; 2240280b571SJan Kiszka 225e5074b38SPeter Xu trace_ioapic_eoi_broadcast(vector); 226e5074b38SPeter Xu 2270280b571SJan Kiszka for (i = 0; i < MAX_IOAPICS; i++) { 2280280b571SJan Kiszka s = ioapics[i]; 2290280b571SJan Kiszka if (!s) { 2300280b571SJan Kiszka continue; 2310280b571SJan Kiszka } 2320280b571SJan Kiszka for (n = 0; n < IOAPIC_NUM_PINS; n++) { 2330280b571SJan Kiszka entry = s->ioredtbl[n]; 234*958a01daSVitaly Kuznetsov 235*958a01daSVitaly Kuznetsov if ((entry & IOAPIC_VECTOR_MASK) != vector || 236*958a01daSVitaly Kuznetsov ((entry >> IOAPIC_LVT_TRIGGER_MODE_SHIFT) & 1) != IOAPIC_TRIGGER_LEVEL) { 237*958a01daSVitaly Kuznetsov continue; 238*958a01daSVitaly Kuznetsov } 239*958a01daSVitaly Kuznetsov 240*958a01daSVitaly Kuznetsov if (!(entry & IOAPIC_LVT_REMOTE_IRR)) { 241*958a01daSVitaly Kuznetsov continue; 242*958a01daSVitaly Kuznetsov } 243*958a01daSVitaly Kuznetsov 244e5074b38SPeter Xu trace_ioapic_clear_remote_irr(n, vector); 2450280b571SJan Kiszka s->ioredtbl[n] = entry & ~IOAPIC_LVT_REMOTE_IRR; 246*958a01daSVitaly Kuznetsov 2470280b571SJan Kiszka if (!(entry & IOAPIC_LVT_MASKED) && (s->irr & (1 << n))) { 248*958a01daSVitaly Kuznetsov ++s->irq_eoi[vector]; 249*958a01daSVitaly Kuznetsov if (s->irq_eoi[vector] >= SUCCESSIVE_IRQ_MAX_COUNT) { 250*958a01daSVitaly Kuznetsov /* 251*958a01daSVitaly Kuznetsov * Real hardware does not deliver the interrupt immediately 252*958a01daSVitaly Kuznetsov * during eoi broadcast, and this lets a buggy guest make 253*958a01daSVitaly Kuznetsov * slow progress even if it does not correctly handle a 254*958a01daSVitaly Kuznetsov * level-triggered interrupt. Emulate this behavior if we 255*958a01daSVitaly Kuznetsov * detect an interrupt storm. 256*958a01daSVitaly Kuznetsov */ 257*958a01daSVitaly Kuznetsov s->irq_eoi[vector] = 0; 258*958a01daSVitaly Kuznetsov timer_mod_anticipate(s->delayed_ioapic_service_timer, 259*958a01daSVitaly Kuznetsov qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) + 260*958a01daSVitaly Kuznetsov NANOSECONDS_PER_SECOND / 100); 261*958a01daSVitaly Kuznetsov trace_ioapic_eoi_delayed_reassert(vector); 262*958a01daSVitaly Kuznetsov } else { 2630280b571SJan Kiszka ioapic_service(s); 2640280b571SJan Kiszka } 265*958a01daSVitaly Kuznetsov } else { 266*958a01daSVitaly Kuznetsov s->irq_eoi[vector] = 0; 2670280b571SJan Kiszka } 2680280b571SJan Kiszka } 2690280b571SJan Kiszka } 2700280b571SJan Kiszka } 2710280b571SJan Kiszka 2724d5bf5f6SJan Kiszka static uint64_t 273a8170e5eSAvi Kivity ioapic_mem_read(void *opaque, hwaddr addr, unsigned int size) 274610626afSaliguori { 275244ac3afSJan Kiszka IOAPICCommonState *s = opaque; 276610626afSaliguori int index; 277610626afSaliguori uint32_t val = 0; 278610626afSaliguori 279e5074b38SPeter Xu addr &= 0xff; 280e5074b38SPeter Xu 281e5074b38SPeter Xu switch (addr) { 2821f5e71a8SJan Kiszka case IOAPIC_IOREGSEL: 283610626afSaliguori val = s->ioregsel; 2841f5e71a8SJan Kiszka break; 2851f5e71a8SJan Kiszka case IOAPIC_IOWIN: 2861a440963SJan Kiszka if (size != 4) { 2871a440963SJan Kiszka break; 2881a440963SJan Kiszka } 289610626afSaliguori switch (s->ioregsel) { 2901f5e71a8SJan Kiszka case IOAPIC_REG_ID: 2912f5a3b12SPaolo Bonzini case IOAPIC_REG_ARB: 2921f5e71a8SJan Kiszka val = s->id << IOAPIC_ID_SHIFT; 293610626afSaliguori break; 2941f5e71a8SJan Kiszka case IOAPIC_REG_VER: 29520fd4b7bSPeter Xu val = s->version | 2961f5e71a8SJan Kiszka ((IOAPIC_NUM_PINS - 1) << IOAPIC_VER_ENTRIES_SHIFT); 297610626afSaliguori break; 298610626afSaliguori default: 2991f5e71a8SJan Kiszka index = (s->ioregsel - IOAPIC_REG_REDTBL_BASE) >> 1; 300610626afSaliguori if (index >= 0 && index < IOAPIC_NUM_PINS) { 3011f5e71a8SJan Kiszka if (s->ioregsel & 1) { 302610626afSaliguori val = s->ioredtbl[index] >> 32; 3031f5e71a8SJan Kiszka } else { 304610626afSaliguori val = s->ioredtbl[index] & 0xffffffff; 305610626afSaliguori } 306610626afSaliguori } 3071f5e71a8SJan Kiszka } 3081f5e71a8SJan Kiszka break; 309610626afSaliguori } 310e5074b38SPeter Xu 311a2e6ffabSDr. David Alan Gilbert trace_ioapic_mem_read(addr, s->ioregsel, size, val); 312e5074b38SPeter Xu 313610626afSaliguori return val; 314610626afSaliguori } 315610626afSaliguori 316ed1263c3SPeter Xu /* 317ed1263c3SPeter Xu * This is to satisfy the hack in Linux kernel. One hack of it is to 318ed1263c3SPeter Xu * simulate clearing the Remote IRR bit of IOAPIC entry using the 319ed1263c3SPeter Xu * following: 320ed1263c3SPeter Xu * 321ed1263c3SPeter Xu * "For IO-APIC's with EOI register, we use that to do an explicit EOI. 322ed1263c3SPeter Xu * Otherwise, we simulate the EOI message manually by changing the trigger 323ed1263c3SPeter Xu * mode to edge and then back to level, with RTE being masked during 324ed1263c3SPeter Xu * this." 325ed1263c3SPeter Xu * 326ed1263c3SPeter Xu * (See linux kernel __eoi_ioapic_pin() comment in commit c0205701) 327ed1263c3SPeter Xu * 328ed1263c3SPeter Xu * This is based on the assumption that, Remote IRR bit will be 329ed1263c3SPeter Xu * cleared by IOAPIC hardware when configured as edge-triggered 330ed1263c3SPeter Xu * interrupts. 331ed1263c3SPeter Xu * 332ed1263c3SPeter Xu * Without this, level-triggered interrupts in IR mode might fail to 333ed1263c3SPeter Xu * work correctly. 334ed1263c3SPeter Xu */ 335ed1263c3SPeter Xu static inline void 336ed1263c3SPeter Xu ioapic_fix_edge_remote_irr(uint64_t *entry) 337ed1263c3SPeter Xu { 338ed1263c3SPeter Xu if (!(*entry & IOAPIC_LVT_TRIGGER_MODE)) { 339ed1263c3SPeter Xu /* Edge-triggered interrupts, make sure remote IRR is zero */ 340ed1263c3SPeter Xu *entry &= ~((uint64_t)IOAPIC_LVT_REMOTE_IRR); 341ed1263c3SPeter Xu } 342ed1263c3SPeter Xu } 343ed1263c3SPeter Xu 3441f5e71a8SJan Kiszka static void 345a8170e5eSAvi Kivity ioapic_mem_write(void *opaque, hwaddr addr, uint64_t val, 3464d5bf5f6SJan Kiszka unsigned int size) 347610626afSaliguori { 348244ac3afSJan Kiszka IOAPICCommonState *s = opaque; 349610626afSaliguori int index; 350610626afSaliguori 351e5074b38SPeter Xu addr &= 0xff; 352a2e6ffabSDr. David Alan Gilbert trace_ioapic_mem_write(addr, s->ioregsel, size, val); 353e5074b38SPeter Xu 354e5074b38SPeter Xu switch (addr) { 3551f5e71a8SJan Kiszka case IOAPIC_IOREGSEL: 356610626afSaliguori s->ioregsel = val; 3571f5e71a8SJan Kiszka break; 3581f5e71a8SJan Kiszka case IOAPIC_IOWIN: 3591a440963SJan Kiszka if (size != 4) { 3601a440963SJan Kiszka break; 3611a440963SJan Kiszka } 362610626afSaliguori switch (s->ioregsel) { 3631f5e71a8SJan Kiszka case IOAPIC_REG_ID: 3641f5e71a8SJan Kiszka s->id = (val >> IOAPIC_ID_SHIFT) & IOAPIC_ID_MASK; 3651f5e71a8SJan Kiszka break; 3661f5e71a8SJan Kiszka case IOAPIC_REG_VER: 3671f5e71a8SJan Kiszka case IOAPIC_REG_ARB: 3681f5e71a8SJan Kiszka break; 369610626afSaliguori default: 3701f5e71a8SJan Kiszka index = (s->ioregsel - IOAPIC_REG_REDTBL_BASE) >> 1; 371610626afSaliguori if (index >= 0 && index < IOAPIC_NUM_PINS) { 372479c2a1cSPeter Xu uint64_t ro_bits = s->ioredtbl[index] & IOAPIC_RO_BITS; 373610626afSaliguori if (s->ioregsel & 1) { 374610626afSaliguori s->ioredtbl[index] &= 0xffffffff; 375610626afSaliguori s->ioredtbl[index] |= (uint64_t)val << 32; 376610626afSaliguori } else { 377610626afSaliguori s->ioredtbl[index] &= ~0xffffffffULL; 378610626afSaliguori s->ioredtbl[index] |= val; 379610626afSaliguori } 380479c2a1cSPeter Xu /* restore RO bits */ 381479c2a1cSPeter Xu s->ioredtbl[index] &= IOAPIC_RW_BITS; 382479c2a1cSPeter Xu s->ioredtbl[index] |= ro_bits; 383ed1263c3SPeter Xu ioapic_fix_edge_remote_irr(&s->ioredtbl[index]); 384610626afSaliguori ioapic_service(s); 385610626afSaliguori } 386610626afSaliguori } 3871f5e71a8SJan Kiszka break; 38820fd4b7bSPeter Xu case IOAPIC_EOI: 38920fd4b7bSPeter Xu /* Explicit EOI is only supported for IOAPIC version 0x20 */ 39020fd4b7bSPeter Xu if (size != 4 || s->version != 0x20) { 39120fd4b7bSPeter Xu break; 39220fd4b7bSPeter Xu } 39320fd4b7bSPeter Xu ioapic_eoi_broadcast(val); 39420fd4b7bSPeter Xu break; 395610626afSaliguori } 39615eafc2eSPaolo Bonzini 39715eafc2eSPaolo Bonzini ioapic_update_kvm_routes(s); 398610626afSaliguori } 399610626afSaliguori 4004d5bf5f6SJan Kiszka static const MemoryRegionOps ioapic_io_ops = { 4014d5bf5f6SJan Kiszka .read = ioapic_mem_read, 4024d5bf5f6SJan Kiszka .write = ioapic_mem_write, 4034d5bf5f6SJan Kiszka .endianness = DEVICE_NATIVE_ENDIAN, 404610626afSaliguori }; 405610626afSaliguori 406e3d9c925SPeter Xu static void ioapic_machine_done_notify(Notifier *notifier, void *data) 407e3d9c925SPeter Xu { 408e3d9c925SPeter Xu #ifdef CONFIG_KVM 409e3d9c925SPeter Xu IOAPICCommonState *s = container_of(notifier, IOAPICCommonState, 410e3d9c925SPeter Xu machine_done); 411e3d9c925SPeter Xu 412e3d9c925SPeter Xu if (kvm_irqchip_is_split()) { 413e3d9c925SPeter Xu X86IOMMUState *iommu = x86_iommu_get_default(); 414e3d9c925SPeter Xu if (iommu) { 415e3d9c925SPeter Xu /* Register this IOAPIC with IOMMU IEC notifier, so that 416e3d9c925SPeter Xu * when there are IR invalidates, we can be notified to 417e3d9c925SPeter Xu * update kernel IR cache. */ 418e3d9c925SPeter Xu x86_iommu_iec_register_notifier(iommu, ioapic_iec_notifier, s); 419e3d9c925SPeter Xu } 420e3d9c925SPeter Xu } 421e3d9c925SPeter Xu #endif 422e3d9c925SPeter Xu } 423e3d9c925SPeter Xu 4248d5516beSPeter Xu #define IOAPIC_VER_DEF 0x20 4258d5516beSPeter Xu 426db0f8888Sxiaoqiang zhao static void ioapic_realize(DeviceState *dev, Error **errp) 427610626afSaliguori { 428db0f8888Sxiaoqiang zhao IOAPICCommonState *s = IOAPIC_COMMON(dev); 429f9771858Sxiaoqiang zhao 43020fd4b7bSPeter Xu if (s->version != 0x11 && s->version != 0x20) { 43111ab69d6SMarkus Armbruster error_setg(errp, "IOAPIC only supports version 0x11 or 0x20 " 4328d5516beSPeter Xu "(default: 0x%x).", IOAPIC_VER_DEF); 43311ab69d6SMarkus Armbruster return; 43420fd4b7bSPeter Xu } 43520fd4b7bSPeter Xu 4361437c94bSPaolo Bonzini memory_region_init_io(&s->io_memory, OBJECT(s), &ioapic_io_ops, s, 4371437c94bSPaolo Bonzini "ioapic", 0x1000); 438610626afSaliguori 439*958a01daSVitaly Kuznetsov s->delayed_ioapic_service_timer = 440*958a01daSVitaly Kuznetsov timer_new_ns(QEMU_CLOCK_VIRTUAL, delayed_ioapic_service_cb, s); 441*958a01daSVitaly Kuznetsov 442f9771858Sxiaoqiang zhao qdev_init_gpio_in(dev, ioapic_set_irq, IOAPIC_NUM_PINS); 443610626afSaliguori 444db0f8888Sxiaoqiang zhao ioapics[ioapic_no] = s; 445e3d9c925SPeter Xu s->machine_done.notify = ioapic_machine_done_notify; 446e3d9c925SPeter Xu qemu_add_machine_init_done_notifier(&s->machine_done); 447610626afSaliguori } 44896051119SBlue Swirl 449*958a01daSVitaly Kuznetsov static void ioapic_unrealize(DeviceState *dev, Error **errp) 450*958a01daSVitaly Kuznetsov { 451*958a01daSVitaly Kuznetsov IOAPICCommonState *s = IOAPIC_COMMON(dev); 452*958a01daSVitaly Kuznetsov 453*958a01daSVitaly Kuznetsov timer_del(s->delayed_ioapic_service_timer); 454*958a01daSVitaly Kuznetsov timer_free(s->delayed_ioapic_service_timer); 455*958a01daSVitaly Kuznetsov } 456*958a01daSVitaly Kuznetsov 45720fd4b7bSPeter Xu static Property ioapic_properties[] = { 4588d5516beSPeter Xu DEFINE_PROP_UINT8("version", IOAPICCommonState, version, IOAPIC_VER_DEF), 45920fd4b7bSPeter Xu DEFINE_PROP_END_OF_LIST(), 46020fd4b7bSPeter Xu }; 46120fd4b7bSPeter Xu 462999e12bbSAnthony Liguori static void ioapic_class_init(ObjectClass *klass, void *data) 463999e12bbSAnthony Liguori { 464999e12bbSAnthony Liguori IOAPICCommonClass *k = IOAPIC_COMMON_CLASS(klass); 46539bffca2SAnthony Liguori DeviceClass *dc = DEVICE_CLASS(klass); 466999e12bbSAnthony Liguori 467db0f8888Sxiaoqiang zhao k->realize = ioapic_realize; 468*958a01daSVitaly Kuznetsov k->unrealize = ioapic_unrealize; 4690f254b1aSPeter Xu /* 4700f254b1aSPeter Xu * If APIC is in kernel, we need to update the kernel cache after 4710f254b1aSPeter Xu * migration, otherwise first 24 gsi routes will be invalid. 4720f254b1aSPeter Xu */ 4730f254b1aSPeter Xu k->post_load = ioapic_update_kvm_routes; 47439bffca2SAnthony Liguori dc->reset = ioapic_reset_common; 47520fd4b7bSPeter Xu dc->props = ioapic_properties; 476999e12bbSAnthony Liguori } 477999e12bbSAnthony Liguori 4788c43a6f0SAndreas Färber static const TypeInfo ioapic_info = { 47934bec7a8SLi Qiang .name = TYPE_IOAPIC, 48039bffca2SAnthony Liguori .parent = TYPE_IOAPIC_COMMON, 48139bffca2SAnthony Liguori .instance_size = sizeof(IOAPICCommonState), 482999e12bbSAnthony Liguori .class_init = ioapic_class_init, 48396051119SBlue Swirl }; 48496051119SBlue Swirl 48583f7d43aSAndreas Färber static void ioapic_register_types(void) 48696051119SBlue Swirl { 48739bffca2SAnthony Liguori type_register_static(&ioapic_info); 48896051119SBlue Swirl } 48996051119SBlue Swirl 49083f7d43aSAndreas Färber type_init(ioapic_register_types) 491