1 /* 2 * QEMU 8259 interrupt controller emulation 3 * 4 * Copyright (c) 2003-2004 Fabrice Bellard 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a copy 7 * of this software and associated documentation files (the "Software"), to deal 8 * in the Software without restriction, including without limitation the rights 9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 10 * copies of the Software, and to permit persons to whom the Software is 11 * furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice shall be included in 14 * all copies or substantial portions of the Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN 22 * THE SOFTWARE. 23 */ 24 #include "vl.h" 25 26 /* debug PIC */ 27 //#define DEBUG_PIC 28 29 //#define DEBUG_IRQ_LATENCY 30 //#define DEBUG_IRQ_COUNT 31 32 typedef struct PicState { 33 uint8_t last_irr; /* edge detection */ 34 uint8_t irr; /* interrupt request register */ 35 uint8_t imr; /* interrupt mask register */ 36 uint8_t isr; /* interrupt service register */ 37 uint8_t priority_add; /* highest irq priority */ 38 uint8_t irq_base; 39 uint8_t read_reg_select; 40 uint8_t poll; 41 uint8_t special_mask; 42 uint8_t init_state; 43 uint8_t auto_eoi; 44 uint8_t rotate_on_auto_eoi; 45 uint8_t special_fully_nested_mode; 46 uint8_t init4; /* true if 4 byte init */ 47 uint8_t single_mode; /* true if slave pic is not initialized */ 48 uint8_t elcr; /* PIIX edge/trigger selection*/ 49 uint8_t elcr_mask; 50 PicState2 *pics_state; 51 } PicState; 52 53 struct PicState2 { 54 /* 0 is master pic, 1 is slave pic */ 55 /* XXX: better separation between the two pics */ 56 PicState pics[2]; 57 qemu_irq parent_irq; 58 void *irq_request_opaque; 59 /* IOAPIC callback support */ 60 SetIRQFunc *alt_irq_func; 61 void *alt_irq_opaque; 62 }; 63 64 #if defined(DEBUG_PIC) || defined (DEBUG_IRQ_COUNT) 65 static int irq_level[16]; 66 #endif 67 #ifdef DEBUG_IRQ_COUNT 68 static uint64_t irq_count[16]; 69 #endif 70 71 /* set irq level. If an edge is detected, then the IRR is set to 1 */ 72 static inline void pic_set_irq1(PicState *s, int irq, int level) 73 { 74 int mask; 75 mask = 1 << irq; 76 if (s->elcr & mask) { 77 /* level triggered */ 78 if (level) { 79 s->irr |= mask; 80 s->last_irr |= mask; 81 } else { 82 s->irr &= ~mask; 83 s->last_irr &= ~mask; 84 } 85 } else { 86 /* edge triggered */ 87 if (level) { 88 if ((s->last_irr & mask) == 0) 89 s->irr |= mask; 90 s->last_irr |= mask; 91 } else { 92 s->last_irr &= ~mask; 93 } 94 } 95 } 96 97 /* return the highest priority found in mask (highest = smallest 98 number). Return 8 if no irq */ 99 static inline int get_priority(PicState *s, int mask) 100 { 101 int priority; 102 if (mask == 0) 103 return 8; 104 priority = 0; 105 while ((mask & (1 << ((priority + s->priority_add) & 7))) == 0) 106 priority++; 107 return priority; 108 } 109 110 /* return the pic wanted interrupt. return -1 if none */ 111 static int pic_get_irq(PicState *s) 112 { 113 int mask, cur_priority, priority; 114 115 mask = s->irr & ~s->imr; 116 priority = get_priority(s, mask); 117 if (priority == 8) 118 return -1; 119 /* compute current priority. If special fully nested mode on the 120 master, the IRQ coming from the slave is not taken into account 121 for the priority computation. */ 122 mask = s->isr; 123 if (s->special_fully_nested_mode && s == &s->pics_state->pics[0]) 124 mask &= ~(1 << 2); 125 cur_priority = get_priority(s, mask); 126 if (priority < cur_priority) { 127 /* higher priority found: an irq should be generated */ 128 return (priority + s->priority_add) & 7; 129 } else { 130 return -1; 131 } 132 } 133 134 /* raise irq to CPU if necessary. must be called every time the active 135 irq may change */ 136 /* XXX: should not export it, but it is needed for an APIC kludge */ 137 void pic_update_irq(PicState2 *s) 138 { 139 int irq2, irq; 140 141 /* first look at slave pic */ 142 irq2 = pic_get_irq(&s->pics[1]); 143 if (irq2 >= 0) { 144 /* if irq request by slave pic, signal master PIC */ 145 pic_set_irq1(&s->pics[0], 2, 1); 146 pic_set_irq1(&s->pics[0], 2, 0); 147 } 148 /* look at requested irq */ 149 irq = pic_get_irq(&s->pics[0]); 150 if (irq >= 0) { 151 #if defined(DEBUG_PIC) 152 { 153 int i; 154 for(i = 0; i < 2; i++) { 155 printf("pic%d: imr=%x irr=%x padd=%d\n", 156 i, s->pics[i].imr, s->pics[i].irr, 157 s->pics[i].priority_add); 158 159 } 160 } 161 printf("pic: cpu_interrupt\n"); 162 #endif 163 qemu_irq_raise(s->parent_irq); 164 } 165 166 /* all targets should do this rather than acking the IRQ in the cpu */ 167 #if defined(TARGET_MIPS) 168 else { 169 qemu_irq_lower(s->parent_irq); 170 } 171 #endif 172 } 173 174 #ifdef DEBUG_IRQ_LATENCY 175 int64_t irq_time[16]; 176 #endif 177 178 void i8259_set_irq(void *opaque, int irq, int level) 179 { 180 PicState2 *s = opaque; 181 182 #if defined(DEBUG_PIC) || defined(DEBUG_IRQ_COUNT) 183 if (level != irq_level[irq]) { 184 #if defined(DEBUG_PIC) 185 printf("i8259_set_irq: irq=%d level=%d\n", irq, level); 186 #endif 187 irq_level[irq] = level; 188 #ifdef DEBUG_IRQ_COUNT 189 if (level == 1) 190 irq_count[irq]++; 191 #endif 192 } 193 #endif 194 #ifdef DEBUG_IRQ_LATENCY 195 if (level) { 196 irq_time[irq] = qemu_get_clock(vm_clock); 197 } 198 #endif 199 pic_set_irq1(&s->pics[irq >> 3], irq & 7, level); 200 /* used for IOAPIC irqs */ 201 if (s->alt_irq_func) 202 s->alt_irq_func(s->alt_irq_opaque, irq, level); 203 pic_update_irq(s); 204 } 205 206 /* acknowledge interrupt 'irq' */ 207 static inline void pic_intack(PicState *s, int irq) 208 { 209 if (s->auto_eoi) { 210 if (s->rotate_on_auto_eoi) 211 s->priority_add = (irq + 1) & 7; 212 } else { 213 s->isr |= (1 << irq); 214 } 215 /* We don't clear a level sensitive interrupt here */ 216 if (!(s->elcr & (1 << irq))) 217 s->irr &= ~(1 << irq); 218 } 219 220 int pic_read_irq(PicState2 *s) 221 { 222 int irq, irq2, intno; 223 224 irq = pic_get_irq(&s->pics[0]); 225 if (irq >= 0) { 226 pic_intack(&s->pics[0], irq); 227 if (irq == 2) { 228 irq2 = pic_get_irq(&s->pics[1]); 229 if (irq2 >= 0) { 230 pic_intack(&s->pics[1], irq2); 231 } else { 232 /* spurious IRQ on slave controller */ 233 irq2 = 7; 234 } 235 intno = s->pics[1].irq_base + irq2; 236 irq = irq2 + 8; 237 } else { 238 intno = s->pics[0].irq_base + irq; 239 } 240 } else { 241 /* spurious IRQ on host controller */ 242 irq = 7; 243 intno = s->pics[0].irq_base + irq; 244 } 245 pic_update_irq(s); 246 247 #ifdef DEBUG_IRQ_LATENCY 248 printf("IRQ%d latency=%0.3fus\n", 249 irq, 250 (double)(qemu_get_clock(vm_clock) - irq_time[irq]) * 1000000.0 / ticks_per_sec); 251 #endif 252 #if defined(DEBUG_PIC) 253 printf("pic_interrupt: irq=%d\n", irq); 254 #endif 255 return intno; 256 } 257 258 static void pic_reset(void *opaque) 259 { 260 PicState *s = opaque; 261 262 s->last_irr = 0; 263 s->irr = 0; 264 s->imr = 0; 265 s->isr = 0; 266 s->priority_add = 0; 267 s->irq_base = 0; 268 s->read_reg_select = 0; 269 s->poll = 0; 270 s->special_mask = 0; 271 s->init_state = 0; 272 s->auto_eoi = 0; 273 s->rotate_on_auto_eoi = 0; 274 s->special_fully_nested_mode = 0; 275 s->init4 = 0; 276 s->single_mode = 0; 277 /* Note: ELCR is not reset */ 278 } 279 280 static void pic_ioport_write(void *opaque, uint32_t addr, uint32_t val) 281 { 282 PicState *s = opaque; 283 int priority, cmd, irq; 284 285 #ifdef DEBUG_PIC 286 printf("pic_write: addr=0x%02x val=0x%02x\n", addr, val); 287 #endif 288 addr &= 1; 289 if (addr == 0) { 290 if (val & 0x10) { 291 /* init */ 292 pic_reset(s); 293 /* deassert a pending interrupt */ 294 qemu_irq_lower(s->pics_state->parent_irq); 295 s->init_state = 1; 296 s->init4 = val & 1; 297 s->single_mode = val & 2; 298 if (val & 0x08) 299 hw_error("level sensitive irq not supported"); 300 } else if (val & 0x08) { 301 if (val & 0x04) 302 s->poll = 1; 303 if (val & 0x02) 304 s->read_reg_select = val & 1; 305 if (val & 0x40) 306 s->special_mask = (val >> 5) & 1; 307 } else { 308 cmd = val >> 5; 309 switch(cmd) { 310 case 0: 311 case 4: 312 s->rotate_on_auto_eoi = cmd >> 2; 313 break; 314 case 1: /* end of interrupt */ 315 case 5: 316 priority = get_priority(s, s->isr); 317 if (priority != 8) { 318 irq = (priority + s->priority_add) & 7; 319 s->isr &= ~(1 << irq); 320 if (cmd == 5) 321 s->priority_add = (irq + 1) & 7; 322 pic_update_irq(s->pics_state); 323 } 324 break; 325 case 3: 326 irq = val & 7; 327 s->isr &= ~(1 << irq); 328 pic_update_irq(s->pics_state); 329 break; 330 case 6: 331 s->priority_add = (val + 1) & 7; 332 pic_update_irq(s->pics_state); 333 break; 334 case 7: 335 irq = val & 7; 336 s->isr &= ~(1 << irq); 337 s->priority_add = (irq + 1) & 7; 338 pic_update_irq(s->pics_state); 339 break; 340 default: 341 /* no operation */ 342 break; 343 } 344 } 345 } else { 346 switch(s->init_state) { 347 case 0: 348 /* normal mode */ 349 s->imr = val; 350 pic_update_irq(s->pics_state); 351 break; 352 case 1: 353 s->irq_base = val & 0xf8; 354 s->init_state = s->single_mode && s->init4 ? 3 : 2; 355 break; 356 case 2: 357 if (s->init4) { 358 s->init_state = 3; 359 } else { 360 s->init_state = 0; 361 } 362 break; 363 case 3: 364 s->special_fully_nested_mode = (val >> 4) & 1; 365 s->auto_eoi = (val >> 1) & 1; 366 s->init_state = 0; 367 break; 368 } 369 } 370 } 371 372 static uint32_t pic_poll_read (PicState *s, uint32_t addr1) 373 { 374 int ret; 375 376 ret = pic_get_irq(s); 377 if (ret >= 0) { 378 if (addr1 >> 7) { 379 s->pics_state->pics[0].isr &= ~(1 << 2); 380 s->pics_state->pics[0].irr &= ~(1 << 2); 381 } 382 s->irr &= ~(1 << ret); 383 s->isr &= ~(1 << ret); 384 if (addr1 >> 7 || ret != 2) 385 pic_update_irq(s->pics_state); 386 } else { 387 ret = 0x07; 388 pic_update_irq(s->pics_state); 389 } 390 391 return ret; 392 } 393 394 static uint32_t pic_ioport_read(void *opaque, uint32_t addr1) 395 { 396 PicState *s = opaque; 397 unsigned int addr; 398 int ret; 399 400 addr = addr1; 401 addr &= 1; 402 if (s->poll) { 403 ret = pic_poll_read(s, addr1); 404 s->poll = 0; 405 } else { 406 if (addr == 0) { 407 if (s->read_reg_select) 408 ret = s->isr; 409 else 410 ret = s->irr; 411 } else { 412 ret = s->imr; 413 } 414 } 415 #ifdef DEBUG_PIC 416 printf("pic_read: addr=0x%02x val=0x%02x\n", addr1, ret); 417 #endif 418 return ret; 419 } 420 421 /* memory mapped interrupt status */ 422 /* XXX: may be the same than pic_read_irq() */ 423 uint32_t pic_intack_read(PicState2 *s) 424 { 425 int ret; 426 427 ret = pic_poll_read(&s->pics[0], 0x00); 428 if (ret == 2) 429 ret = pic_poll_read(&s->pics[1], 0x80) + 8; 430 /* Prepare for ISR read */ 431 s->pics[0].read_reg_select = 1; 432 433 return ret; 434 } 435 436 static void elcr_ioport_write(void *opaque, uint32_t addr, uint32_t val) 437 { 438 PicState *s = opaque; 439 s->elcr = val & s->elcr_mask; 440 } 441 442 static uint32_t elcr_ioport_read(void *opaque, uint32_t addr1) 443 { 444 PicState *s = opaque; 445 return s->elcr; 446 } 447 448 static void pic_save(QEMUFile *f, void *opaque) 449 { 450 PicState *s = opaque; 451 452 qemu_put_8s(f, &s->last_irr); 453 qemu_put_8s(f, &s->irr); 454 qemu_put_8s(f, &s->imr); 455 qemu_put_8s(f, &s->isr); 456 qemu_put_8s(f, &s->priority_add); 457 qemu_put_8s(f, &s->irq_base); 458 qemu_put_8s(f, &s->read_reg_select); 459 qemu_put_8s(f, &s->poll); 460 qemu_put_8s(f, &s->special_mask); 461 qemu_put_8s(f, &s->init_state); 462 qemu_put_8s(f, &s->auto_eoi); 463 qemu_put_8s(f, &s->rotate_on_auto_eoi); 464 qemu_put_8s(f, &s->special_fully_nested_mode); 465 qemu_put_8s(f, &s->init4); 466 qemu_put_8s(f, &s->single_mode); 467 qemu_put_8s(f, &s->elcr); 468 } 469 470 static int pic_load(QEMUFile *f, void *opaque, int version_id) 471 { 472 PicState *s = opaque; 473 474 if (version_id != 1) 475 return -EINVAL; 476 477 qemu_get_8s(f, &s->last_irr); 478 qemu_get_8s(f, &s->irr); 479 qemu_get_8s(f, &s->imr); 480 qemu_get_8s(f, &s->isr); 481 qemu_get_8s(f, &s->priority_add); 482 qemu_get_8s(f, &s->irq_base); 483 qemu_get_8s(f, &s->read_reg_select); 484 qemu_get_8s(f, &s->poll); 485 qemu_get_8s(f, &s->special_mask); 486 qemu_get_8s(f, &s->init_state); 487 qemu_get_8s(f, &s->auto_eoi); 488 qemu_get_8s(f, &s->rotate_on_auto_eoi); 489 qemu_get_8s(f, &s->special_fully_nested_mode); 490 qemu_get_8s(f, &s->init4); 491 qemu_get_8s(f, &s->single_mode); 492 qemu_get_8s(f, &s->elcr); 493 return 0; 494 } 495 496 /* XXX: add generic master/slave system */ 497 static void pic_init1(int io_addr, int elcr_addr, PicState *s) 498 { 499 register_ioport_write(io_addr, 2, 1, pic_ioport_write, s); 500 register_ioport_read(io_addr, 2, 1, pic_ioport_read, s); 501 if (elcr_addr >= 0) { 502 register_ioport_write(elcr_addr, 1, 1, elcr_ioport_write, s); 503 register_ioport_read(elcr_addr, 1, 1, elcr_ioport_read, s); 504 } 505 register_savevm("i8259", io_addr, 1, pic_save, pic_load, s); 506 qemu_register_reset(pic_reset, s); 507 } 508 509 void pic_info(void) 510 { 511 int i; 512 PicState *s; 513 514 if (!isa_pic) 515 return; 516 517 for(i=0;i<2;i++) { 518 s = &isa_pic->pics[i]; 519 term_printf("pic%d: irr=%02x imr=%02x isr=%02x hprio=%d irq_base=%02x rr_sel=%d elcr=%02x fnm=%d\n", 520 i, s->irr, s->imr, s->isr, s->priority_add, 521 s->irq_base, s->read_reg_select, s->elcr, 522 s->special_fully_nested_mode); 523 } 524 } 525 526 void irq_info(void) 527 { 528 #ifndef DEBUG_IRQ_COUNT 529 term_printf("irq statistic code not compiled.\n"); 530 #else 531 int i; 532 int64_t count; 533 534 term_printf("IRQ statistics:\n"); 535 for (i = 0; i < 16; i++) { 536 count = irq_count[i]; 537 if (count > 0) 538 term_printf("%2d: %" PRId64 "\n", i, count); 539 } 540 #endif 541 } 542 543 qemu_irq *i8259_init(qemu_irq parent_irq) 544 { 545 PicState2 *s; 546 547 s = qemu_mallocz(sizeof(PicState2)); 548 if (!s) 549 return NULL; 550 pic_init1(0x20, 0x4d0, &s->pics[0]); 551 pic_init1(0xa0, 0x4d1, &s->pics[1]); 552 s->pics[0].elcr_mask = 0xf8; 553 s->pics[1].elcr_mask = 0xde; 554 s->parent_irq = parent_irq; 555 s->pics[0].pics_state = s; 556 s->pics[1].pics_state = s; 557 isa_pic = s; 558 return qemu_allocate_irqs(i8259_set_irq, s, 16); 559 } 560 561 void pic_set_alt_irq_func(PicState2 *s, SetIRQFunc *alt_irq_func, 562 void *alt_irq_opaque) 563 { 564 s->alt_irq_func = alt_irq_func; 565 s->alt_irq_opaque = alt_irq_opaque; 566 } 567