107e2034dSPavel Fedin /* 207e2034dSPavel Fedin * ARM GICv3 support - internal interfaces 307e2034dSPavel Fedin * 407e2034dSPavel Fedin * Copyright (c) 2012 Linaro Limited 507e2034dSPavel Fedin * Copyright (c) 2015 Huawei. 607e2034dSPavel Fedin * Copyright (c) 2015 Samsung Electronics Co., Ltd. 707e2034dSPavel Fedin * Written by Peter Maydell 807e2034dSPavel Fedin * Reworked for GICv3 by Shlomo Pongratz and Pavel Fedin 907e2034dSPavel Fedin * 1007e2034dSPavel Fedin * This program is free software; you can redistribute it and/or modify 1107e2034dSPavel Fedin * it under the terms of the GNU General Public License as published by 1207e2034dSPavel Fedin * the Free Software Foundation, either version 2 of the License, or 1307e2034dSPavel Fedin * (at your option) any later version. 1407e2034dSPavel Fedin * 1507e2034dSPavel Fedin * This program is distributed in the hope that it will be useful, 1607e2034dSPavel Fedin * but WITHOUT ANY WARRANTY; without even the implied warranty of 1707e2034dSPavel Fedin * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 1807e2034dSPavel Fedin * GNU General Public License for more details. 1907e2034dSPavel Fedin * 2007e2034dSPavel Fedin * You should have received a copy of the GNU General Public License along 2107e2034dSPavel Fedin * with this program; if not, see <http://www.gnu.org/licenses/>. 2207e2034dSPavel Fedin */ 2307e2034dSPavel Fedin 2407e2034dSPavel Fedin #ifndef QEMU_ARM_GICV3_INTERNAL_H 2507e2034dSPavel Fedin #define QEMU_ARM_GICV3_INTERNAL_H 2607e2034dSPavel Fedin 2718f6290aSShashi Mallela #include "hw/registerfields.h" 2807e2034dSPavel Fedin #include "hw/intc/arm_gicv3_common.h" 2907e2034dSPavel Fedin 3007e2034dSPavel Fedin /* Distributor registers, as offsets from the distributor base address */ 3107e2034dSPavel Fedin #define GICD_CTLR 0x0000 3207e2034dSPavel Fedin #define GICD_TYPER 0x0004 3307e2034dSPavel Fedin #define GICD_IIDR 0x0008 3407e2034dSPavel Fedin #define GICD_STATUSR 0x0010 3507e2034dSPavel Fedin #define GICD_SETSPI_NSR 0x0040 3607e2034dSPavel Fedin #define GICD_CLRSPI_NSR 0x0048 3707e2034dSPavel Fedin #define GICD_SETSPI_SR 0x0050 3807e2034dSPavel Fedin #define GICD_CLRSPI_SR 0x0058 3907e2034dSPavel Fedin #define GICD_SEIR 0x0068 4007e2034dSPavel Fedin #define GICD_IGROUPR 0x0080 4107e2034dSPavel Fedin #define GICD_ISENABLER 0x0100 4207e2034dSPavel Fedin #define GICD_ICENABLER 0x0180 4307e2034dSPavel Fedin #define GICD_ISPENDR 0x0200 4407e2034dSPavel Fedin #define GICD_ICPENDR 0x0280 4507e2034dSPavel Fedin #define GICD_ISACTIVER 0x0300 4607e2034dSPavel Fedin #define GICD_ICACTIVER 0x0380 4707e2034dSPavel Fedin #define GICD_IPRIORITYR 0x0400 4807e2034dSPavel Fedin #define GICD_ITARGETSR 0x0800 4907e2034dSPavel Fedin #define GICD_ICFGR 0x0C00 5007e2034dSPavel Fedin #define GICD_IGRPMODR 0x0D00 5107e2034dSPavel Fedin #define GICD_NSACR 0x0E00 5207e2034dSPavel Fedin #define GICD_SGIR 0x0F00 5307e2034dSPavel Fedin #define GICD_CPENDSGIR 0x0F10 5407e2034dSPavel Fedin #define GICD_SPENDSGIR 0x0F20 5507e2034dSPavel Fedin #define GICD_IROUTER 0x6000 5607e2034dSPavel Fedin #define GICD_IDREGS 0xFFD0 5707e2034dSPavel Fedin 5807e2034dSPavel Fedin /* GICD_CTLR fields */ 5907e2034dSPavel Fedin #define GICD_CTLR_EN_GRP0 (1U << 0) 6007e2034dSPavel Fedin #define GICD_CTLR_EN_GRP1NS (1U << 1) /* GICv3 5.3.20 */ 6107e2034dSPavel Fedin #define GICD_CTLR_EN_GRP1S (1U << 2) 6207e2034dSPavel Fedin #define GICD_CTLR_EN_GRP1_ALL (GICD_CTLR_EN_GRP1NS | GICD_CTLR_EN_GRP1S) 6307e2034dSPavel Fedin /* Bit 4 is ARE if the system doesn't support TrustZone, ARE_S otherwise */ 6407e2034dSPavel Fedin #define GICD_CTLR_ARE (1U << 4) 6507e2034dSPavel Fedin #define GICD_CTLR_ARE_S (1U << 4) 6607e2034dSPavel Fedin #define GICD_CTLR_ARE_NS (1U << 5) 6707e2034dSPavel Fedin #define GICD_CTLR_DS (1U << 6) 6807e2034dSPavel Fedin #define GICD_CTLR_E1NWF (1U << 7) 6907e2034dSPavel Fedin #define GICD_CTLR_RWP (1U << 31) 7007e2034dSPavel Fedin 71ac30dec3SShashi Mallela #define GICD_TYPER_LPIS_SHIFT 17 72ac30dec3SShashi Mallela 7318f6290aSShashi Mallela /* 16 bits EventId */ 7418f6290aSShashi Mallela #define GICD_TYPER_IDBITS 0xf 7518f6290aSShashi Mallela 7607e2034dSPavel Fedin /* 7707e2034dSPavel Fedin * Redistributor frame offsets from RD_base 7807e2034dSPavel Fedin */ 7907e2034dSPavel Fedin #define GICR_SGI_OFFSET 0x10000 8007e2034dSPavel Fedin 8107e2034dSPavel Fedin /* 8207e2034dSPavel Fedin * Redistributor registers, offsets from RD_base 8307e2034dSPavel Fedin */ 8407e2034dSPavel Fedin #define GICR_CTLR 0x0000 8507e2034dSPavel Fedin #define GICR_IIDR 0x0004 8607e2034dSPavel Fedin #define GICR_TYPER 0x0008 8707e2034dSPavel Fedin #define GICR_STATUSR 0x0010 8807e2034dSPavel Fedin #define GICR_WAKER 0x0014 8907e2034dSPavel Fedin #define GICR_SETLPIR 0x0040 9007e2034dSPavel Fedin #define GICR_CLRLPIR 0x0048 9107e2034dSPavel Fedin #define GICR_PROPBASER 0x0070 9207e2034dSPavel Fedin #define GICR_PENDBASER 0x0078 9307e2034dSPavel Fedin #define GICR_INVLPIR 0x00A0 9407e2034dSPavel Fedin #define GICR_INVALLR 0x00B0 9507e2034dSPavel Fedin #define GICR_SYNCR 0x00C0 9607e2034dSPavel Fedin #define GICR_IDREGS 0xFFD0 9707e2034dSPavel Fedin 9807e2034dSPavel Fedin /* SGI and PPI Redistributor registers, offsets from RD_base */ 9907e2034dSPavel Fedin #define GICR_IGROUPR0 (GICR_SGI_OFFSET + 0x0080) 10007e2034dSPavel Fedin #define GICR_ISENABLER0 (GICR_SGI_OFFSET + 0x0100) 10107e2034dSPavel Fedin #define GICR_ICENABLER0 (GICR_SGI_OFFSET + 0x0180) 10207e2034dSPavel Fedin #define GICR_ISPENDR0 (GICR_SGI_OFFSET + 0x0200) 10307e2034dSPavel Fedin #define GICR_ICPENDR0 (GICR_SGI_OFFSET + 0x0280) 10407e2034dSPavel Fedin #define GICR_ISACTIVER0 (GICR_SGI_OFFSET + 0x0300) 10507e2034dSPavel Fedin #define GICR_ICACTIVER0 (GICR_SGI_OFFSET + 0x0380) 10607e2034dSPavel Fedin #define GICR_IPRIORITYR (GICR_SGI_OFFSET + 0x0400) 10707e2034dSPavel Fedin #define GICR_ICFGR0 (GICR_SGI_OFFSET + 0x0C00) 10807e2034dSPavel Fedin #define GICR_ICFGR1 (GICR_SGI_OFFSET + 0x0C04) 10907e2034dSPavel Fedin #define GICR_IGRPMODR0 (GICR_SGI_OFFSET + 0x0D00) 11007e2034dSPavel Fedin #define GICR_NSACR (GICR_SGI_OFFSET + 0x0E00) 11107e2034dSPavel Fedin 11207e2034dSPavel Fedin #define GICR_CTLR_ENABLE_LPIS (1U << 0) 11307e2034dSPavel Fedin #define GICR_CTLR_RWP (1U << 3) 11407e2034dSPavel Fedin #define GICR_CTLR_DPG0 (1U << 24) 11507e2034dSPavel Fedin #define GICR_CTLR_DPG1NS (1U << 25) 11607e2034dSPavel Fedin #define GICR_CTLR_DPG1S (1U << 26) 11707e2034dSPavel Fedin #define GICR_CTLR_UWP (1U << 31) 11807e2034dSPavel Fedin 11907e2034dSPavel Fedin #define GICR_TYPER_PLPIS (1U << 0) 12007e2034dSPavel Fedin #define GICR_TYPER_VLPIS (1U << 1) 12107e2034dSPavel Fedin #define GICR_TYPER_DIRECTLPI (1U << 3) 12207e2034dSPavel Fedin #define GICR_TYPER_LAST (1U << 4) 12307e2034dSPavel Fedin #define GICR_TYPER_DPGS (1U << 5) 12407e2034dSPavel Fedin #define GICR_TYPER_PROCNUM (0xFFFFU << 8) 12507e2034dSPavel Fedin #define GICR_TYPER_COMMONLPIAFF (0x3 << 24) 12607e2034dSPavel Fedin #define GICR_TYPER_AFFINITYVALUE (0xFFFFFFFFULL << 32) 12707e2034dSPavel Fedin 12807e2034dSPavel Fedin #define GICR_WAKER_ProcessorSleep (1U << 1) 12907e2034dSPavel Fedin #define GICR_WAKER_ChildrenAsleep (1U << 2) 13007e2034dSPavel Fedin 13118f6290aSShashi Mallela FIELD(GICR_PROPBASER, IDBITS, 0, 5) 13218f6290aSShashi Mallela FIELD(GICR_PROPBASER, INNERCACHE, 7, 3) 13318f6290aSShashi Mallela FIELD(GICR_PROPBASER, SHAREABILITY, 10, 2) 13418f6290aSShashi Mallela FIELD(GICR_PROPBASER, PHYADDR, 12, 40) 13518f6290aSShashi Mallela FIELD(GICR_PROPBASER, OUTERCACHE, 56, 3) 13607e2034dSPavel Fedin 13718f6290aSShashi Mallela FIELD(GICR_PENDBASER, INNERCACHE, 7, 3) 13818f6290aSShashi Mallela FIELD(GICR_PENDBASER, SHAREABILITY, 10, 2) 13918f6290aSShashi Mallela FIELD(GICR_PENDBASER, PHYADDR, 16, 36) 14018f6290aSShashi Mallela FIELD(GICR_PENDBASER, OUTERCACHE, 56, 3) 14118f6290aSShashi Mallela FIELD(GICR_PENDBASER, PTZ, 62, 1) 14207e2034dSPavel Fedin 14317fb5e36SShashi Mallela #define GICR_PROPBASER_IDBITS_THRESHOLD 0xd 14417fb5e36SShashi Mallela 14507e2034dSPavel Fedin #define ICC_CTLR_EL1_CBPR (1U << 0) 14607e2034dSPavel Fedin #define ICC_CTLR_EL1_EOIMODE (1U << 1) 14707e2034dSPavel Fedin #define ICC_CTLR_EL1_PMHE (1U << 6) 14807e2034dSPavel Fedin #define ICC_CTLR_EL1_PRIBITS_SHIFT 8 149367b9f52SVijaya Kumar K #define ICC_CTLR_EL1_PRIBITS_MASK (7U << ICC_CTLR_EL1_PRIBITS_SHIFT) 15007e2034dSPavel Fedin #define ICC_CTLR_EL1_IDBITS_SHIFT 11 15107e2034dSPavel Fedin #define ICC_CTLR_EL1_SEIS (1U << 14) 15207e2034dSPavel Fedin #define ICC_CTLR_EL1_A3V (1U << 15) 15307e2034dSPavel Fedin 15407e2034dSPavel Fedin #define ICC_PMR_PRIORITY_MASK 0xff 15507e2034dSPavel Fedin #define ICC_BPR_BINARYPOINT_MASK 0x07 15607e2034dSPavel Fedin #define ICC_IGRPEN_ENABLE 0x01 15707e2034dSPavel Fedin 15807e2034dSPavel Fedin #define ICC_CTLR_EL3_CBPR_EL1S (1U << 0) 15907e2034dSPavel Fedin #define ICC_CTLR_EL3_CBPR_EL1NS (1U << 1) 16007e2034dSPavel Fedin #define ICC_CTLR_EL3_EOIMODE_EL3 (1U << 2) 16107e2034dSPavel Fedin #define ICC_CTLR_EL3_EOIMODE_EL1S (1U << 3) 16207e2034dSPavel Fedin #define ICC_CTLR_EL3_EOIMODE_EL1NS (1U << 4) 16307e2034dSPavel Fedin #define ICC_CTLR_EL3_RM (1U << 5) 16407e2034dSPavel Fedin #define ICC_CTLR_EL3_PMHE (1U << 6) 16507e2034dSPavel Fedin #define ICC_CTLR_EL3_PRIBITS_SHIFT 8 16607e2034dSPavel Fedin #define ICC_CTLR_EL3_IDBITS_SHIFT 11 16707e2034dSPavel Fedin #define ICC_CTLR_EL3_SEIS (1U << 14) 16807e2034dSPavel Fedin #define ICC_CTLR_EL3_A3V (1U << 15) 16907e2034dSPavel Fedin #define ICC_CTLR_EL3_NDS (1U << 17) 17007e2034dSPavel Fedin 171e69d2fa0SPeter Maydell #define ICH_VMCR_EL2_VENG0_SHIFT 0 172e69d2fa0SPeter Maydell #define ICH_VMCR_EL2_VENG0 (1U << ICH_VMCR_EL2_VENG0_SHIFT) 173e69d2fa0SPeter Maydell #define ICH_VMCR_EL2_VENG1_SHIFT 1 174e69d2fa0SPeter Maydell #define ICH_VMCR_EL2_VENG1 (1U << ICH_VMCR_EL2_VENG1_SHIFT) 175e69d2fa0SPeter Maydell #define ICH_VMCR_EL2_VACKCTL (1U << 2) 176e69d2fa0SPeter Maydell #define ICH_VMCR_EL2_VFIQEN (1U << 3) 177e69d2fa0SPeter Maydell #define ICH_VMCR_EL2_VCBPR_SHIFT 4 178e69d2fa0SPeter Maydell #define ICH_VMCR_EL2_VCBPR (1U << ICH_VMCR_EL2_VCBPR_SHIFT) 179e69d2fa0SPeter Maydell #define ICH_VMCR_EL2_VEOIM_SHIFT 9 180e69d2fa0SPeter Maydell #define ICH_VMCR_EL2_VEOIM (1U << ICH_VMCR_EL2_VEOIM_SHIFT) 181e69d2fa0SPeter Maydell #define ICH_VMCR_EL2_VBPR1_SHIFT 18 182e69d2fa0SPeter Maydell #define ICH_VMCR_EL2_VBPR1_LENGTH 3 183e69d2fa0SPeter Maydell #define ICH_VMCR_EL2_VBPR1_MASK (0x7U << ICH_VMCR_EL2_VBPR1_SHIFT) 184e69d2fa0SPeter Maydell #define ICH_VMCR_EL2_VBPR0_SHIFT 21 185e69d2fa0SPeter Maydell #define ICH_VMCR_EL2_VBPR0_LENGTH 3 186e69d2fa0SPeter Maydell #define ICH_VMCR_EL2_VBPR0_MASK (0x7U << ICH_VMCR_EL2_VBPR0_SHIFT) 187e69d2fa0SPeter Maydell #define ICH_VMCR_EL2_VPMR_SHIFT 24 188e69d2fa0SPeter Maydell #define ICH_VMCR_EL2_VPMR_LENGTH 8 189e69d2fa0SPeter Maydell #define ICH_VMCR_EL2_VPMR_MASK (0xffU << ICH_VMCR_EL2_VPMR_SHIFT) 190e69d2fa0SPeter Maydell 191e69d2fa0SPeter Maydell #define ICH_HCR_EL2_EN (1U << 0) 192e69d2fa0SPeter Maydell #define ICH_HCR_EL2_UIE (1U << 1) 193e69d2fa0SPeter Maydell #define ICH_HCR_EL2_LRENPIE (1U << 2) 194e69d2fa0SPeter Maydell #define ICH_HCR_EL2_NPIE (1U << 3) 195e69d2fa0SPeter Maydell #define ICH_HCR_EL2_VGRP0EIE (1U << 4) 196e69d2fa0SPeter Maydell #define ICH_HCR_EL2_VGRP0DIE (1U << 5) 197e69d2fa0SPeter Maydell #define ICH_HCR_EL2_VGRP1EIE (1U << 6) 198e69d2fa0SPeter Maydell #define ICH_HCR_EL2_VGRP1DIE (1U << 7) 199e69d2fa0SPeter Maydell #define ICH_HCR_EL2_TC (1U << 10) 200e69d2fa0SPeter Maydell #define ICH_HCR_EL2_TALL0 (1U << 11) 201e69d2fa0SPeter Maydell #define ICH_HCR_EL2_TALL1 (1U << 12) 202e69d2fa0SPeter Maydell #define ICH_HCR_EL2_TSEI (1U << 13) 203e69d2fa0SPeter Maydell #define ICH_HCR_EL2_TDIR (1U << 14) 204e69d2fa0SPeter Maydell #define ICH_HCR_EL2_EOICOUNT_SHIFT 27 205e69d2fa0SPeter Maydell #define ICH_HCR_EL2_EOICOUNT_LENGTH 5 206e69d2fa0SPeter Maydell #define ICH_HCR_EL2_EOICOUNT_MASK (0x1fU << ICH_HCR_EL2_EOICOUNT_SHIFT) 207e69d2fa0SPeter Maydell 208e69d2fa0SPeter Maydell #define ICH_LR_EL2_VINTID_SHIFT 0 209e69d2fa0SPeter Maydell #define ICH_LR_EL2_VINTID_LENGTH 32 210e69d2fa0SPeter Maydell #define ICH_LR_EL2_VINTID_MASK (0xffffffffULL << ICH_LR_EL2_VINTID_SHIFT) 211e69d2fa0SPeter Maydell #define ICH_LR_EL2_PINTID_SHIFT 32 212e69d2fa0SPeter Maydell #define ICH_LR_EL2_PINTID_LENGTH 10 213e69d2fa0SPeter Maydell #define ICH_LR_EL2_PINTID_MASK (0x3ffULL << ICH_LR_EL2_PINTID_SHIFT) 214e69d2fa0SPeter Maydell /* Note that EOI shares with the top bit of the pINTID field */ 215e69d2fa0SPeter Maydell #define ICH_LR_EL2_EOI (1ULL << 41) 216e69d2fa0SPeter Maydell #define ICH_LR_EL2_PRIORITY_SHIFT 48 217e69d2fa0SPeter Maydell #define ICH_LR_EL2_PRIORITY_LENGTH 8 218e69d2fa0SPeter Maydell #define ICH_LR_EL2_PRIORITY_MASK (0xffULL << ICH_LR_EL2_PRIORITY_SHIFT) 219e69d2fa0SPeter Maydell #define ICH_LR_EL2_GROUP (1ULL << 60) 220e69d2fa0SPeter Maydell #define ICH_LR_EL2_HW (1ULL << 61) 221e69d2fa0SPeter Maydell #define ICH_LR_EL2_STATE_SHIFT 62 222e69d2fa0SPeter Maydell #define ICH_LR_EL2_STATE_LENGTH 2 223e69d2fa0SPeter Maydell #define ICH_LR_EL2_STATE_MASK (3ULL << ICH_LR_EL2_STATE_SHIFT) 224e69d2fa0SPeter Maydell /* values for the state field: */ 225e69d2fa0SPeter Maydell #define ICH_LR_EL2_STATE_INVALID 0 226e69d2fa0SPeter Maydell #define ICH_LR_EL2_STATE_PENDING 1 227e69d2fa0SPeter Maydell #define ICH_LR_EL2_STATE_ACTIVE 2 228e69d2fa0SPeter Maydell #define ICH_LR_EL2_STATE_ACTIVE_PENDING 3 229e69d2fa0SPeter Maydell #define ICH_LR_EL2_STATE_PENDING_BIT (1ULL << ICH_LR_EL2_STATE_SHIFT) 230e69d2fa0SPeter Maydell #define ICH_LR_EL2_STATE_ACTIVE_BIT (2ULL << ICH_LR_EL2_STATE_SHIFT) 231e69d2fa0SPeter Maydell 232e69d2fa0SPeter Maydell #define ICH_MISR_EL2_EOI (1U << 0) 233e69d2fa0SPeter Maydell #define ICH_MISR_EL2_U (1U << 1) 234e69d2fa0SPeter Maydell #define ICH_MISR_EL2_LRENP (1U << 2) 235e69d2fa0SPeter Maydell #define ICH_MISR_EL2_NP (1U << 3) 236e69d2fa0SPeter Maydell #define ICH_MISR_EL2_VGRP0E (1U << 4) 237e69d2fa0SPeter Maydell #define ICH_MISR_EL2_VGRP0D (1U << 5) 238e69d2fa0SPeter Maydell #define ICH_MISR_EL2_VGRP1E (1U << 6) 239e69d2fa0SPeter Maydell #define ICH_MISR_EL2_VGRP1D (1U << 7) 240e69d2fa0SPeter Maydell 241e69d2fa0SPeter Maydell #define ICH_VTR_EL2_LISTREGS_SHIFT 0 242e69d2fa0SPeter Maydell #define ICH_VTR_EL2_TDS (1U << 19) 243e69d2fa0SPeter Maydell #define ICH_VTR_EL2_NV4 (1U << 20) 244e69d2fa0SPeter Maydell #define ICH_VTR_EL2_A3V (1U << 21) 245e69d2fa0SPeter Maydell #define ICH_VTR_EL2_SEIS (1U << 22) 246e69d2fa0SPeter Maydell #define ICH_VTR_EL2_IDBITS_SHIFT 23 247e69d2fa0SPeter Maydell #define ICH_VTR_EL2_PREBITS_SHIFT 26 248e69d2fa0SPeter Maydell #define ICH_VTR_EL2_PRIBITS_SHIFT 29 249e69d2fa0SPeter Maydell 25018f6290aSShashi Mallela /* ITS Registers */ 25118f6290aSShashi Mallela 25218f6290aSShashi Mallela FIELD(GITS_BASER, SIZE, 0, 8) 25318f6290aSShashi Mallela FIELD(GITS_BASER, PAGESIZE, 8, 2) 25418f6290aSShashi Mallela FIELD(GITS_BASER, SHAREABILITY, 10, 2) 25518f6290aSShashi Mallela FIELD(GITS_BASER, PHYADDR, 12, 36) 25618f6290aSShashi Mallela FIELD(GITS_BASER, PHYADDRL_64K, 16, 32) 25718f6290aSShashi Mallela FIELD(GITS_BASER, PHYADDRH_64K, 12, 4) 25818f6290aSShashi Mallela FIELD(GITS_BASER, ENTRYSIZE, 48, 5) 25918f6290aSShashi Mallela FIELD(GITS_BASER, OUTERCACHE, 53, 3) 26018f6290aSShashi Mallela FIELD(GITS_BASER, TYPE, 56, 3) 26118f6290aSShashi Mallela FIELD(GITS_BASER, INNERCACHE, 59, 3) 26218f6290aSShashi Mallela FIELD(GITS_BASER, INDIRECT, 62, 1) 26318f6290aSShashi Mallela FIELD(GITS_BASER, VALID, 63, 1) 26418f6290aSShashi Mallela 2651b08e436SShashi Mallela FIELD(GITS_CBASER, SIZE, 0, 8) 2661b08e436SShashi Mallela FIELD(GITS_CBASER, SHAREABILITY, 10, 2) 2671b08e436SShashi Mallela FIELD(GITS_CBASER, PHYADDR, 12, 40) 2681b08e436SShashi Mallela FIELD(GITS_CBASER, OUTERCACHE, 53, 3) 2691b08e436SShashi Mallela FIELD(GITS_CBASER, INNERCACHE, 59, 3) 2701b08e436SShashi Mallela FIELD(GITS_CBASER, VALID, 63, 1) 2711b08e436SShashi Mallela 2721b08e436SShashi Mallela FIELD(GITS_CREADR, STALLED, 0, 1) 2731b08e436SShashi Mallela FIELD(GITS_CREADR, OFFSET, 5, 15) 2741b08e436SShashi Mallela 2751b08e436SShashi Mallela FIELD(GITS_CWRITER, RETRY, 0, 1) 2761b08e436SShashi Mallela FIELD(GITS_CWRITER, OFFSET, 5, 15) 2771b08e436SShashi Mallela 2781b08e436SShashi Mallela FIELD(GITS_CTLR, ENABLED, 0, 1) 27918f6290aSShashi Mallela FIELD(GITS_CTLR, QUIESCENT, 31, 1) 28018f6290aSShashi Mallela 28118f6290aSShashi Mallela FIELD(GITS_TYPER, PHYSICAL, 0, 1) 28218f6290aSShashi Mallela FIELD(GITS_TYPER, ITT_ENTRY_SIZE, 4, 4) 28318f6290aSShashi Mallela FIELD(GITS_TYPER, IDBITS, 8, 5) 28418f6290aSShashi Mallela FIELD(GITS_TYPER, DEVBITS, 13, 5) 28518f6290aSShashi Mallela FIELD(GITS_TYPER, SEIS, 18, 1) 28618f6290aSShashi Mallela FIELD(GITS_TYPER, PTA, 19, 1) 28718f6290aSShashi Mallela FIELD(GITS_TYPER, CIDBITS, 32, 4) 28818f6290aSShashi Mallela FIELD(GITS_TYPER, CIL, 36, 1) 28918f6290aSShashi Mallela 2901b08e436SShashi Mallela #define GITS_IDREGS 0xFFD0 2911b08e436SShashi Mallela 2921b08e436SShashi Mallela #define GITS_BASER_RO_MASK (R_GITS_BASER_ENTRYSIZE_MASK | \ 2931b08e436SShashi Mallela R_GITS_BASER_TYPE_MASK) 2941b08e436SShashi Mallela 29518f6290aSShashi Mallela #define GITS_BASER_PAGESIZE_4K 0 29618f6290aSShashi Mallela #define GITS_BASER_PAGESIZE_16K 1 29718f6290aSShashi Mallela #define GITS_BASER_PAGESIZE_64K 2 29818f6290aSShashi Mallela 29918f6290aSShashi Mallela #define GITS_BASER_TYPE_DEVICE 1ULL 30018f6290aSShashi Mallela #define GITS_BASER_TYPE_COLLECTION 4ULL 30118f6290aSShashi Mallela 3021b08e436SShashi Mallela #define GITS_PAGE_SIZE_4K 0x1000 3031b08e436SShashi Mallela #define GITS_PAGE_SIZE_16K 0x4000 3041b08e436SShashi Mallela #define GITS_PAGE_SIZE_64K 0x10000 3051b08e436SShashi Mallela 3061b08e436SShashi Mallela #define L1TABLE_ENTRY_SIZE 8 3071b08e436SShashi Mallela 30817fb5e36SShashi Mallela #define LPI_CTE_ENABLED TABLE_ENTRY_VALID_MASK 30917fb5e36SShashi Mallela #define LPI_PRIORITY_MASK 0xfc 31017fb5e36SShashi Mallela 3111b08e436SShashi Mallela #define GITS_CMDQ_ENTRY_SIZE 32 3127eca39e0SShashi Mallela #define NUM_BYTES_IN_DW 8 3137eca39e0SShashi Mallela 3147eca39e0SShashi Mallela #define CMD_MASK 0xff 3157eca39e0SShashi Mallela 3167eca39e0SShashi Mallela /* ITS Commands */ 3177eca39e0SShashi Mallela #define GITS_CMD_CLEAR 0x04 3187eca39e0SShashi Mallela #define GITS_CMD_DISCARD 0x0F 3197eca39e0SShashi Mallela #define GITS_CMD_INT 0x03 3207eca39e0SShashi Mallela #define GITS_CMD_MAPC 0x09 3217eca39e0SShashi Mallela #define GITS_CMD_MAPD 0x08 3227eca39e0SShashi Mallela #define GITS_CMD_MAPI 0x0B 3237eca39e0SShashi Mallela #define GITS_CMD_MAPTI 0x0A 3247eca39e0SShashi Mallela #define GITS_CMD_INV 0x0C 3257eca39e0SShashi Mallela #define GITS_CMD_INVALL 0x0D 3267eca39e0SShashi Mallela #define GITS_CMD_SYNC 0x05 3277eca39e0SShashi Mallela 3287eca39e0SShashi Mallela /* MAPC command fields */ 3297eca39e0SShashi Mallela #define ICID_LENGTH 16 3307eca39e0SShashi Mallela #define ICID_MASK ((1U << ICID_LENGTH) - 1) 3317eca39e0SShashi Mallela FIELD(MAPC, RDBASE, 16, 32) 3327eca39e0SShashi Mallela 3337eca39e0SShashi Mallela #define RDBASE_PROCNUM_LENGTH 16 3347eca39e0SShashi Mallela #define RDBASE_PROCNUM_MASK ((1ULL << RDBASE_PROCNUM_LENGTH) - 1) 3357eca39e0SShashi Mallela 3367eca39e0SShashi Mallela /* MAPD command fields */ 3377eca39e0SShashi Mallela #define ITTADDR_LENGTH 44 3387eca39e0SShashi Mallela #define ITTADDR_SHIFT 8 3397eca39e0SShashi Mallela #define ITTADDR_MASK MAKE_64BIT_MASK(ITTADDR_SHIFT, ITTADDR_LENGTH) 3407eca39e0SShashi Mallela #define SIZE_MASK 0x1f 3417eca39e0SShashi Mallela 342c694cb4cSShashi Mallela /* MAPI command fields */ 343c694cb4cSShashi Mallela #define EVENTID_MASK ((1ULL << 32) - 1) 344c694cb4cSShashi Mallela 345c694cb4cSShashi Mallela /* MAPTI command fields */ 346c694cb4cSShashi Mallela #define pINTID_SHIFT 32 347c694cb4cSShashi Mallela #define pINTID_MASK MAKE_64BIT_MASK(32, 32) 348c694cb4cSShashi Mallela 3497eca39e0SShashi Mallela #define DEVID_SHIFT 32 3507eca39e0SShashi Mallela #define DEVID_MASK MAKE_64BIT_MASK(32, 32) 3517eca39e0SShashi Mallela 3527eca39e0SShashi Mallela #define VALID_SHIFT 63 3537eca39e0SShashi Mallela #define CMD_FIELD_VALID_MASK (1ULL << VALID_SHIFT) 3547eca39e0SShashi Mallela #define L2_TABLE_VALID_MASK CMD_FIELD_VALID_MASK 3557eca39e0SShashi Mallela #define TABLE_ENTRY_VALID_MASK (1ULL << 0) 3561b08e436SShashi Mallela 35718f6290aSShashi Mallela /* 35818f6290aSShashi Mallela * 12 bytes Interrupt translation Table Entry size 35918f6290aSShashi Mallela * as per Table 5.3 in GICv3 spec 36018f6290aSShashi Mallela * ITE Lower 8 Bytes 36118f6290aSShashi Mallela * Bits: | 49 ... 26 | 25 ... 2 | 1 | 0 | 362*764d6ba1SPeter Maydell * Values: | Doorbell | IntNum | IntType | Valid | 36318f6290aSShashi Mallela * ITE Higher 4 Bytes 36418f6290aSShashi Mallela * Bits: | 31 ... 16 | 15 ...0 | 36518f6290aSShashi Mallela * Values: | vPEID | ICID | 366*764d6ba1SPeter Maydell * (When Doorbell is unused, as it always is in GICv3, it is 1023) 36718f6290aSShashi Mallela */ 36818f6290aSShashi Mallela #define ITS_ITT_ENTRY_SIZE 0xC 369*764d6ba1SPeter Maydell 370*764d6ba1SPeter Maydell FIELD(ITE_L, VALID, 0, 1) 371*764d6ba1SPeter Maydell FIELD(ITE_L, INTTYPE, 1, 1) 372*764d6ba1SPeter Maydell FIELD(ITE_L, INTID, 2, 24) 373*764d6ba1SPeter Maydell FIELD(ITE_L, DOORBELL, 26, 24) 374*764d6ba1SPeter Maydell 375*764d6ba1SPeter Maydell FIELD(ITE_H, ICID, 0, 16) 376*764d6ba1SPeter Maydell FIELD(ITE_H, VPEID, 16, 16) 377*764d6ba1SPeter Maydell 378*764d6ba1SPeter Maydell /* Possible values for ITE_L INTTYPE */ 379*764d6ba1SPeter Maydell #define ITE_INTTYPE_VIRTUAL 0 380*764d6ba1SPeter Maydell #define ITE_INTTYPE_PHYSICAL 1 38118f6290aSShashi Mallela 38218f6290aSShashi Mallela /* 16 bits EventId */ 38318f6290aSShashi Mallela #define ITS_IDBITS GICD_TYPER_IDBITS 38418f6290aSShashi Mallela 38518f6290aSShashi Mallela /* 16 bits DeviceId */ 38618f6290aSShashi Mallela #define ITS_DEVBITS 0xF 38718f6290aSShashi Mallela 38818f6290aSShashi Mallela /* 16 bits CollectionId */ 38918f6290aSShashi Mallela #define ITS_CIDBITS 0xF 39018f6290aSShashi Mallela 39118f6290aSShashi Mallela /* 39218f6290aSShashi Mallela * 8 bytes Device Table Entry size 39318f6290aSShashi Mallela * Valid = 1 bit,ITTAddr = 44 bits,Size = 5 bits 39418f6290aSShashi Mallela */ 39518f6290aSShashi Mallela #define GITS_DTE_SIZE (0x8ULL) 3967eca39e0SShashi Mallela #define GITS_DTE_ITTADDR_SHIFT 6 3977eca39e0SShashi Mallela #define GITS_DTE_ITTADDR_MASK MAKE_64BIT_MASK(GITS_DTE_ITTADDR_SHIFT, \ 3987eca39e0SShashi Mallela ITTADDR_LENGTH) 39918f6290aSShashi Mallela 40018f6290aSShashi Mallela /* 40118f6290aSShashi Mallela * 8 bytes Collection Table Entry size 40218f6290aSShashi Mallela * Valid = 1 bit,RDBase = 36 bits(considering max RDBASE) 40318f6290aSShashi Mallela */ 40418f6290aSShashi Mallela #define GITS_CTE_SIZE (0x8ULL) 40517fb5e36SShashi Mallela #define GITS_CTE_RDBASE_PROCNUM_MASK MAKE_64BIT_MASK(1, RDBASE_PROCNUM_LENGTH) 40618f6290aSShashi Mallela 407227a8653SPeter Maydell /* Special interrupt IDs */ 408227a8653SPeter Maydell #define INTID_SECURE 1020 409227a8653SPeter Maydell #define INTID_NONSECURE 1021 410227a8653SPeter Maydell #define INTID_SPURIOUS 1023 411227a8653SPeter Maydell 412ce187c3cSPeter Maydell /* Functions internal to the emulated GICv3 */ 413ce187c3cSPeter Maydell 414ce187c3cSPeter Maydell /** 415b74d7c0eSPeter Maydell * gicv3_intid_is_special: 416b74d7c0eSPeter Maydell * @intid: interrupt ID 417b74d7c0eSPeter Maydell * 418b74d7c0eSPeter Maydell * Return true if @intid is a special interrupt ID (1020 to 419b74d7c0eSPeter Maydell * 1023 inclusive). This corresponds to the GIC spec pseudocode 420b74d7c0eSPeter Maydell * IsSpecial() function. 421b74d7c0eSPeter Maydell */ 422b74d7c0eSPeter Maydell static inline bool gicv3_intid_is_special(int intid) 423b74d7c0eSPeter Maydell { 424b74d7c0eSPeter Maydell return intid >= INTID_SECURE && intid <= INTID_SPURIOUS; 425b74d7c0eSPeter Maydell } 426b74d7c0eSPeter Maydell 427b74d7c0eSPeter Maydell /** 428ce187c3cSPeter Maydell * gicv3_redist_update: 429ce187c3cSPeter Maydell * @cs: GICv3CPUState for this redistributor 430ce187c3cSPeter Maydell * 431ce187c3cSPeter Maydell * Recalculate the highest priority pending interrupt after a 432ce187c3cSPeter Maydell * change to redistributor state, and inform the CPU accordingly. 433ce187c3cSPeter Maydell */ 434ce187c3cSPeter Maydell void gicv3_redist_update(GICv3CPUState *cs); 435ce187c3cSPeter Maydell 436ce187c3cSPeter Maydell /** 437ce187c3cSPeter Maydell * gicv3_update: 438ce187c3cSPeter Maydell * @s: GICv3State 439ce187c3cSPeter Maydell * @start: first interrupt whose state changed 440ce187c3cSPeter Maydell * @len: length of the range of interrupts whose state changed 441ce187c3cSPeter Maydell * 442ce187c3cSPeter Maydell * Recalculate the highest priority pending interrupts after a 443ce187c3cSPeter Maydell * change to the distributor state affecting @len interrupts 444ce187c3cSPeter Maydell * starting at @start, and inform the CPUs accordingly. 445ce187c3cSPeter Maydell */ 446ce187c3cSPeter Maydell void gicv3_update(GICv3State *s, int start, int len); 447ce187c3cSPeter Maydell 448ce187c3cSPeter Maydell /** 449ce187c3cSPeter Maydell * gicv3_full_update_noirqset: 450ce187c3cSPeter Maydell * @s: GICv3State 451ce187c3cSPeter Maydell * 452ce187c3cSPeter Maydell * Recalculate the cached information about highest priority 453ce187c3cSPeter Maydell * pending interrupts, but don't inform the CPUs. This should be 454ce187c3cSPeter Maydell * called after an incoming migration has loaded new state. 455ce187c3cSPeter Maydell */ 456ce187c3cSPeter Maydell void gicv3_full_update_noirqset(GICv3State *s); 457ce187c3cSPeter Maydell 458ce187c3cSPeter Maydell /** 459ce187c3cSPeter Maydell * gicv3_full_update: 460ce187c3cSPeter Maydell * @s: GICv3State 461ce187c3cSPeter Maydell * 462ce187c3cSPeter Maydell * Recalculate the highest priority pending interrupts after 463ce187c3cSPeter Maydell * a change that could affect the status of all interrupts, 464ce187c3cSPeter Maydell * and inform the CPUs accordingly. 465ce187c3cSPeter Maydell */ 466ce187c3cSPeter Maydell void gicv3_full_update(GICv3State *s); 467e52af513SShlomo Pongratz MemTxResult gicv3_dist_read(void *opaque, hwaddr offset, uint64_t *data, 468e52af513SShlomo Pongratz unsigned size, MemTxAttrs attrs); 469e52af513SShlomo Pongratz MemTxResult gicv3_dist_write(void *opaque, hwaddr addr, uint64_t data, 470e52af513SShlomo Pongratz unsigned size, MemTxAttrs attrs); 471cec93a93SShlomo Pongratz MemTxResult gicv3_redist_read(void *opaque, hwaddr offset, uint64_t *data, 472cec93a93SShlomo Pongratz unsigned size, MemTxAttrs attrs); 473cec93a93SShlomo Pongratz MemTxResult gicv3_redist_write(void *opaque, hwaddr offset, uint64_t data, 474cec93a93SShlomo Pongratz unsigned size, MemTxAttrs attrs); 475c84428b3SPeter Maydell void gicv3_dist_set_irq(GICv3State *s, int irq, int level); 476c84428b3SPeter Maydell void gicv3_redist_set_irq(GICv3CPUState *cs, int irq, int level); 47717fb5e36SShashi Mallela void gicv3_redist_process_lpi(GICv3CPUState *cs, int irq, int level); 47817fb5e36SShashi Mallela void gicv3_redist_lpi_pending(GICv3CPUState *cs, int irq, int level); 479101f27f3SPeter Maydell /** 480101f27f3SPeter Maydell * gicv3_redist_update_lpi: 481101f27f3SPeter Maydell * @cs: GICv3CPUState 482101f27f3SPeter Maydell * 483101f27f3SPeter Maydell * Scan the LPI pending table and recalculate the highest priority 484101f27f3SPeter Maydell * pending LPI and also the overall highest priority pending interrupt. 485101f27f3SPeter Maydell */ 48617fb5e36SShashi Mallela void gicv3_redist_update_lpi(GICv3CPUState *cs); 487101f27f3SPeter Maydell /** 488101f27f3SPeter Maydell * gicv3_redist_update_lpi_only: 489101f27f3SPeter Maydell * @cs: GICv3CPUState 490101f27f3SPeter Maydell * 491101f27f3SPeter Maydell * Scan the LPI pending table and recalculate cs->hpplpi only, 492101f27f3SPeter Maydell * without calling gicv3_redist_update() to recalculate the overall 493101f27f3SPeter Maydell * highest priority pending interrupt. This should be called after 494101f27f3SPeter Maydell * an incoming migration has loaded new state. 495101f27f3SPeter Maydell */ 496101f27f3SPeter Maydell void gicv3_redist_update_lpi_only(GICv3CPUState *cs); 497b1a0eb77SPeter Maydell void gicv3_redist_send_sgi(GICv3CPUState *cs, int grp, int irq, bool ns); 498359fbe65SPeter Maydell void gicv3_init_cpuif(GICv3State *s); 499ce187c3cSPeter Maydell 500ce187c3cSPeter Maydell /** 501ce187c3cSPeter Maydell * gicv3_cpuif_update: 502ce187c3cSPeter Maydell * @cs: GICv3CPUState for the CPU to update 503ce187c3cSPeter Maydell * 504ce187c3cSPeter Maydell * Recalculate whether to assert the IRQ or FIQ lines after a change 505ce187c3cSPeter Maydell * to the current highest priority pending interrupt, the CPU's 506ce187c3cSPeter Maydell * current running priority or the CPU's current exception level or 507ce187c3cSPeter Maydell * security state. 508ce187c3cSPeter Maydell */ 509f7b9358eSPeter Maydell void gicv3_cpuif_update(GICv3CPUState *cs); 510ce187c3cSPeter Maydell 51156992670SShlomo Pongratz static inline uint32_t gicv3_iidr(void) 51256992670SShlomo Pongratz { 51356992670SShlomo Pongratz /* Return the Implementer Identification Register value 51456992670SShlomo Pongratz * for the emulated GICv3, as reported in GICD_IIDR and GICR_IIDR. 51556992670SShlomo Pongratz * 51656992670SShlomo Pongratz * We claim to be an ARM r0p0 with a zero ProductID. 51756992670SShlomo Pongratz * This is the same as an r0p0 GIC-500. 51856992670SShlomo Pongratz */ 51956992670SShlomo Pongratz return 0x43b; 52056992670SShlomo Pongratz } 52156992670SShlomo Pongratz 52256992670SShlomo Pongratz static inline uint32_t gicv3_idreg(int regoffset) 52356992670SShlomo Pongratz { 52456992670SShlomo Pongratz /* Return the value of the CoreSight ID register at the specified 52556992670SShlomo Pongratz * offset from the first ID register (as found in the distributor 52656992670SShlomo Pongratz * and redistributor register banks). 52756992670SShlomo Pongratz * These values indicate an ARM implementation of a GICv3. 52856992670SShlomo Pongratz */ 52956992670SShlomo Pongratz static const uint8_t gicd_ids[] = { 53056992670SShlomo Pongratz 0x44, 0x00, 0x00, 0x00, 0x92, 0xB4, 0x3B, 0x00, 0x0D, 0xF0, 0x05, 0xB1 53156992670SShlomo Pongratz }; 53256992670SShlomo Pongratz return gicd_ids[regoffset / 4]; 53356992670SShlomo Pongratz } 53456992670SShlomo Pongratz 53507e2034dSPavel Fedin /** 536ce187c3cSPeter Maydell * gicv3_irq_group: 537ce187c3cSPeter Maydell * 538ce187c3cSPeter Maydell * Return the group which this interrupt is configured as (GICV3_G0, 539ce187c3cSPeter Maydell * GICV3_G1 or GICV3_G1NS). 540ce187c3cSPeter Maydell */ 541ce187c3cSPeter Maydell static inline int gicv3_irq_group(GICv3State *s, GICv3CPUState *cs, int irq) 542ce187c3cSPeter Maydell { 543ce187c3cSPeter Maydell bool grpbit, grpmodbit; 544ce187c3cSPeter Maydell 545ce187c3cSPeter Maydell if (irq < GIC_INTERNAL) { 546ce187c3cSPeter Maydell grpbit = extract32(cs->gicr_igroupr0, irq, 1); 547ce187c3cSPeter Maydell grpmodbit = extract32(cs->gicr_igrpmodr0, irq, 1); 548ce187c3cSPeter Maydell } else { 549ce187c3cSPeter Maydell grpbit = gicv3_gicd_group_test(s, irq); 550ce187c3cSPeter Maydell grpmodbit = gicv3_gicd_grpmod_test(s, irq); 551ce187c3cSPeter Maydell } 552ce187c3cSPeter Maydell if (grpbit) { 553ce187c3cSPeter Maydell return GICV3_G1NS; 554ce187c3cSPeter Maydell } 555ce187c3cSPeter Maydell if (s->gicd_ctlr & GICD_CTLR_DS) { 556ce187c3cSPeter Maydell return GICV3_G0; 557ce187c3cSPeter Maydell } 558ce187c3cSPeter Maydell return grpmodbit ? GICV3_G1 : GICV3_G0; 559ce187c3cSPeter Maydell } 560ce187c3cSPeter Maydell 561ce187c3cSPeter Maydell /** 56207e2034dSPavel Fedin * gicv3_redist_affid: 56307e2034dSPavel Fedin * 56407e2034dSPavel Fedin * Return the 32-bit affinity ID of the CPU connected to this redistributor 56507e2034dSPavel Fedin */ 56607e2034dSPavel Fedin static inline uint32_t gicv3_redist_affid(GICv3CPUState *cs) 56707e2034dSPavel Fedin { 56807e2034dSPavel Fedin return cs->gicr_typer >> 32; 56907e2034dSPavel Fedin } 57007e2034dSPavel Fedin 571ce187c3cSPeter Maydell /** 572ce187c3cSPeter Maydell * gicv3_cache_target_cpustate: 573ce187c3cSPeter Maydell * 574ce187c3cSPeter Maydell * Update the cached CPU state corresponding to the target for this interrupt 575ce187c3cSPeter Maydell * (which is kept in s->gicd_irouter_target[]). 576ce187c3cSPeter Maydell */ 577ce187c3cSPeter Maydell static inline void gicv3_cache_target_cpustate(GICv3State *s, int irq) 578ce187c3cSPeter Maydell { 579ce187c3cSPeter Maydell GICv3CPUState *cs = NULL; 580ce187c3cSPeter Maydell int i; 581ce187c3cSPeter Maydell uint32_t tgtaff = extract64(s->gicd_irouter[irq], 0, 24) | 582ce187c3cSPeter Maydell extract64(s->gicd_irouter[irq], 32, 8) << 24; 583ce187c3cSPeter Maydell 584ce187c3cSPeter Maydell for (i = 0; i < s->num_cpu; i++) { 585ce187c3cSPeter Maydell if (s->cpu[i].gicr_typer >> 32 == tgtaff) { 586ce187c3cSPeter Maydell cs = &s->cpu[i]; 587ce187c3cSPeter Maydell break; 588ce187c3cSPeter Maydell } 589ce187c3cSPeter Maydell } 590ce187c3cSPeter Maydell 591ce187c3cSPeter Maydell s->gicd_irouter_target[irq] = cs; 592ce187c3cSPeter Maydell } 593ce187c3cSPeter Maydell 594ce187c3cSPeter Maydell /** 595ce187c3cSPeter Maydell * gicv3_cache_all_target_cpustates: 596ce187c3cSPeter Maydell * 597ce187c3cSPeter Maydell * Populate the entire cache of CPU state pointers for interrupt targets 598ce187c3cSPeter Maydell * (eg after inbound migration or CPU reset) 599ce187c3cSPeter Maydell */ 600ce187c3cSPeter Maydell static inline void gicv3_cache_all_target_cpustates(GICv3State *s) 601ce187c3cSPeter Maydell { 602ce187c3cSPeter Maydell int irq; 603ce187c3cSPeter Maydell 604ce187c3cSPeter Maydell for (irq = GIC_INTERNAL; irq < GICV3_MAXIRQ; irq++) { 605ce187c3cSPeter Maydell gicv3_cache_target_cpustate(s, irq); 606ce187c3cSPeter Maydell } 607ce187c3cSPeter Maydell } 608ce187c3cSPeter Maydell 609d3a3e529SVijaya Kumar K void gicv3_set_gicv3state(CPUState *cpu, GICv3CPUState *s); 610d3a3e529SVijaya Kumar K 611175de524SMarkus Armbruster #endif /* QEMU_ARM_GICV3_INTERNAL_H */ 612