1 /* 2 * ARM Generic Interrupt Controller using KVM in-kernel support 3 * 4 * Copyright (c) 2015 Samsung Electronics Co., Ltd. 5 * Written by Pavel Fedin 6 * Based on vGICv2 code by Peter Maydell 7 * 8 * This program is free software; you can redistribute it and/or modify 9 * it under the terms of the GNU General Public License as published by 10 * the Free Software Foundation, either version 2 of the License, or 11 * (at your option) any later version. 12 * 13 * This program is distributed in the hope that it will be useful, 14 * but WITHOUT ANY WARRANTY; without even the implied warranty of 15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 16 * GNU General Public License for more details. 17 * 18 * You should have received a copy of the GNU General Public License along 19 * with this program; if not, see <http://www.gnu.org/licenses/>. 20 */ 21 22 #include "qemu/osdep.h" 23 #include "qapi/error.h" 24 #include "hw/intc/arm_gicv3_common.h" 25 #include "hw/sysbus.h" 26 #include "qemu/error-report.h" 27 #include "sysemu/kvm.h" 28 #include "sysemu/sysemu.h" 29 #include "kvm_arm.h" 30 #include "gicv3_internal.h" 31 #include "vgic_common.h" 32 #include "migration/blocker.h" 33 34 #ifdef DEBUG_GICV3_KVM 35 #define DPRINTF(fmt, ...) \ 36 do { fprintf(stderr, "kvm_gicv3: " fmt, ## __VA_ARGS__); } while (0) 37 #else 38 #define DPRINTF(fmt, ...) \ 39 do { } while (0) 40 #endif 41 42 #define TYPE_KVM_ARM_GICV3 "kvm-arm-gicv3" 43 #define KVM_ARM_GICV3(obj) \ 44 OBJECT_CHECK(GICv3State, (obj), TYPE_KVM_ARM_GICV3) 45 #define KVM_ARM_GICV3_CLASS(klass) \ 46 OBJECT_CLASS_CHECK(KVMARMGICv3Class, (klass), TYPE_KVM_ARM_GICV3) 47 #define KVM_ARM_GICV3_GET_CLASS(obj) \ 48 OBJECT_GET_CLASS(KVMARMGICv3Class, (obj), TYPE_KVM_ARM_GICV3) 49 50 #define KVM_DEV_ARM_VGIC_SYSREG(op0, op1, crn, crm, op2) \ 51 (ARM64_SYS_REG_SHIFT_MASK(op0, OP0) | \ 52 ARM64_SYS_REG_SHIFT_MASK(op1, OP1) | \ 53 ARM64_SYS_REG_SHIFT_MASK(crn, CRN) | \ 54 ARM64_SYS_REG_SHIFT_MASK(crm, CRM) | \ 55 ARM64_SYS_REG_SHIFT_MASK(op2, OP2)) 56 57 #define ICC_PMR_EL1 \ 58 KVM_DEV_ARM_VGIC_SYSREG(3, 0, 4, 6, 0) 59 #define ICC_BPR0_EL1 \ 60 KVM_DEV_ARM_VGIC_SYSREG(3, 0, 12, 8, 3) 61 #define ICC_AP0R_EL1(n) \ 62 KVM_DEV_ARM_VGIC_SYSREG(3, 0, 12, 8, 4 | n) 63 #define ICC_AP1R_EL1(n) \ 64 KVM_DEV_ARM_VGIC_SYSREG(3, 0, 12, 9, n) 65 #define ICC_BPR1_EL1 \ 66 KVM_DEV_ARM_VGIC_SYSREG(3, 0, 12, 12, 3) 67 #define ICC_CTLR_EL1 \ 68 KVM_DEV_ARM_VGIC_SYSREG(3, 0, 12, 12, 4) 69 #define ICC_SRE_EL1 \ 70 KVM_DEV_ARM_VGIC_SYSREG(3, 0, 12, 12, 5) 71 #define ICC_IGRPEN0_EL1 \ 72 KVM_DEV_ARM_VGIC_SYSREG(3, 0, 12, 12, 6) 73 #define ICC_IGRPEN1_EL1 \ 74 KVM_DEV_ARM_VGIC_SYSREG(3, 0, 12, 12, 7) 75 76 typedef struct KVMARMGICv3Class { 77 ARMGICv3CommonClass parent_class; 78 DeviceRealize parent_realize; 79 void (*parent_reset)(DeviceState *dev); 80 } KVMARMGICv3Class; 81 82 static void kvm_arm_gicv3_set_irq(void *opaque, int irq, int level) 83 { 84 GICv3State *s = (GICv3State *)opaque; 85 86 kvm_arm_gic_set_irq(s->num_irq, irq, level); 87 } 88 89 #define KVM_VGIC_ATTR(reg, typer) \ 90 ((typer & KVM_DEV_ARM_VGIC_V3_MPIDR_MASK) | (reg)) 91 92 static inline void kvm_gicd_access(GICv3State *s, int offset, 93 uint32_t *val, bool write) 94 { 95 kvm_device_access(s->dev_fd, KVM_DEV_ARM_VGIC_GRP_DIST_REGS, 96 KVM_VGIC_ATTR(offset, 0), 97 val, write, &error_abort); 98 } 99 100 static inline void kvm_gicr_access(GICv3State *s, int offset, int cpu, 101 uint32_t *val, bool write) 102 { 103 kvm_device_access(s->dev_fd, KVM_DEV_ARM_VGIC_GRP_REDIST_REGS, 104 KVM_VGIC_ATTR(offset, s->cpu[cpu].gicr_typer), 105 val, write, &error_abort); 106 } 107 108 static inline void kvm_gicc_access(GICv3State *s, uint64_t reg, int cpu, 109 uint64_t *val, bool write) 110 { 111 kvm_device_access(s->dev_fd, KVM_DEV_ARM_VGIC_GRP_CPU_SYSREGS, 112 KVM_VGIC_ATTR(reg, s->cpu[cpu].gicr_typer), 113 val, write, &error_abort); 114 } 115 116 static inline void kvm_gic_line_level_access(GICv3State *s, int irq, int cpu, 117 uint32_t *val, bool write) 118 { 119 kvm_device_access(s->dev_fd, KVM_DEV_ARM_VGIC_GRP_LEVEL_INFO, 120 KVM_VGIC_ATTR(irq, s->cpu[cpu].gicr_typer) | 121 (VGIC_LEVEL_INFO_LINE_LEVEL << 122 KVM_DEV_ARM_VGIC_LINE_LEVEL_INFO_SHIFT), 123 val, write, &error_abort); 124 } 125 126 /* Loop through each distributor IRQ related register; since bits 127 * corresponding to SPIs and PPIs are RAZ/WI when affinity routing 128 * is enabled, we skip those. 129 */ 130 #define for_each_dist_irq_reg(_irq, _max, _field_width) \ 131 for (_irq = GIC_INTERNAL; _irq < _max; _irq += (32 / _field_width)) 132 133 static void kvm_dist_get_priority(GICv3State *s, uint32_t offset, uint8_t *bmp) 134 { 135 uint32_t reg, *field; 136 int irq; 137 138 field = (uint32_t *)bmp; 139 for_each_dist_irq_reg(irq, s->num_irq, 8) { 140 kvm_gicd_access(s, offset, ®, false); 141 *field = reg; 142 offset += 4; 143 field++; 144 } 145 } 146 147 static void kvm_dist_put_priority(GICv3State *s, uint32_t offset, uint8_t *bmp) 148 { 149 uint32_t reg, *field; 150 int irq; 151 152 field = (uint32_t *)bmp; 153 for_each_dist_irq_reg(irq, s->num_irq, 8) { 154 reg = *field; 155 kvm_gicd_access(s, offset, ®, true); 156 offset += 4; 157 field++; 158 } 159 } 160 161 static void kvm_dist_get_edge_trigger(GICv3State *s, uint32_t offset, 162 uint32_t *bmp) 163 { 164 uint32_t reg; 165 int irq; 166 167 for_each_dist_irq_reg(irq, s->num_irq, 2) { 168 kvm_gicd_access(s, offset, ®, false); 169 reg = half_unshuffle32(reg >> 1); 170 if (irq % 32 != 0) { 171 reg = (reg << 16); 172 } 173 *gic_bmp_ptr32(bmp, irq) |= reg; 174 offset += 4; 175 } 176 } 177 178 static void kvm_dist_put_edge_trigger(GICv3State *s, uint32_t offset, 179 uint32_t *bmp) 180 { 181 uint32_t reg; 182 int irq; 183 184 for_each_dist_irq_reg(irq, s->num_irq, 2) { 185 reg = *gic_bmp_ptr32(bmp, irq); 186 if (irq % 32 != 0) { 187 reg = (reg & 0xffff0000) >> 16; 188 } else { 189 reg = reg & 0xffff; 190 } 191 reg = half_shuffle32(reg) << 1; 192 kvm_gicd_access(s, offset, ®, true); 193 offset += 4; 194 } 195 } 196 197 static void kvm_gic_get_line_level_bmp(GICv3State *s, uint32_t *bmp) 198 { 199 uint32_t reg; 200 int irq; 201 202 for_each_dist_irq_reg(irq, s->num_irq, 1) { 203 kvm_gic_line_level_access(s, irq, 0, ®, false); 204 *gic_bmp_ptr32(bmp, irq) = reg; 205 } 206 } 207 208 static void kvm_gic_put_line_level_bmp(GICv3State *s, uint32_t *bmp) 209 { 210 uint32_t reg; 211 int irq; 212 213 for_each_dist_irq_reg(irq, s->num_irq, 1) { 214 reg = *gic_bmp_ptr32(bmp, irq); 215 kvm_gic_line_level_access(s, irq, 0, ®, true); 216 } 217 } 218 219 /* Read a bitmap register group from the kernel VGIC. */ 220 static void kvm_dist_getbmp(GICv3State *s, uint32_t offset, uint32_t *bmp) 221 { 222 uint32_t reg; 223 int irq; 224 225 for_each_dist_irq_reg(irq, s->num_irq, 1) { 226 kvm_gicd_access(s, offset, ®, false); 227 *gic_bmp_ptr32(bmp, irq) = reg; 228 offset += 4; 229 } 230 } 231 232 static void kvm_dist_putbmp(GICv3State *s, uint32_t offset, 233 uint32_t clroffset, uint32_t *bmp) 234 { 235 uint32_t reg; 236 int irq; 237 238 for_each_dist_irq_reg(irq, s->num_irq, 1) { 239 /* If this bitmap is a set/clear register pair, first write to the 240 * clear-reg to clear all bits before using the set-reg to write 241 * the 1 bits. 242 */ 243 if (clroffset != 0) { 244 reg = 0; 245 kvm_gicd_access(s, clroffset, ®, true); 246 clroffset += 4; 247 } 248 reg = *gic_bmp_ptr32(bmp, irq); 249 kvm_gicd_access(s, offset, ®, true); 250 offset += 4; 251 } 252 } 253 254 static void kvm_arm_gicv3_check(GICv3State *s) 255 { 256 uint32_t reg; 257 uint32_t num_irq; 258 259 /* Sanity checking s->num_irq */ 260 kvm_gicd_access(s, GICD_TYPER, ®, false); 261 num_irq = ((reg & 0x1f) + 1) * 32; 262 263 if (num_irq < s->num_irq) { 264 error_report("Model requests %u IRQs, but kernel supports max %u", 265 s->num_irq, num_irq); 266 abort(); 267 } 268 } 269 270 static void kvm_arm_gicv3_put(GICv3State *s) 271 { 272 uint32_t regl, regh, reg; 273 uint64_t reg64, redist_typer; 274 int ncpu, i; 275 276 kvm_arm_gicv3_check(s); 277 278 kvm_gicr_access(s, GICR_TYPER, 0, ®l, false); 279 kvm_gicr_access(s, GICR_TYPER + 4, 0, ®h, false); 280 redist_typer = ((uint64_t)regh << 32) | regl; 281 282 reg = s->gicd_ctlr; 283 kvm_gicd_access(s, GICD_CTLR, ®, true); 284 285 if (redist_typer & GICR_TYPER_PLPIS) { 286 /* Set base addresses before LPIs are enabled by GICR_CTLR write */ 287 for (ncpu = 0; ncpu < s->num_cpu; ncpu++) { 288 GICv3CPUState *c = &s->cpu[ncpu]; 289 290 reg64 = c->gicr_propbaser; 291 regl = (uint32_t)reg64; 292 kvm_gicr_access(s, GICR_PROPBASER, ncpu, ®l, true); 293 regh = (uint32_t)(reg64 >> 32); 294 kvm_gicr_access(s, GICR_PROPBASER + 4, ncpu, ®h, true); 295 296 reg64 = c->gicr_pendbaser; 297 if (!(c->gicr_ctlr & GICR_CTLR_ENABLE_LPIS)) { 298 /* Setting PTZ is advised if LPIs are disabled, to reduce 299 * GIC initialization time. 300 */ 301 reg64 |= GICR_PENDBASER_PTZ; 302 } 303 regl = (uint32_t)reg64; 304 kvm_gicr_access(s, GICR_PENDBASER, ncpu, ®l, true); 305 regh = (uint32_t)(reg64 >> 32); 306 kvm_gicr_access(s, GICR_PENDBASER + 4, ncpu, ®h, true); 307 } 308 } 309 310 /* Redistributor state (one per CPU) */ 311 312 for (ncpu = 0; ncpu < s->num_cpu; ncpu++) { 313 GICv3CPUState *c = &s->cpu[ncpu]; 314 315 reg = c->gicr_ctlr; 316 kvm_gicr_access(s, GICR_CTLR, ncpu, ®, true); 317 318 reg = c->gicr_statusr[GICV3_NS]; 319 kvm_gicr_access(s, GICR_STATUSR, ncpu, ®, true); 320 321 reg = c->gicr_waker; 322 kvm_gicr_access(s, GICR_WAKER, ncpu, ®, true); 323 324 reg = c->gicr_igroupr0; 325 kvm_gicr_access(s, GICR_IGROUPR0, ncpu, ®, true); 326 327 reg = ~0; 328 kvm_gicr_access(s, GICR_ICENABLER0, ncpu, ®, true); 329 reg = c->gicr_ienabler0; 330 kvm_gicr_access(s, GICR_ISENABLER0, ncpu, ®, true); 331 332 /* Restore config before pending so we treat level/edge correctly */ 333 reg = half_shuffle32(c->edge_trigger >> 16) << 1; 334 kvm_gicr_access(s, GICR_ICFGR1, ncpu, ®, true); 335 336 reg = c->level; 337 kvm_gic_line_level_access(s, 0, ncpu, ®, true); 338 339 reg = ~0; 340 kvm_gicr_access(s, GICR_ICPENDR0, ncpu, ®, true); 341 reg = c->gicr_ipendr0; 342 kvm_gicr_access(s, GICR_ISPENDR0, ncpu, ®, true); 343 344 reg = ~0; 345 kvm_gicr_access(s, GICR_ICACTIVER0, ncpu, ®, true); 346 reg = c->gicr_iactiver0; 347 kvm_gicr_access(s, GICR_ISACTIVER0, ncpu, ®, true); 348 349 for (i = 0; i < GIC_INTERNAL; i += 4) { 350 reg = c->gicr_ipriorityr[i] | 351 (c->gicr_ipriorityr[i + 1] << 8) | 352 (c->gicr_ipriorityr[i + 2] << 16) | 353 (c->gicr_ipriorityr[i + 3] << 24); 354 kvm_gicr_access(s, GICR_IPRIORITYR + i, ncpu, ®, true); 355 } 356 } 357 358 /* Distributor state (shared between all CPUs */ 359 reg = s->gicd_statusr[GICV3_NS]; 360 kvm_gicd_access(s, GICD_STATUSR, ®, true); 361 362 /* s->enable bitmap -> GICD_ISENABLERn */ 363 kvm_dist_putbmp(s, GICD_ISENABLER, GICD_ICENABLER, s->enabled); 364 365 /* s->group bitmap -> GICD_IGROUPRn */ 366 kvm_dist_putbmp(s, GICD_IGROUPR, 0, s->group); 367 368 /* Restore targets before pending to ensure the pending state is set on 369 * the appropriate CPU interfaces in the kernel 370 */ 371 372 /* s->gicd_irouter[irq] -> GICD_IROUTERn 373 * We can't use kvm_dist_put() here because the registers are 64-bit 374 */ 375 for (i = GIC_INTERNAL; i < s->num_irq; i++) { 376 uint32_t offset; 377 378 offset = GICD_IROUTER + (sizeof(uint32_t) * i); 379 reg = (uint32_t)s->gicd_irouter[i]; 380 kvm_gicd_access(s, offset, ®, true); 381 382 offset = GICD_IROUTER + (sizeof(uint32_t) * i) + 4; 383 reg = (uint32_t)(s->gicd_irouter[i] >> 32); 384 kvm_gicd_access(s, offset, ®, true); 385 } 386 387 /* s->trigger bitmap -> GICD_ICFGRn 388 * (restore configuration registers before pending IRQs so we treat 389 * level/edge correctly) 390 */ 391 kvm_dist_put_edge_trigger(s, GICD_ICFGR, s->edge_trigger); 392 393 /* s->level bitmap -> line_level */ 394 kvm_gic_put_line_level_bmp(s, s->level); 395 396 /* s->pending bitmap -> GICD_ISPENDRn */ 397 kvm_dist_putbmp(s, GICD_ISPENDR, GICD_ICPENDR, s->pending); 398 399 /* s->active bitmap -> GICD_ISACTIVERn */ 400 kvm_dist_putbmp(s, GICD_ISACTIVER, GICD_ICACTIVER, s->active); 401 402 /* s->gicd_ipriority[] -> GICD_IPRIORITYRn */ 403 kvm_dist_put_priority(s, GICD_IPRIORITYR, s->gicd_ipriority); 404 405 /* CPU Interface state (one per CPU) */ 406 407 for (ncpu = 0; ncpu < s->num_cpu; ncpu++) { 408 GICv3CPUState *c = &s->cpu[ncpu]; 409 int num_pri_bits; 410 411 kvm_gicc_access(s, ICC_SRE_EL1, ncpu, &c->icc_sre_el1, true); 412 kvm_gicc_access(s, ICC_CTLR_EL1, ncpu, 413 &c->icc_ctlr_el1[GICV3_NS], true); 414 kvm_gicc_access(s, ICC_IGRPEN0_EL1, ncpu, 415 &c->icc_igrpen[GICV3_G0], true); 416 kvm_gicc_access(s, ICC_IGRPEN1_EL1, ncpu, 417 &c->icc_igrpen[GICV3_G1NS], true); 418 kvm_gicc_access(s, ICC_PMR_EL1, ncpu, &c->icc_pmr_el1, true); 419 kvm_gicc_access(s, ICC_BPR0_EL1, ncpu, &c->icc_bpr[GICV3_G0], true); 420 kvm_gicc_access(s, ICC_BPR1_EL1, ncpu, &c->icc_bpr[GICV3_G1NS], true); 421 422 num_pri_bits = ((c->icc_ctlr_el1[GICV3_NS] & 423 ICC_CTLR_EL1_PRIBITS_MASK) >> 424 ICC_CTLR_EL1_PRIBITS_SHIFT) + 1; 425 426 switch (num_pri_bits) { 427 case 7: 428 reg64 = c->icc_apr[GICV3_G0][3]; 429 kvm_gicc_access(s, ICC_AP0R_EL1(3), ncpu, ®64, true); 430 reg64 = c->icc_apr[GICV3_G0][2]; 431 kvm_gicc_access(s, ICC_AP0R_EL1(2), ncpu, ®64, true); 432 case 6: 433 reg64 = c->icc_apr[GICV3_G0][1]; 434 kvm_gicc_access(s, ICC_AP0R_EL1(1), ncpu, ®64, true); 435 default: 436 reg64 = c->icc_apr[GICV3_G0][0]; 437 kvm_gicc_access(s, ICC_AP0R_EL1(0), ncpu, ®64, true); 438 } 439 440 switch (num_pri_bits) { 441 case 7: 442 reg64 = c->icc_apr[GICV3_G1NS][3]; 443 kvm_gicc_access(s, ICC_AP1R_EL1(3), ncpu, ®64, true); 444 reg64 = c->icc_apr[GICV3_G1NS][2]; 445 kvm_gicc_access(s, ICC_AP1R_EL1(2), ncpu, ®64, true); 446 case 6: 447 reg64 = c->icc_apr[GICV3_G1NS][1]; 448 kvm_gicc_access(s, ICC_AP1R_EL1(1), ncpu, ®64, true); 449 default: 450 reg64 = c->icc_apr[GICV3_G1NS][0]; 451 kvm_gicc_access(s, ICC_AP1R_EL1(0), ncpu, ®64, true); 452 } 453 } 454 } 455 456 static void kvm_arm_gicv3_get(GICv3State *s) 457 { 458 uint32_t regl, regh, reg; 459 uint64_t reg64, redist_typer; 460 int ncpu, i; 461 462 kvm_arm_gicv3_check(s); 463 464 kvm_gicr_access(s, GICR_TYPER, 0, ®l, false); 465 kvm_gicr_access(s, GICR_TYPER + 4, 0, ®h, false); 466 redist_typer = ((uint64_t)regh << 32) | regl; 467 468 kvm_gicd_access(s, GICD_CTLR, ®, false); 469 s->gicd_ctlr = reg; 470 471 /* Redistributor state (one per CPU) */ 472 473 for (ncpu = 0; ncpu < s->num_cpu; ncpu++) { 474 GICv3CPUState *c = &s->cpu[ncpu]; 475 476 kvm_gicr_access(s, GICR_CTLR, ncpu, ®, false); 477 c->gicr_ctlr = reg; 478 479 kvm_gicr_access(s, GICR_STATUSR, ncpu, ®, false); 480 c->gicr_statusr[GICV3_NS] = reg; 481 482 kvm_gicr_access(s, GICR_WAKER, ncpu, ®, false); 483 c->gicr_waker = reg; 484 485 kvm_gicr_access(s, GICR_IGROUPR0, ncpu, ®, false); 486 c->gicr_igroupr0 = reg; 487 kvm_gicr_access(s, GICR_ISENABLER0, ncpu, ®, false); 488 c->gicr_ienabler0 = reg; 489 kvm_gicr_access(s, GICR_ICFGR1, ncpu, ®, false); 490 c->edge_trigger = half_unshuffle32(reg >> 1) << 16; 491 kvm_gic_line_level_access(s, 0, ncpu, ®, false); 492 c->level = reg; 493 kvm_gicr_access(s, GICR_ISPENDR0, ncpu, ®, false); 494 c->gicr_ipendr0 = reg; 495 kvm_gicr_access(s, GICR_ISACTIVER0, ncpu, ®, false); 496 c->gicr_iactiver0 = reg; 497 498 for (i = 0; i < GIC_INTERNAL; i += 4) { 499 kvm_gicr_access(s, GICR_IPRIORITYR + i, ncpu, ®, false); 500 c->gicr_ipriorityr[i] = extract32(reg, 0, 8); 501 c->gicr_ipriorityr[i + 1] = extract32(reg, 8, 8); 502 c->gicr_ipriorityr[i + 2] = extract32(reg, 16, 8); 503 c->gicr_ipriorityr[i + 3] = extract32(reg, 24, 8); 504 } 505 } 506 507 if (redist_typer & GICR_TYPER_PLPIS) { 508 for (ncpu = 0; ncpu < s->num_cpu; ncpu++) { 509 GICv3CPUState *c = &s->cpu[ncpu]; 510 511 kvm_gicr_access(s, GICR_PROPBASER, ncpu, ®l, false); 512 kvm_gicr_access(s, GICR_PROPBASER + 4, ncpu, ®h, false); 513 c->gicr_propbaser = ((uint64_t)regh << 32) | regl; 514 515 kvm_gicr_access(s, GICR_PENDBASER, ncpu, ®l, false); 516 kvm_gicr_access(s, GICR_PENDBASER + 4, ncpu, ®h, false); 517 c->gicr_pendbaser = ((uint64_t)regh << 32) | regl; 518 } 519 } 520 521 /* Distributor state (shared between all CPUs */ 522 523 kvm_gicd_access(s, GICD_STATUSR, ®, false); 524 s->gicd_statusr[GICV3_NS] = reg; 525 526 /* GICD_IGROUPRn -> s->group bitmap */ 527 kvm_dist_getbmp(s, GICD_IGROUPR, s->group); 528 529 /* GICD_ISENABLERn -> s->enabled bitmap */ 530 kvm_dist_getbmp(s, GICD_ISENABLER, s->enabled); 531 532 /* Line level of irq */ 533 kvm_gic_get_line_level_bmp(s, s->level); 534 /* GICD_ISPENDRn -> s->pending bitmap */ 535 kvm_dist_getbmp(s, GICD_ISPENDR, s->pending); 536 537 /* GICD_ISACTIVERn -> s->active bitmap */ 538 kvm_dist_getbmp(s, GICD_ISACTIVER, s->active); 539 540 /* GICD_ICFGRn -> s->trigger bitmap */ 541 kvm_dist_get_edge_trigger(s, GICD_ICFGR, s->edge_trigger); 542 543 /* GICD_IPRIORITYRn -> s->gicd_ipriority[] */ 544 kvm_dist_get_priority(s, GICD_IPRIORITYR, s->gicd_ipriority); 545 546 /* GICD_IROUTERn -> s->gicd_irouter[irq] */ 547 for (i = GIC_INTERNAL; i < s->num_irq; i++) { 548 uint32_t offset; 549 550 offset = GICD_IROUTER + (sizeof(uint32_t) * i); 551 kvm_gicd_access(s, offset, ®l, false); 552 offset = GICD_IROUTER + (sizeof(uint32_t) * i) + 4; 553 kvm_gicd_access(s, offset, ®h, false); 554 s->gicd_irouter[i] = ((uint64_t)regh << 32) | regl; 555 } 556 557 /***************************************************************** 558 * CPU Interface(s) State 559 */ 560 561 for (ncpu = 0; ncpu < s->num_cpu; ncpu++) { 562 GICv3CPUState *c = &s->cpu[ncpu]; 563 int num_pri_bits; 564 565 kvm_gicc_access(s, ICC_SRE_EL1, ncpu, &c->icc_sre_el1, false); 566 kvm_gicc_access(s, ICC_CTLR_EL1, ncpu, 567 &c->icc_ctlr_el1[GICV3_NS], false); 568 kvm_gicc_access(s, ICC_IGRPEN0_EL1, ncpu, 569 &c->icc_igrpen[GICV3_G0], false); 570 kvm_gicc_access(s, ICC_IGRPEN1_EL1, ncpu, 571 &c->icc_igrpen[GICV3_G1NS], false); 572 kvm_gicc_access(s, ICC_PMR_EL1, ncpu, &c->icc_pmr_el1, false); 573 kvm_gicc_access(s, ICC_BPR0_EL1, ncpu, &c->icc_bpr[GICV3_G0], false); 574 kvm_gicc_access(s, ICC_BPR1_EL1, ncpu, &c->icc_bpr[GICV3_G1NS], false); 575 num_pri_bits = ((c->icc_ctlr_el1[GICV3_NS] & 576 ICC_CTLR_EL1_PRIBITS_MASK) >> 577 ICC_CTLR_EL1_PRIBITS_SHIFT) + 1; 578 579 switch (num_pri_bits) { 580 case 7: 581 kvm_gicc_access(s, ICC_AP0R_EL1(3), ncpu, ®64, false); 582 c->icc_apr[GICV3_G0][3] = reg64; 583 kvm_gicc_access(s, ICC_AP0R_EL1(2), ncpu, ®64, false); 584 c->icc_apr[GICV3_G0][2] = reg64; 585 case 6: 586 kvm_gicc_access(s, ICC_AP0R_EL1(1), ncpu, ®64, false); 587 c->icc_apr[GICV3_G0][1] = reg64; 588 default: 589 kvm_gicc_access(s, ICC_AP0R_EL1(0), ncpu, ®64, false); 590 c->icc_apr[GICV3_G0][0] = reg64; 591 } 592 593 switch (num_pri_bits) { 594 case 7: 595 kvm_gicc_access(s, ICC_AP1R_EL1(3), ncpu, ®64, false); 596 c->icc_apr[GICV3_G1NS][3] = reg64; 597 kvm_gicc_access(s, ICC_AP1R_EL1(2), ncpu, ®64, false); 598 c->icc_apr[GICV3_G1NS][2] = reg64; 599 case 6: 600 kvm_gicc_access(s, ICC_AP1R_EL1(1), ncpu, ®64, false); 601 c->icc_apr[GICV3_G1NS][1] = reg64; 602 default: 603 kvm_gicc_access(s, ICC_AP1R_EL1(0), ncpu, ®64, false); 604 c->icc_apr[GICV3_G1NS][0] = reg64; 605 } 606 } 607 } 608 609 static void arm_gicv3_icc_reset(CPUARMState *env, const ARMCPRegInfo *ri) 610 { 611 ARMCPU *cpu; 612 GICv3State *s; 613 GICv3CPUState *c; 614 615 c = (GICv3CPUState *)env->gicv3state; 616 s = c->gic; 617 cpu = ARM_CPU(c->cpu); 618 619 c->icc_pmr_el1 = 0; 620 c->icc_bpr[GICV3_G0] = GIC_MIN_BPR; 621 c->icc_bpr[GICV3_G1] = GIC_MIN_BPR; 622 c->icc_bpr[GICV3_G1NS] = GIC_MIN_BPR; 623 624 c->icc_sre_el1 = 0x7; 625 memset(c->icc_apr, 0, sizeof(c->icc_apr)); 626 memset(c->icc_igrpen, 0, sizeof(c->icc_igrpen)); 627 628 if (s->migration_blocker) { 629 return; 630 } 631 632 /* Initialize to actual HW supported configuration */ 633 kvm_device_access(s->dev_fd, KVM_DEV_ARM_VGIC_GRP_CPU_SYSREGS, 634 KVM_VGIC_ATTR(ICC_CTLR_EL1, cpu->mp_affinity), 635 &c->icc_ctlr_el1[GICV3_NS], false, &error_abort); 636 637 c->icc_ctlr_el1[GICV3_S] = c->icc_ctlr_el1[GICV3_NS]; 638 } 639 640 static void kvm_arm_gicv3_reset(DeviceState *dev) 641 { 642 GICv3State *s = ARM_GICV3_COMMON(dev); 643 KVMARMGICv3Class *kgc = KVM_ARM_GICV3_GET_CLASS(s); 644 645 DPRINTF("Reset\n"); 646 647 kgc->parent_reset(dev); 648 649 if (s->migration_blocker) { 650 DPRINTF("Cannot put kernel gic state, no kernel interface\n"); 651 return; 652 } 653 654 kvm_arm_gicv3_put(s); 655 } 656 657 /* 658 * CPU interface registers of GIC needs to be reset on CPU reset. 659 * For the calling arm_gicv3_icc_reset() on CPU reset, we register 660 * below ARMCPRegInfo. As we reset the whole cpu interface under single 661 * register reset, we define only one register of CPU interface instead 662 * of defining all the registers. 663 */ 664 static const ARMCPRegInfo gicv3_cpuif_reginfo[] = { 665 { .name = "ICC_CTLR_EL1", .state = ARM_CP_STATE_BOTH, 666 .opc0 = 3, .opc1 = 0, .crn = 12, .crm = 12, .opc2 = 4, 667 /* 668 * If ARM_CP_NOP is used, resetfn is not called, 669 * So ARM_CP_NO_RAW is appropriate type. 670 */ 671 .type = ARM_CP_NO_RAW, 672 .access = PL1_RW, 673 .readfn = arm_cp_read_zero, 674 .writefn = arm_cp_write_ignore, 675 /* 676 * We hang the whole cpu interface reset routine off here 677 * rather than parcelling it out into one little function 678 * per register 679 */ 680 .resetfn = arm_gicv3_icc_reset, 681 }, 682 REGINFO_SENTINEL 683 }; 684 685 /** 686 * vm_change_state_handler - VM change state callback aiming at flushing 687 * RDIST pending tables into guest RAM 688 * 689 * The tables get flushed to guest RAM whenever the VM gets stopped. 690 */ 691 static void vm_change_state_handler(void *opaque, int running, 692 RunState state) 693 { 694 GICv3State *s = (GICv3State *)opaque; 695 Error *err = NULL; 696 int ret; 697 698 if (running) { 699 return; 700 } 701 702 ret = kvm_device_access(s->dev_fd, KVM_DEV_ARM_VGIC_GRP_CTRL, 703 KVM_DEV_ARM_VGIC_SAVE_PENDING_TABLES, 704 NULL, true, &err); 705 if (err) { 706 error_report_err(err); 707 } 708 if (ret < 0 && ret != -EFAULT) { 709 abort(); 710 } 711 } 712 713 714 static void kvm_arm_gicv3_realize(DeviceState *dev, Error **errp) 715 { 716 GICv3State *s = KVM_ARM_GICV3(dev); 717 KVMARMGICv3Class *kgc = KVM_ARM_GICV3_GET_CLASS(s); 718 Error *local_err = NULL; 719 int i; 720 721 DPRINTF("kvm_arm_gicv3_realize\n"); 722 723 kgc->parent_realize(dev, &local_err); 724 if (local_err) { 725 error_propagate(errp, local_err); 726 return; 727 } 728 729 if (s->security_extn) { 730 error_setg(errp, "the in-kernel VGICv3 does not implement the " 731 "security extensions"); 732 return; 733 } 734 735 gicv3_init_irqs_and_mmio(s, kvm_arm_gicv3_set_irq, NULL); 736 737 for (i = 0; i < s->num_cpu; i++) { 738 ARMCPU *cpu = ARM_CPU(qemu_get_cpu(i)); 739 740 define_arm_cp_regs(cpu, gicv3_cpuif_reginfo); 741 } 742 743 /* Try to create the device via the device control API */ 744 s->dev_fd = kvm_create_device(kvm_state, KVM_DEV_TYPE_ARM_VGIC_V3, false); 745 if (s->dev_fd < 0) { 746 error_setg_errno(errp, -s->dev_fd, "error creating in-kernel VGIC"); 747 return; 748 } 749 750 kvm_device_access(s->dev_fd, KVM_DEV_ARM_VGIC_GRP_NR_IRQS, 751 0, &s->num_irq, true, &error_abort); 752 753 /* Tell the kernel to complete VGIC initialization now */ 754 kvm_device_access(s->dev_fd, KVM_DEV_ARM_VGIC_GRP_CTRL, 755 KVM_DEV_ARM_VGIC_CTRL_INIT, NULL, true, &error_abort); 756 757 kvm_arm_register_device(&s->iomem_dist, -1, KVM_DEV_ARM_VGIC_GRP_ADDR, 758 KVM_VGIC_V3_ADDR_TYPE_DIST, s->dev_fd); 759 kvm_arm_register_device(&s->iomem_redist, -1, KVM_DEV_ARM_VGIC_GRP_ADDR, 760 KVM_VGIC_V3_ADDR_TYPE_REDIST, s->dev_fd); 761 762 if (kvm_has_gsi_routing()) { 763 /* set up irq routing */ 764 for (i = 0; i < s->num_irq - GIC_INTERNAL; ++i) { 765 kvm_irqchip_add_irq_route(kvm_state, i, 0, i); 766 } 767 768 kvm_gsi_routing_allowed = true; 769 770 kvm_irqchip_commit_routes(kvm_state); 771 } 772 773 if (!kvm_device_check_attr(s->dev_fd, KVM_DEV_ARM_VGIC_GRP_DIST_REGS, 774 GICD_CTLR)) { 775 error_setg(&s->migration_blocker, "This operating system kernel does " 776 "not support vGICv3 migration"); 777 migrate_add_blocker(s->migration_blocker, &local_err); 778 if (local_err) { 779 error_propagate(errp, local_err); 780 error_free(s->migration_blocker); 781 return; 782 } 783 } 784 if (kvm_device_check_attr(s->dev_fd, KVM_DEV_ARM_VGIC_GRP_CTRL, 785 KVM_DEV_ARM_VGIC_SAVE_PENDING_TABLES)) { 786 qemu_add_vm_change_state_handler(vm_change_state_handler, s); 787 } 788 } 789 790 static void kvm_arm_gicv3_class_init(ObjectClass *klass, void *data) 791 { 792 DeviceClass *dc = DEVICE_CLASS(klass); 793 ARMGICv3CommonClass *agcc = ARM_GICV3_COMMON_CLASS(klass); 794 KVMARMGICv3Class *kgc = KVM_ARM_GICV3_CLASS(klass); 795 796 agcc->pre_save = kvm_arm_gicv3_get; 797 agcc->post_load = kvm_arm_gicv3_put; 798 device_class_set_parent_realize(dc, kvm_arm_gicv3_realize, 799 &kgc->parent_realize); 800 device_class_set_parent_reset(dc, kvm_arm_gicv3_reset, &kgc->parent_reset); 801 } 802 803 static const TypeInfo kvm_arm_gicv3_info = { 804 .name = TYPE_KVM_ARM_GICV3, 805 .parent = TYPE_ARM_GICV3_COMMON, 806 .instance_size = sizeof(GICv3State), 807 .class_init = kvm_arm_gicv3_class_init, 808 .class_size = sizeof(KVMARMGICv3Class), 809 }; 810 811 static void kvm_arm_gicv3_register_types(void) 812 { 813 type_register_static(&kvm_arm_gicv3_info); 814 } 815 816 type_init(kvm_arm_gicv3_register_types) 817