1 /* 2 * ARM GICv3 support - common bits of emulated and KVM kernel model 3 * 4 * Copyright (c) 2012 Linaro Limited 5 * Copyright (c) 2015 Huawei. 6 * Copyright (c) 2015 Samsung Electronics Co., Ltd. 7 * Written by Peter Maydell 8 * Reworked for GICv3 by Shlomo Pongratz and Pavel Fedin 9 * 10 * This program is free software; you can redistribute it and/or modify 11 * it under the terms of the GNU General Public License as published by 12 * the Free Software Foundation, either version 2 of the License, or 13 * (at your option) any later version. 14 * 15 * This program is distributed in the hope that it will be useful, 16 * but WITHOUT ANY WARRANTY; without even the implied warranty of 17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 18 * GNU General Public License for more details. 19 * 20 * You should have received a copy of the GNU General Public License along 21 * with this program; if not, see <http://www.gnu.org/licenses/>. 22 */ 23 24 #include "qemu/osdep.h" 25 #include "qapi/error.h" 26 #include "qom/cpu.h" 27 #include "hw/intc/arm_gicv3_common.h" 28 #include "gicv3_internal.h" 29 #include "hw/arm/linux-boot-if.h" 30 31 static void gicv3_pre_save(void *opaque) 32 { 33 GICv3State *s = (GICv3State *)opaque; 34 ARMGICv3CommonClass *c = ARM_GICV3_COMMON_GET_CLASS(s); 35 36 if (c->pre_save) { 37 c->pre_save(s); 38 } 39 } 40 41 static int gicv3_post_load(void *opaque, int version_id) 42 { 43 GICv3State *s = (GICv3State *)opaque; 44 ARMGICv3CommonClass *c = ARM_GICV3_COMMON_GET_CLASS(s); 45 46 if (c->post_load) { 47 c->post_load(s); 48 } 49 return 0; 50 } 51 52 static const VMStateDescription vmstate_gicv3_cpu = { 53 .name = "arm_gicv3_cpu", 54 .version_id = 1, 55 .minimum_version_id = 1, 56 .fields = (VMStateField[]) { 57 VMSTATE_UINT32(level, GICv3CPUState), 58 VMSTATE_UINT32(gicr_ctlr, GICv3CPUState), 59 VMSTATE_UINT32_ARRAY(gicr_statusr, GICv3CPUState, 2), 60 VMSTATE_UINT32(gicr_waker, GICv3CPUState), 61 VMSTATE_UINT64(gicr_propbaser, GICv3CPUState), 62 VMSTATE_UINT64(gicr_pendbaser, GICv3CPUState), 63 VMSTATE_UINT32(gicr_igroupr0, GICv3CPUState), 64 VMSTATE_UINT32(gicr_ienabler0, GICv3CPUState), 65 VMSTATE_UINT32(gicr_ipendr0, GICv3CPUState), 66 VMSTATE_UINT32(gicr_iactiver0, GICv3CPUState), 67 VMSTATE_UINT32(edge_trigger, GICv3CPUState), 68 VMSTATE_UINT32(gicr_igrpmodr0, GICv3CPUState), 69 VMSTATE_UINT32(gicr_nsacr, GICv3CPUState), 70 VMSTATE_UINT8_ARRAY(gicr_ipriorityr, GICv3CPUState, GIC_INTERNAL), 71 VMSTATE_UINT64_ARRAY(icc_ctlr_el1, GICv3CPUState, 2), 72 VMSTATE_UINT64(icc_pmr_el1, GICv3CPUState), 73 VMSTATE_UINT64_ARRAY(icc_bpr, GICv3CPUState, 3), 74 VMSTATE_UINT64_2DARRAY(icc_apr, GICv3CPUState, 3, 4), 75 VMSTATE_UINT64_ARRAY(icc_igrpen, GICv3CPUState, 3), 76 VMSTATE_UINT64(icc_ctlr_el3, GICv3CPUState), 77 VMSTATE_END_OF_LIST() 78 } 79 }; 80 81 static const VMStateDescription vmstate_gicv3 = { 82 .name = "arm_gicv3", 83 .version_id = 1, 84 .minimum_version_id = 1, 85 .pre_save = gicv3_pre_save, 86 .post_load = gicv3_post_load, 87 .fields = (VMStateField[]) { 88 VMSTATE_UINT32(gicd_ctlr, GICv3State), 89 VMSTATE_UINT32_ARRAY(gicd_statusr, GICv3State, 2), 90 VMSTATE_UINT32_ARRAY(group, GICv3State, GICV3_BMP_SIZE), 91 VMSTATE_UINT32_ARRAY(grpmod, GICv3State, GICV3_BMP_SIZE), 92 VMSTATE_UINT32_ARRAY(enabled, GICv3State, GICV3_BMP_SIZE), 93 VMSTATE_UINT32_ARRAY(pending, GICv3State, GICV3_BMP_SIZE), 94 VMSTATE_UINT32_ARRAY(active, GICv3State, GICV3_BMP_SIZE), 95 VMSTATE_UINT32_ARRAY(level, GICv3State, GICV3_BMP_SIZE), 96 VMSTATE_UINT32_ARRAY(edge_trigger, GICv3State, GICV3_BMP_SIZE), 97 VMSTATE_UINT8_ARRAY(gicd_ipriority, GICv3State, GICV3_MAXIRQ), 98 VMSTATE_UINT64_ARRAY(gicd_irouter, GICv3State, GICV3_MAXIRQ), 99 VMSTATE_UINT32_ARRAY(gicd_nsacr, GICv3State, 100 DIV_ROUND_UP(GICV3_MAXIRQ, 16)), 101 VMSTATE_STRUCT_VARRAY_POINTER_UINT32(cpu, GICv3State, num_cpu, 102 vmstate_gicv3_cpu, GICv3CPUState), 103 VMSTATE_END_OF_LIST() 104 } 105 }; 106 107 void gicv3_init_irqs_and_mmio(GICv3State *s, qemu_irq_handler handler, 108 const MemoryRegionOps *ops) 109 { 110 SysBusDevice *sbd = SYS_BUS_DEVICE(s); 111 int i; 112 113 /* For the GIC, also expose incoming GPIO lines for PPIs for each CPU. 114 * GPIO array layout is thus: 115 * [0..N-1] spi 116 * [N..N+31] PPIs for CPU 0 117 * [N+32..N+63] PPIs for CPU 1 118 * ... 119 */ 120 i = s->num_irq - GIC_INTERNAL + GIC_INTERNAL * s->num_cpu; 121 qdev_init_gpio_in(DEVICE(s), handler, i); 122 123 for (i = 0; i < s->num_cpu; i++) { 124 sysbus_init_irq(sbd, &s->cpu[i].parent_irq); 125 } 126 for (i = 0; i < s->num_cpu; i++) { 127 sysbus_init_irq(sbd, &s->cpu[i].parent_fiq); 128 } 129 for (i = 0; i < s->num_cpu; i++) { 130 sysbus_init_irq(sbd, &s->cpu[i].parent_virq); 131 } 132 for (i = 0; i < s->num_cpu; i++) { 133 sysbus_init_irq(sbd, &s->cpu[i].parent_vfiq); 134 } 135 136 memory_region_init_io(&s->iomem_dist, OBJECT(s), ops, s, 137 "gicv3_dist", 0x10000); 138 memory_region_init_io(&s->iomem_redist, OBJECT(s), ops ? &ops[1] : NULL, s, 139 "gicv3_redist", 0x20000 * s->num_cpu); 140 141 sysbus_init_mmio(sbd, &s->iomem_dist); 142 sysbus_init_mmio(sbd, &s->iomem_redist); 143 } 144 145 static void arm_gicv3_common_realize(DeviceState *dev, Error **errp) 146 { 147 GICv3State *s = ARM_GICV3_COMMON(dev); 148 int i; 149 150 /* revision property is actually reserved and currently used only in order 151 * to keep the interface compatible with GICv2 code, avoiding extra 152 * conditions. However, in future it could be used, for example, if we 153 * implement GICv4. 154 */ 155 if (s->revision != 3) { 156 error_setg(errp, "unsupported GIC revision %d", s->revision); 157 return; 158 } 159 160 if (s->num_irq > GICV3_MAXIRQ) { 161 error_setg(errp, 162 "requested %u interrupt lines exceeds GIC maximum %d", 163 s->num_irq, GICV3_MAXIRQ); 164 return; 165 } 166 if (s->num_irq < GIC_INTERNAL) { 167 error_setg(errp, 168 "requested %u interrupt lines is below GIC minimum %d", 169 s->num_irq, GIC_INTERNAL); 170 return; 171 } 172 173 /* ITLinesNumber is represented as (N / 32) - 1, so this is an 174 * implementation imposed restriction, not an architectural one, 175 * so we don't have to deal with bitfields where only some of the 176 * bits in a 32-bit word should be valid. 177 */ 178 if (s->num_irq % 32) { 179 error_setg(errp, 180 "%d interrupt lines unsupported: not divisible by 32", 181 s->num_irq); 182 return; 183 } 184 185 s->cpu = g_new0(GICv3CPUState, s->num_cpu); 186 187 for (i = 0; i < s->num_cpu; i++) { 188 CPUState *cpu = qemu_get_cpu(i); 189 uint64_t cpu_affid; 190 int last; 191 192 s->cpu[i].cpu = cpu; 193 s->cpu[i].gic = s; 194 195 /* Pre-construct the GICR_TYPER: 196 * For our implementation: 197 * Top 32 bits are the affinity value of the associated CPU 198 * CommonLPIAff == 01 (redistributors with same Aff3 share LPI table) 199 * Processor_Number == CPU index starting from 0 200 * DPGS == 0 (GICR_CTLR.DPG* not supported) 201 * Last == 1 if this is the last redistributor in a series of 202 * contiguous redistributor pages 203 * DirectLPI == 0 (direct injection of LPIs not supported) 204 * VLPIS == 0 (virtual LPIs not supported) 205 * PLPIS == 0 (physical LPIs not supported) 206 */ 207 cpu_affid = object_property_get_int(OBJECT(cpu), "mp-affinity", NULL); 208 last = (i == s->num_cpu - 1); 209 210 /* The CPU mp-affinity property is in MPIDR register format; squash 211 * the affinity bytes into 32 bits as the GICR_TYPER has them. 212 */ 213 cpu_affid = ((cpu_affid & 0xFF00000000ULL) >> 8) | 214 (cpu_affid & 0xFFFFFF); 215 s->cpu[i].gicr_typer = (cpu_affid << 32) | 216 (1 << 24) | 217 (i << 8) | 218 (last << 4); 219 } 220 } 221 222 static void arm_gicv3_common_reset(DeviceState *dev) 223 { 224 GICv3State *s = ARM_GICV3_COMMON(dev); 225 int i; 226 227 for (i = 0; i < s->num_cpu; i++) { 228 GICv3CPUState *cs = &s->cpu[i]; 229 230 cs->level = 0; 231 cs->gicr_ctlr = 0; 232 cs->gicr_statusr[GICV3_S] = 0; 233 cs->gicr_statusr[GICV3_NS] = 0; 234 cs->gicr_waker = GICR_WAKER_ProcessorSleep | GICR_WAKER_ChildrenAsleep; 235 cs->gicr_propbaser = 0; 236 cs->gicr_pendbaser = 0; 237 /* If we're resetting a TZ-aware GIC as if secure firmware 238 * had set it up ready to start a kernel in non-secure, we 239 * need to set interrupts to group 1 so the kernel can use them. 240 * Otherwise they reset to group 0 like the hardware. 241 */ 242 if (s->irq_reset_nonsecure) { 243 cs->gicr_igroupr0 = 0xffffffff; 244 } else { 245 cs->gicr_igroupr0 = 0; 246 } 247 248 cs->gicr_ienabler0 = 0; 249 cs->gicr_ipendr0 = 0; 250 cs->gicr_iactiver0 = 0; 251 cs->edge_trigger = 0xffff; 252 cs->gicr_igrpmodr0 = 0; 253 cs->gicr_nsacr = 0; 254 memset(cs->gicr_ipriorityr, 0, sizeof(cs->gicr_ipriorityr)); 255 256 cs->hppi.prio = 0xff; 257 258 /* State in the CPU interface must *not* be reset here, because it 259 * is part of the CPU's reset domain, not the GIC device's. 260 */ 261 } 262 263 /* For our implementation affinity routing is always enabled */ 264 if (s->security_extn) { 265 s->gicd_ctlr = GICD_CTLR_ARE_S | GICD_CTLR_ARE_NS; 266 } else { 267 s->gicd_ctlr = GICD_CTLR_DS | GICD_CTLR_ARE; 268 } 269 270 s->gicd_statusr[GICV3_S] = 0; 271 s->gicd_statusr[GICV3_NS] = 0; 272 273 memset(s->group, 0, sizeof(s->group)); 274 memset(s->grpmod, 0, sizeof(s->grpmod)); 275 memset(s->enabled, 0, sizeof(s->enabled)); 276 memset(s->pending, 0, sizeof(s->pending)); 277 memset(s->active, 0, sizeof(s->active)); 278 memset(s->level, 0, sizeof(s->level)); 279 memset(s->edge_trigger, 0, sizeof(s->edge_trigger)); 280 memset(s->gicd_ipriority, 0, sizeof(s->gicd_ipriority)); 281 memset(s->gicd_irouter, 0, sizeof(s->gicd_irouter)); 282 memset(s->gicd_nsacr, 0, sizeof(s->gicd_nsacr)); 283 /* GICD_IROUTER are UNKNOWN at reset so in theory the guest must 284 * write these to get sane behaviour and we need not populate the 285 * pointer cache here; however having the cache be different for 286 * "happened to be 0 from reset" and "guest wrote 0" would be 287 * too confusing. 288 */ 289 gicv3_cache_all_target_cpustates(s); 290 291 if (s->irq_reset_nonsecure) { 292 /* If we're resetting a TZ-aware GIC as if secure firmware 293 * had set it up ready to start a kernel in non-secure, we 294 * need to set interrupts to group 1 so the kernel can use them. 295 * Otherwise they reset to group 0 like the hardware. 296 */ 297 for (i = GIC_INTERNAL; i < s->num_irq; i++) { 298 gicv3_gicd_group_set(s, i); 299 } 300 } 301 } 302 303 static void arm_gic_common_linux_init(ARMLinuxBootIf *obj, 304 bool secure_boot) 305 { 306 GICv3State *s = ARM_GICV3_COMMON(obj); 307 308 if (s->security_extn && !secure_boot) { 309 /* We're directly booting a kernel into NonSecure. If this GIC 310 * implements the security extensions then we must configure it 311 * to have all the interrupts be NonSecure (this is a job that 312 * is done by the Secure boot firmware in real hardware, and in 313 * this mode QEMU is acting as a minimalist firmware-and-bootloader 314 * equivalent). 315 */ 316 s->irq_reset_nonsecure = true; 317 } 318 } 319 320 static Property arm_gicv3_common_properties[] = { 321 DEFINE_PROP_UINT32("num-cpu", GICv3State, num_cpu, 1), 322 DEFINE_PROP_UINT32("num-irq", GICv3State, num_irq, 32), 323 DEFINE_PROP_UINT32("revision", GICv3State, revision, 3), 324 DEFINE_PROP_BOOL("has-security-extensions", GICv3State, security_extn, 0), 325 DEFINE_PROP_END_OF_LIST(), 326 }; 327 328 static void arm_gicv3_common_class_init(ObjectClass *klass, void *data) 329 { 330 DeviceClass *dc = DEVICE_CLASS(klass); 331 ARMLinuxBootIfClass *albifc = ARM_LINUX_BOOT_IF_CLASS(klass); 332 333 dc->reset = arm_gicv3_common_reset; 334 dc->realize = arm_gicv3_common_realize; 335 dc->props = arm_gicv3_common_properties; 336 dc->vmsd = &vmstate_gicv3; 337 albifc->arm_linux_init = arm_gic_common_linux_init; 338 } 339 340 static const TypeInfo arm_gicv3_common_type = { 341 .name = TYPE_ARM_GICV3_COMMON, 342 .parent = TYPE_SYS_BUS_DEVICE, 343 .instance_size = sizeof(GICv3State), 344 .class_size = sizeof(ARMGICv3CommonClass), 345 .class_init = arm_gicv3_common_class_init, 346 .abstract = true, 347 .interfaces = (InterfaceInfo []) { 348 { TYPE_ARM_LINUX_BOOT_IF }, 349 { }, 350 }, 351 }; 352 353 static void register_types(void) 354 { 355 type_register_static(&arm_gicv3_common_type); 356 } 357 358 type_init(register_types) 359