1 /* 2 * APIC support 3 * 4 * Copyright (c) 2004-2005 Fabrice Bellard 5 * 6 * This library is free software; you can redistribute it and/or 7 * modify it under the terms of the GNU Lesser General Public 8 * License as published by the Free Software Foundation; either 9 * version 2 of the License, or (at your option) any later version. 10 * 11 * This library is distributed in the hope that it will be useful, 12 * but WITHOUT ANY WARRANTY; without even the implied warranty of 13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 14 * Lesser General Public License for more details. 15 * 16 * You should have received a copy of the GNU Lesser General Public 17 * License along with this library; if not, see <http://www.gnu.org/licenses/> 18 */ 19 #include "hw.h" 20 #include "apic.h" 21 #include "ioapic.h" 22 #include "qemu-timer.h" 23 #include "host-utils.h" 24 #include "sysbus.h" 25 #include "trace.h" 26 #include "pc.h" 27 28 /* APIC Local Vector Table */ 29 #define APIC_LVT_TIMER 0 30 #define APIC_LVT_THERMAL 1 31 #define APIC_LVT_PERFORM 2 32 #define APIC_LVT_LINT0 3 33 #define APIC_LVT_LINT1 4 34 #define APIC_LVT_ERROR 5 35 #define APIC_LVT_NB 6 36 37 /* APIC delivery modes */ 38 #define APIC_DM_FIXED 0 39 #define APIC_DM_LOWPRI 1 40 #define APIC_DM_SMI 2 41 #define APIC_DM_NMI 4 42 #define APIC_DM_INIT 5 43 #define APIC_DM_SIPI 6 44 #define APIC_DM_EXTINT 7 45 46 /* APIC destination mode */ 47 #define APIC_DESTMODE_FLAT 0xf 48 #define APIC_DESTMODE_CLUSTER 1 49 50 #define APIC_TRIGGER_EDGE 0 51 #define APIC_TRIGGER_LEVEL 1 52 53 #define APIC_LVT_TIMER_PERIODIC (1<<17) 54 #define APIC_LVT_MASKED (1<<16) 55 #define APIC_LVT_LEVEL_TRIGGER (1<<15) 56 #define APIC_LVT_REMOTE_IRR (1<<14) 57 #define APIC_INPUT_POLARITY (1<<13) 58 #define APIC_SEND_PENDING (1<<12) 59 60 #define ESR_ILLEGAL_ADDRESS (1 << 7) 61 62 #define APIC_SV_DIRECTED_IO (1<<12) 63 #define APIC_SV_ENABLE (1<<8) 64 65 #define MAX_APICS 255 66 #define MAX_APIC_WORDS 8 67 68 /* Intel APIC constants: from include/asm/msidef.h */ 69 #define MSI_DATA_VECTOR_SHIFT 0 70 #define MSI_DATA_VECTOR_MASK 0x000000ff 71 #define MSI_DATA_DELIVERY_MODE_SHIFT 8 72 #define MSI_DATA_TRIGGER_SHIFT 15 73 #define MSI_DATA_LEVEL_SHIFT 14 74 #define MSI_ADDR_DEST_MODE_SHIFT 2 75 #define MSI_ADDR_DEST_ID_SHIFT 12 76 #define MSI_ADDR_DEST_ID_MASK 0x00ffff0 77 78 #define MSI_ADDR_SIZE 0x100000 79 80 typedef struct APICState APICState; 81 82 struct APICState { 83 SysBusDevice busdev; 84 MemoryRegion io_memory; 85 void *cpu_env; 86 uint32_t apicbase; 87 uint8_t id; 88 uint8_t arb_id; 89 uint8_t tpr; 90 uint32_t spurious_vec; 91 uint8_t log_dest; 92 uint8_t dest_mode; 93 uint32_t isr[8]; /* in service register */ 94 uint32_t tmr[8]; /* trigger mode register */ 95 uint32_t irr[8]; /* interrupt request register */ 96 uint32_t lvt[APIC_LVT_NB]; 97 uint32_t esr; /* error register */ 98 uint32_t icr[2]; 99 100 uint32_t divide_conf; 101 int count_shift; 102 uint32_t initial_count; 103 int64_t initial_count_load_time, next_time; 104 uint32_t idx; 105 QEMUTimer *timer; 106 int sipi_vector; 107 int wait_for_sipi; 108 }; 109 110 static APICState *local_apics[MAX_APICS + 1]; 111 static int apic_irq_delivered; 112 113 static void apic_set_irq(APICState *s, int vector_num, int trigger_mode); 114 static void apic_update_irq(APICState *s); 115 static void apic_get_delivery_bitmask(uint32_t *deliver_bitmask, 116 uint8_t dest, uint8_t dest_mode); 117 118 /* Find first bit starting from msb */ 119 static int fls_bit(uint32_t value) 120 { 121 return 31 - clz32(value); 122 } 123 124 /* Find first bit starting from lsb */ 125 static int ffs_bit(uint32_t value) 126 { 127 return ctz32(value); 128 } 129 130 static inline void set_bit(uint32_t *tab, int index) 131 { 132 int i, mask; 133 i = index >> 5; 134 mask = 1 << (index & 0x1f); 135 tab[i] |= mask; 136 } 137 138 static inline void reset_bit(uint32_t *tab, int index) 139 { 140 int i, mask; 141 i = index >> 5; 142 mask = 1 << (index & 0x1f); 143 tab[i] &= ~mask; 144 } 145 146 static inline int get_bit(uint32_t *tab, int index) 147 { 148 int i, mask; 149 i = index >> 5; 150 mask = 1 << (index & 0x1f); 151 return !!(tab[i] & mask); 152 } 153 154 static void apic_local_deliver(APICState *s, int vector) 155 { 156 uint32_t lvt = s->lvt[vector]; 157 int trigger_mode; 158 159 trace_apic_local_deliver(vector, (lvt >> 8) & 7); 160 161 if (lvt & APIC_LVT_MASKED) 162 return; 163 164 switch ((lvt >> 8) & 7) { 165 case APIC_DM_SMI: 166 cpu_interrupt(s->cpu_env, CPU_INTERRUPT_SMI); 167 break; 168 169 case APIC_DM_NMI: 170 cpu_interrupt(s->cpu_env, CPU_INTERRUPT_NMI); 171 break; 172 173 case APIC_DM_EXTINT: 174 cpu_interrupt(s->cpu_env, CPU_INTERRUPT_HARD); 175 break; 176 177 case APIC_DM_FIXED: 178 trigger_mode = APIC_TRIGGER_EDGE; 179 if ((vector == APIC_LVT_LINT0 || vector == APIC_LVT_LINT1) && 180 (lvt & APIC_LVT_LEVEL_TRIGGER)) 181 trigger_mode = APIC_TRIGGER_LEVEL; 182 apic_set_irq(s, lvt & 0xff, trigger_mode); 183 } 184 } 185 186 void apic_deliver_pic_intr(DeviceState *d, int level) 187 { 188 APICState *s = DO_UPCAST(APICState, busdev.qdev, d); 189 190 if (level) { 191 apic_local_deliver(s, APIC_LVT_LINT0); 192 } else { 193 uint32_t lvt = s->lvt[APIC_LVT_LINT0]; 194 195 switch ((lvt >> 8) & 7) { 196 case APIC_DM_FIXED: 197 if (!(lvt & APIC_LVT_LEVEL_TRIGGER)) 198 break; 199 reset_bit(s->irr, lvt & 0xff); 200 /* fall through */ 201 case APIC_DM_EXTINT: 202 cpu_reset_interrupt(s->cpu_env, CPU_INTERRUPT_HARD); 203 break; 204 } 205 } 206 } 207 208 #define foreach_apic(apic, deliver_bitmask, code) \ 209 {\ 210 int __i, __j, __mask;\ 211 for(__i = 0; __i < MAX_APIC_WORDS; __i++) {\ 212 __mask = deliver_bitmask[__i];\ 213 if (__mask) {\ 214 for(__j = 0; __j < 32; __j++) {\ 215 if (__mask & (1 << __j)) {\ 216 apic = local_apics[__i * 32 + __j];\ 217 if (apic) {\ 218 code;\ 219 }\ 220 }\ 221 }\ 222 }\ 223 }\ 224 } 225 226 static void apic_bus_deliver(const uint32_t *deliver_bitmask, 227 uint8_t delivery_mode, uint8_t vector_num, 228 uint8_t trigger_mode) 229 { 230 APICState *apic_iter; 231 232 switch (delivery_mode) { 233 case APIC_DM_LOWPRI: 234 /* XXX: search for focus processor, arbitration */ 235 { 236 int i, d; 237 d = -1; 238 for(i = 0; i < MAX_APIC_WORDS; i++) { 239 if (deliver_bitmask[i]) { 240 d = i * 32 + ffs_bit(deliver_bitmask[i]); 241 break; 242 } 243 } 244 if (d >= 0) { 245 apic_iter = local_apics[d]; 246 if (apic_iter) { 247 apic_set_irq(apic_iter, vector_num, trigger_mode); 248 } 249 } 250 } 251 return; 252 253 case APIC_DM_FIXED: 254 break; 255 256 case APIC_DM_SMI: 257 foreach_apic(apic_iter, deliver_bitmask, 258 cpu_interrupt(apic_iter->cpu_env, CPU_INTERRUPT_SMI) ); 259 return; 260 261 case APIC_DM_NMI: 262 foreach_apic(apic_iter, deliver_bitmask, 263 cpu_interrupt(apic_iter->cpu_env, CPU_INTERRUPT_NMI) ); 264 return; 265 266 case APIC_DM_INIT: 267 /* normal INIT IPI sent to processors */ 268 foreach_apic(apic_iter, deliver_bitmask, 269 cpu_interrupt(apic_iter->cpu_env, CPU_INTERRUPT_INIT) ); 270 return; 271 272 case APIC_DM_EXTINT: 273 /* handled in I/O APIC code */ 274 break; 275 276 default: 277 return; 278 } 279 280 foreach_apic(apic_iter, deliver_bitmask, 281 apic_set_irq(apic_iter, vector_num, trigger_mode) ); 282 } 283 284 void apic_deliver_irq(uint8_t dest, uint8_t dest_mode, uint8_t delivery_mode, 285 uint8_t vector_num, uint8_t trigger_mode) 286 { 287 uint32_t deliver_bitmask[MAX_APIC_WORDS]; 288 289 trace_apic_deliver_irq(dest, dest_mode, delivery_mode, vector_num, 290 trigger_mode); 291 292 apic_get_delivery_bitmask(deliver_bitmask, dest, dest_mode); 293 apic_bus_deliver(deliver_bitmask, delivery_mode, vector_num, trigger_mode); 294 } 295 296 void cpu_set_apic_base(DeviceState *d, uint64_t val) 297 { 298 APICState *s = DO_UPCAST(APICState, busdev.qdev, d); 299 300 trace_cpu_set_apic_base(val); 301 302 if (!s) 303 return; 304 s->apicbase = (val & 0xfffff000) | 305 (s->apicbase & (MSR_IA32_APICBASE_BSP | MSR_IA32_APICBASE_ENABLE)); 306 /* if disabled, cannot be enabled again */ 307 if (!(val & MSR_IA32_APICBASE_ENABLE)) { 308 s->apicbase &= ~MSR_IA32_APICBASE_ENABLE; 309 cpu_clear_apic_feature(s->cpu_env); 310 s->spurious_vec &= ~APIC_SV_ENABLE; 311 } 312 } 313 314 uint64_t cpu_get_apic_base(DeviceState *d) 315 { 316 APICState *s = DO_UPCAST(APICState, busdev.qdev, d); 317 318 trace_cpu_get_apic_base(s ? (uint64_t)s->apicbase: 0); 319 320 return s ? s->apicbase : 0; 321 } 322 323 void cpu_set_apic_tpr(DeviceState *d, uint8_t val) 324 { 325 APICState *s = DO_UPCAST(APICState, busdev.qdev, d); 326 327 if (!s) 328 return; 329 s->tpr = (val & 0x0f) << 4; 330 apic_update_irq(s); 331 } 332 333 uint8_t cpu_get_apic_tpr(DeviceState *d) 334 { 335 APICState *s = DO_UPCAST(APICState, busdev.qdev, d); 336 337 return s ? s->tpr >> 4 : 0; 338 } 339 340 /* return -1 if no bit is set */ 341 static int get_highest_priority_int(uint32_t *tab) 342 { 343 int i; 344 for(i = 7; i >= 0; i--) { 345 if (tab[i] != 0) { 346 return i * 32 + fls_bit(tab[i]); 347 } 348 } 349 return -1; 350 } 351 352 static int apic_get_ppr(APICState *s) 353 { 354 int tpr, isrv, ppr; 355 356 tpr = (s->tpr >> 4); 357 isrv = get_highest_priority_int(s->isr); 358 if (isrv < 0) 359 isrv = 0; 360 isrv >>= 4; 361 if (tpr >= isrv) 362 ppr = s->tpr; 363 else 364 ppr = isrv << 4; 365 return ppr; 366 } 367 368 static int apic_get_arb_pri(APICState *s) 369 { 370 /* XXX: arbitration */ 371 return 0; 372 } 373 374 375 /* 376 * <0 - low prio interrupt, 377 * 0 - no interrupt, 378 * >0 - interrupt number 379 */ 380 static int apic_irq_pending(APICState *s) 381 { 382 int irrv, ppr; 383 irrv = get_highest_priority_int(s->irr); 384 if (irrv < 0) { 385 return 0; 386 } 387 ppr = apic_get_ppr(s); 388 if (ppr && (irrv & 0xf0) <= (ppr & 0xf0)) { 389 return -1; 390 } 391 392 return irrv; 393 } 394 395 /* signal the CPU if an irq is pending */ 396 static void apic_update_irq(APICState *s) 397 { 398 if (!(s->spurious_vec & APIC_SV_ENABLE)) { 399 return; 400 } 401 if (apic_irq_pending(s) > 0) { 402 cpu_interrupt(s->cpu_env, CPU_INTERRUPT_HARD); 403 } else if (apic_accept_pic_intr(&s->busdev.qdev) && 404 pic_get_output(isa_pic)) { 405 apic_deliver_pic_intr(&s->busdev.qdev, 1); 406 } 407 } 408 409 void apic_reset_irq_delivered(void) 410 { 411 trace_apic_reset_irq_delivered(apic_irq_delivered); 412 413 apic_irq_delivered = 0; 414 } 415 416 int apic_get_irq_delivered(void) 417 { 418 trace_apic_get_irq_delivered(apic_irq_delivered); 419 420 return apic_irq_delivered; 421 } 422 423 static void apic_set_irq(APICState *s, int vector_num, int trigger_mode) 424 { 425 apic_irq_delivered += !get_bit(s->irr, vector_num); 426 427 trace_apic_set_irq(apic_irq_delivered); 428 429 set_bit(s->irr, vector_num); 430 if (trigger_mode) 431 set_bit(s->tmr, vector_num); 432 else 433 reset_bit(s->tmr, vector_num); 434 apic_update_irq(s); 435 } 436 437 static void apic_eoi(APICState *s) 438 { 439 int isrv; 440 isrv = get_highest_priority_int(s->isr); 441 if (isrv < 0) 442 return; 443 reset_bit(s->isr, isrv); 444 if (!(s->spurious_vec & APIC_SV_DIRECTED_IO) && get_bit(s->tmr, isrv)) { 445 ioapic_eoi_broadcast(isrv); 446 } 447 apic_update_irq(s); 448 } 449 450 static int apic_find_dest(uint8_t dest) 451 { 452 APICState *apic = local_apics[dest]; 453 int i; 454 455 if (apic && apic->id == dest) 456 return dest; /* shortcut in case apic->id == apic->idx */ 457 458 for (i = 0; i < MAX_APICS; i++) { 459 apic = local_apics[i]; 460 if (apic && apic->id == dest) 461 return i; 462 if (!apic) 463 break; 464 } 465 466 return -1; 467 } 468 469 static void apic_get_delivery_bitmask(uint32_t *deliver_bitmask, 470 uint8_t dest, uint8_t dest_mode) 471 { 472 APICState *apic_iter; 473 int i; 474 475 if (dest_mode == 0) { 476 if (dest == 0xff) { 477 memset(deliver_bitmask, 0xff, MAX_APIC_WORDS * sizeof(uint32_t)); 478 } else { 479 int idx = apic_find_dest(dest); 480 memset(deliver_bitmask, 0x00, MAX_APIC_WORDS * sizeof(uint32_t)); 481 if (idx >= 0) 482 set_bit(deliver_bitmask, idx); 483 } 484 } else { 485 /* XXX: cluster mode */ 486 memset(deliver_bitmask, 0x00, MAX_APIC_WORDS * sizeof(uint32_t)); 487 for(i = 0; i < MAX_APICS; i++) { 488 apic_iter = local_apics[i]; 489 if (apic_iter) { 490 if (apic_iter->dest_mode == 0xf) { 491 if (dest & apic_iter->log_dest) 492 set_bit(deliver_bitmask, i); 493 } else if (apic_iter->dest_mode == 0x0) { 494 if ((dest & 0xf0) == (apic_iter->log_dest & 0xf0) && 495 (dest & apic_iter->log_dest & 0x0f)) { 496 set_bit(deliver_bitmask, i); 497 } 498 } 499 } else { 500 break; 501 } 502 } 503 } 504 } 505 506 void apic_init_reset(DeviceState *d) 507 { 508 APICState *s = DO_UPCAST(APICState, busdev.qdev, d); 509 int i; 510 511 if (!s) 512 return; 513 514 s->tpr = 0; 515 s->spurious_vec = 0xff; 516 s->log_dest = 0; 517 s->dest_mode = 0xf; 518 memset(s->isr, 0, sizeof(s->isr)); 519 memset(s->tmr, 0, sizeof(s->tmr)); 520 memset(s->irr, 0, sizeof(s->irr)); 521 for(i = 0; i < APIC_LVT_NB; i++) 522 s->lvt[i] = 1 << 16; /* mask LVT */ 523 s->esr = 0; 524 memset(s->icr, 0, sizeof(s->icr)); 525 s->divide_conf = 0; 526 s->count_shift = 0; 527 s->initial_count = 0; 528 s->initial_count_load_time = 0; 529 s->next_time = 0; 530 s->wait_for_sipi = 1; 531 } 532 533 static void apic_startup(APICState *s, int vector_num) 534 { 535 s->sipi_vector = vector_num; 536 cpu_interrupt(s->cpu_env, CPU_INTERRUPT_SIPI); 537 } 538 539 void apic_sipi(DeviceState *d) 540 { 541 APICState *s = DO_UPCAST(APICState, busdev.qdev, d); 542 543 cpu_reset_interrupt(s->cpu_env, CPU_INTERRUPT_SIPI); 544 545 if (!s->wait_for_sipi) 546 return; 547 cpu_x86_load_seg_cache_sipi(s->cpu_env, s->sipi_vector); 548 s->wait_for_sipi = 0; 549 } 550 551 static void apic_deliver(DeviceState *d, uint8_t dest, uint8_t dest_mode, 552 uint8_t delivery_mode, uint8_t vector_num, 553 uint8_t trigger_mode) 554 { 555 APICState *s = DO_UPCAST(APICState, busdev.qdev, d); 556 uint32_t deliver_bitmask[MAX_APIC_WORDS]; 557 int dest_shorthand = (s->icr[0] >> 18) & 3; 558 APICState *apic_iter; 559 560 switch (dest_shorthand) { 561 case 0: 562 apic_get_delivery_bitmask(deliver_bitmask, dest, dest_mode); 563 break; 564 case 1: 565 memset(deliver_bitmask, 0x00, sizeof(deliver_bitmask)); 566 set_bit(deliver_bitmask, s->idx); 567 break; 568 case 2: 569 memset(deliver_bitmask, 0xff, sizeof(deliver_bitmask)); 570 break; 571 case 3: 572 memset(deliver_bitmask, 0xff, sizeof(deliver_bitmask)); 573 reset_bit(deliver_bitmask, s->idx); 574 break; 575 } 576 577 switch (delivery_mode) { 578 case APIC_DM_INIT: 579 { 580 int trig_mode = (s->icr[0] >> 15) & 1; 581 int level = (s->icr[0] >> 14) & 1; 582 if (level == 0 && trig_mode == 1) { 583 foreach_apic(apic_iter, deliver_bitmask, 584 apic_iter->arb_id = apic_iter->id ); 585 return; 586 } 587 } 588 break; 589 590 case APIC_DM_SIPI: 591 foreach_apic(apic_iter, deliver_bitmask, 592 apic_startup(apic_iter, vector_num) ); 593 return; 594 } 595 596 apic_bus_deliver(deliver_bitmask, delivery_mode, vector_num, trigger_mode); 597 } 598 599 int apic_get_interrupt(DeviceState *d) 600 { 601 APICState *s = DO_UPCAST(APICState, busdev.qdev, d); 602 int intno; 603 604 /* if the APIC is installed or enabled, we let the 8259 handle the 605 IRQs */ 606 if (!s) 607 return -1; 608 if (!(s->spurious_vec & APIC_SV_ENABLE)) 609 return -1; 610 611 intno = apic_irq_pending(s); 612 613 if (intno == 0) { 614 return -1; 615 } else if (intno < 0) { 616 return s->spurious_vec & 0xff; 617 } 618 reset_bit(s->irr, intno); 619 set_bit(s->isr, intno); 620 apic_update_irq(s); 621 return intno; 622 } 623 624 int apic_accept_pic_intr(DeviceState *d) 625 { 626 APICState *s = DO_UPCAST(APICState, busdev.qdev, d); 627 uint32_t lvt0; 628 629 if (!s) 630 return -1; 631 632 lvt0 = s->lvt[APIC_LVT_LINT0]; 633 634 if ((s->apicbase & MSR_IA32_APICBASE_ENABLE) == 0 || 635 (lvt0 & APIC_LVT_MASKED) == 0) 636 return 1; 637 638 return 0; 639 } 640 641 static uint32_t apic_get_current_count(APICState *s) 642 { 643 int64_t d; 644 uint32_t val; 645 d = (qemu_get_clock_ns(vm_clock) - s->initial_count_load_time) >> 646 s->count_shift; 647 if (s->lvt[APIC_LVT_TIMER] & APIC_LVT_TIMER_PERIODIC) { 648 /* periodic */ 649 val = s->initial_count - (d % ((uint64_t)s->initial_count + 1)); 650 } else { 651 if (d >= s->initial_count) 652 val = 0; 653 else 654 val = s->initial_count - d; 655 } 656 return val; 657 } 658 659 static void apic_timer_update(APICState *s, int64_t current_time) 660 { 661 int64_t next_time, d; 662 663 if (!(s->lvt[APIC_LVT_TIMER] & APIC_LVT_MASKED)) { 664 d = (current_time - s->initial_count_load_time) >> 665 s->count_shift; 666 if (s->lvt[APIC_LVT_TIMER] & APIC_LVT_TIMER_PERIODIC) { 667 if (!s->initial_count) 668 goto no_timer; 669 d = ((d / ((uint64_t)s->initial_count + 1)) + 1) * ((uint64_t)s->initial_count + 1); 670 } else { 671 if (d >= s->initial_count) 672 goto no_timer; 673 d = (uint64_t)s->initial_count + 1; 674 } 675 next_time = s->initial_count_load_time + (d << s->count_shift); 676 qemu_mod_timer(s->timer, next_time); 677 s->next_time = next_time; 678 } else { 679 no_timer: 680 qemu_del_timer(s->timer); 681 } 682 } 683 684 static void apic_timer(void *opaque) 685 { 686 APICState *s = opaque; 687 688 apic_local_deliver(s, APIC_LVT_TIMER); 689 apic_timer_update(s, s->next_time); 690 } 691 692 static uint32_t apic_mem_readb(void *opaque, target_phys_addr_t addr) 693 { 694 return 0; 695 } 696 697 static uint32_t apic_mem_readw(void *opaque, target_phys_addr_t addr) 698 { 699 return 0; 700 } 701 702 static void apic_mem_writeb(void *opaque, target_phys_addr_t addr, uint32_t val) 703 { 704 } 705 706 static void apic_mem_writew(void *opaque, target_phys_addr_t addr, uint32_t val) 707 { 708 } 709 710 static uint32_t apic_mem_readl(void *opaque, target_phys_addr_t addr) 711 { 712 DeviceState *d; 713 APICState *s; 714 uint32_t val; 715 int index; 716 717 d = cpu_get_current_apic(); 718 if (!d) { 719 return 0; 720 } 721 s = DO_UPCAST(APICState, busdev.qdev, d); 722 723 index = (addr >> 4) & 0xff; 724 switch(index) { 725 case 0x02: /* id */ 726 val = s->id << 24; 727 break; 728 case 0x03: /* version */ 729 val = 0x11 | ((APIC_LVT_NB - 1) << 16); /* version 0x11 */ 730 break; 731 case 0x08: 732 val = s->tpr; 733 break; 734 case 0x09: 735 val = apic_get_arb_pri(s); 736 break; 737 case 0x0a: 738 /* ppr */ 739 val = apic_get_ppr(s); 740 break; 741 case 0x0b: 742 val = 0; 743 break; 744 case 0x0d: 745 val = s->log_dest << 24; 746 break; 747 case 0x0e: 748 val = s->dest_mode << 28; 749 break; 750 case 0x0f: 751 val = s->spurious_vec; 752 break; 753 case 0x10 ... 0x17: 754 val = s->isr[index & 7]; 755 break; 756 case 0x18 ... 0x1f: 757 val = s->tmr[index & 7]; 758 break; 759 case 0x20 ... 0x27: 760 val = s->irr[index & 7]; 761 break; 762 case 0x28: 763 val = s->esr; 764 break; 765 case 0x30: 766 case 0x31: 767 val = s->icr[index & 1]; 768 break; 769 case 0x32 ... 0x37: 770 val = s->lvt[index - 0x32]; 771 break; 772 case 0x38: 773 val = s->initial_count; 774 break; 775 case 0x39: 776 val = apic_get_current_count(s); 777 break; 778 case 0x3e: 779 val = s->divide_conf; 780 break; 781 default: 782 s->esr |= ESR_ILLEGAL_ADDRESS; 783 val = 0; 784 break; 785 } 786 trace_apic_mem_readl(addr, val); 787 return val; 788 } 789 790 static void apic_send_msi(target_phys_addr_t addr, uint32_t data) 791 { 792 uint8_t dest = (addr & MSI_ADDR_DEST_ID_MASK) >> MSI_ADDR_DEST_ID_SHIFT; 793 uint8_t vector = (data & MSI_DATA_VECTOR_MASK) >> MSI_DATA_VECTOR_SHIFT; 794 uint8_t dest_mode = (addr >> MSI_ADDR_DEST_MODE_SHIFT) & 0x1; 795 uint8_t trigger_mode = (data >> MSI_DATA_TRIGGER_SHIFT) & 0x1; 796 uint8_t delivery = (data >> MSI_DATA_DELIVERY_MODE_SHIFT) & 0x7; 797 /* XXX: Ignore redirection hint. */ 798 apic_deliver_irq(dest, dest_mode, delivery, vector, trigger_mode); 799 } 800 801 static void apic_mem_writel(void *opaque, target_phys_addr_t addr, uint32_t val) 802 { 803 DeviceState *d; 804 APICState *s; 805 int index = (addr >> 4) & 0xff; 806 if (addr > 0xfff || !index) { 807 /* MSI and MMIO APIC are at the same memory location, 808 * but actually not on the global bus: MSI is on PCI bus 809 * APIC is connected directly to the CPU. 810 * Mapping them on the global bus happens to work because 811 * MSI registers are reserved in APIC MMIO and vice versa. */ 812 apic_send_msi(addr, val); 813 return; 814 } 815 816 d = cpu_get_current_apic(); 817 if (!d) { 818 return; 819 } 820 s = DO_UPCAST(APICState, busdev.qdev, d); 821 822 trace_apic_mem_writel(addr, val); 823 824 switch(index) { 825 case 0x02: 826 s->id = (val >> 24); 827 break; 828 case 0x03: 829 break; 830 case 0x08: 831 s->tpr = val; 832 apic_update_irq(s); 833 break; 834 case 0x09: 835 case 0x0a: 836 break; 837 case 0x0b: /* EOI */ 838 apic_eoi(s); 839 break; 840 case 0x0d: 841 s->log_dest = val >> 24; 842 break; 843 case 0x0e: 844 s->dest_mode = val >> 28; 845 break; 846 case 0x0f: 847 s->spurious_vec = val & 0x1ff; 848 apic_update_irq(s); 849 break; 850 case 0x10 ... 0x17: 851 case 0x18 ... 0x1f: 852 case 0x20 ... 0x27: 853 case 0x28: 854 break; 855 case 0x30: 856 s->icr[0] = val; 857 apic_deliver(d, (s->icr[1] >> 24) & 0xff, (s->icr[0] >> 11) & 1, 858 (s->icr[0] >> 8) & 7, (s->icr[0] & 0xff), 859 (s->icr[0] >> 15) & 1); 860 break; 861 case 0x31: 862 s->icr[1] = val; 863 break; 864 case 0x32 ... 0x37: 865 { 866 int n = index - 0x32; 867 s->lvt[n] = val; 868 if (n == APIC_LVT_TIMER) 869 apic_timer_update(s, qemu_get_clock_ns(vm_clock)); 870 } 871 break; 872 case 0x38: 873 s->initial_count = val; 874 s->initial_count_load_time = qemu_get_clock_ns(vm_clock); 875 apic_timer_update(s, s->initial_count_load_time); 876 break; 877 case 0x39: 878 break; 879 case 0x3e: 880 { 881 int v; 882 s->divide_conf = val & 0xb; 883 v = (s->divide_conf & 3) | ((s->divide_conf >> 1) & 4); 884 s->count_shift = (v + 1) & 7; 885 } 886 break; 887 default: 888 s->esr |= ESR_ILLEGAL_ADDRESS; 889 break; 890 } 891 } 892 893 /* This function is only used for old state version 1 and 2 */ 894 static int apic_load_old(QEMUFile *f, void *opaque, int version_id) 895 { 896 APICState *s = opaque; 897 int i; 898 899 if (version_id > 2) 900 return -EINVAL; 901 902 /* XXX: what if the base changes? (registered memory regions) */ 903 qemu_get_be32s(f, &s->apicbase); 904 qemu_get_8s(f, &s->id); 905 qemu_get_8s(f, &s->arb_id); 906 qemu_get_8s(f, &s->tpr); 907 qemu_get_be32s(f, &s->spurious_vec); 908 qemu_get_8s(f, &s->log_dest); 909 qemu_get_8s(f, &s->dest_mode); 910 for (i = 0; i < 8; i++) { 911 qemu_get_be32s(f, &s->isr[i]); 912 qemu_get_be32s(f, &s->tmr[i]); 913 qemu_get_be32s(f, &s->irr[i]); 914 } 915 for (i = 0; i < APIC_LVT_NB; i++) { 916 qemu_get_be32s(f, &s->lvt[i]); 917 } 918 qemu_get_be32s(f, &s->esr); 919 qemu_get_be32s(f, &s->icr[0]); 920 qemu_get_be32s(f, &s->icr[1]); 921 qemu_get_be32s(f, &s->divide_conf); 922 s->count_shift=qemu_get_be32(f); 923 qemu_get_be32s(f, &s->initial_count); 924 s->initial_count_load_time=qemu_get_be64(f); 925 s->next_time=qemu_get_be64(f); 926 927 if (version_id >= 2) 928 qemu_get_timer(f, s->timer); 929 return 0; 930 } 931 932 static const VMStateDescription vmstate_apic = { 933 .name = "apic", 934 .version_id = 3, 935 .minimum_version_id = 3, 936 .minimum_version_id_old = 1, 937 .load_state_old = apic_load_old, 938 .fields = (VMStateField []) { 939 VMSTATE_UINT32(apicbase, APICState), 940 VMSTATE_UINT8(id, APICState), 941 VMSTATE_UINT8(arb_id, APICState), 942 VMSTATE_UINT8(tpr, APICState), 943 VMSTATE_UINT32(spurious_vec, APICState), 944 VMSTATE_UINT8(log_dest, APICState), 945 VMSTATE_UINT8(dest_mode, APICState), 946 VMSTATE_UINT32_ARRAY(isr, APICState, 8), 947 VMSTATE_UINT32_ARRAY(tmr, APICState, 8), 948 VMSTATE_UINT32_ARRAY(irr, APICState, 8), 949 VMSTATE_UINT32_ARRAY(lvt, APICState, APIC_LVT_NB), 950 VMSTATE_UINT32(esr, APICState), 951 VMSTATE_UINT32_ARRAY(icr, APICState, 2), 952 VMSTATE_UINT32(divide_conf, APICState), 953 VMSTATE_INT32(count_shift, APICState), 954 VMSTATE_UINT32(initial_count, APICState), 955 VMSTATE_INT64(initial_count_load_time, APICState), 956 VMSTATE_INT64(next_time, APICState), 957 VMSTATE_TIMER(timer, APICState), 958 VMSTATE_END_OF_LIST() 959 } 960 }; 961 962 static void apic_reset(DeviceState *d) 963 { 964 APICState *s = DO_UPCAST(APICState, busdev.qdev, d); 965 int bsp; 966 967 bsp = cpu_is_bsp(s->cpu_env); 968 s->apicbase = 0xfee00000 | 969 (bsp ? MSR_IA32_APICBASE_BSP : 0) | MSR_IA32_APICBASE_ENABLE; 970 971 apic_init_reset(d); 972 973 if (bsp) { 974 /* 975 * LINT0 delivery mode on CPU #0 is set to ExtInt at initialization 976 * time typically by BIOS, so PIC interrupt can be delivered to the 977 * processor when local APIC is enabled. 978 */ 979 s->lvt[APIC_LVT_LINT0] = 0x700; 980 } 981 } 982 983 static const MemoryRegionOps apic_io_ops = { 984 .old_mmio = { 985 .read = { apic_mem_readb, apic_mem_readw, apic_mem_readl, }, 986 .write = { apic_mem_writeb, apic_mem_writew, apic_mem_writel, }, 987 }, 988 .endianness = DEVICE_NATIVE_ENDIAN, 989 }; 990 991 static int apic_init1(SysBusDevice *dev) 992 { 993 APICState *s = FROM_SYSBUS(APICState, dev); 994 static int last_apic_idx; 995 996 if (last_apic_idx >= MAX_APICS) { 997 return -1; 998 } 999 memory_region_init_io(&s->io_memory, &apic_io_ops, s, "apic", 1000 MSI_ADDR_SIZE); 1001 sysbus_init_mmio_region(dev, &s->io_memory); 1002 1003 s->timer = qemu_new_timer_ns(vm_clock, apic_timer, s); 1004 s->idx = last_apic_idx++; 1005 local_apics[s->idx] = s; 1006 return 0; 1007 } 1008 1009 static SysBusDeviceInfo apic_info = { 1010 .init = apic_init1, 1011 .qdev.name = "apic", 1012 .qdev.size = sizeof(APICState), 1013 .qdev.vmsd = &vmstate_apic, 1014 .qdev.reset = apic_reset, 1015 .qdev.no_user = 1, 1016 .qdev.props = (Property[]) { 1017 DEFINE_PROP_UINT8("id", APICState, id, -1), 1018 DEFINE_PROP_PTR("cpu_env", APICState, cpu_env), 1019 DEFINE_PROP_END_OF_LIST(), 1020 } 1021 }; 1022 1023 static void apic_register_devices(void) 1024 { 1025 sysbus_register_withprop(&apic_info); 1026 } 1027 1028 device_init(apic_register_devices) 1029