xref: /qemu/hw/intc/apic.c (revision d34ca5901630dca45f105bbe1a80b51fbb8c4284)
1 /*
2  *  APIC support
3  *
4  *  Copyright (c) 2004-2005 Fabrice Bellard
5  *
6  * This library is free software; you can redistribute it and/or
7  * modify it under the terms of the GNU Lesser General Public
8  * License as published by the Free Software Foundation; either
9  * version 2 of the License, or (at your option) any later version.
10  *
11  * This library is distributed in the hope that it will be useful,
12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
14  * Lesser General Public License for more details.
15  *
16  * You should have received a copy of the GNU Lesser General Public
17  * License along with this library; if not, write to the Free Software
18  * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
19  */
20 #include "hw.h"
21 #include "pc.h"
22 #include "qemu-timer.h"
23 #include "host-utils.h"
24 
25 //#define DEBUG_APIC
26 //#define DEBUG_IOAPIC
27 
28 /* APIC Local Vector Table */
29 #define APIC_LVT_TIMER   0
30 #define APIC_LVT_THERMAL 1
31 #define APIC_LVT_PERFORM 2
32 #define APIC_LVT_LINT0   3
33 #define APIC_LVT_LINT1   4
34 #define APIC_LVT_ERROR   5
35 #define APIC_LVT_NB      6
36 
37 /* APIC delivery modes */
38 #define APIC_DM_FIXED	0
39 #define APIC_DM_LOWPRI	1
40 #define APIC_DM_SMI	2
41 #define APIC_DM_NMI	4
42 #define APIC_DM_INIT	5
43 #define APIC_DM_SIPI	6
44 #define APIC_DM_EXTINT	7
45 
46 /* APIC destination mode */
47 #define APIC_DESTMODE_FLAT	0xf
48 #define APIC_DESTMODE_CLUSTER	1
49 
50 #define APIC_TRIGGER_EDGE  0
51 #define APIC_TRIGGER_LEVEL 1
52 
53 #define	APIC_LVT_TIMER_PERIODIC		(1<<17)
54 #define	APIC_LVT_MASKED			(1<<16)
55 #define	APIC_LVT_LEVEL_TRIGGER		(1<<15)
56 #define	APIC_LVT_REMOTE_IRR		(1<<14)
57 #define	APIC_INPUT_POLARITY		(1<<13)
58 #define	APIC_SEND_PENDING		(1<<12)
59 
60 #define IOAPIC_NUM_PINS			0x18
61 
62 #define ESR_ILLEGAL_ADDRESS (1 << 7)
63 
64 #define APIC_SV_ENABLE (1 << 8)
65 
66 #define MAX_APICS 255
67 #define MAX_APIC_WORDS 8
68 
69 typedef struct APICState {
70     CPUState *cpu_env;
71     uint32_t apicbase;
72     uint8_t id;
73     uint8_t arb_id;
74     uint8_t tpr;
75     uint32_t spurious_vec;
76     uint8_t log_dest;
77     uint8_t dest_mode;
78     uint32_t isr[8];  /* in service register */
79     uint32_t tmr[8];  /* trigger mode register */
80     uint32_t irr[8]; /* interrupt request register */
81     uint32_t lvt[APIC_LVT_NB];
82     uint32_t esr; /* error register */
83     uint32_t icr[2];
84 
85     uint32_t divide_conf;
86     int count_shift;
87     uint32_t initial_count;
88     int64_t initial_count_load_time, next_time;
89     QEMUTimer *timer;
90 } APICState;
91 
92 struct IOAPICState {
93     uint8_t id;
94     uint8_t ioregsel;
95 
96     uint32_t irr;
97     uint64_t ioredtbl[IOAPIC_NUM_PINS];
98 };
99 
100 static int apic_io_memory;
101 static APICState *local_apics[MAX_APICS + 1];
102 static int last_apic_id = 0;
103 
104 static void apic_init_ipi(APICState *s);
105 static void apic_set_irq(APICState *s, int vector_num, int trigger_mode);
106 static void apic_update_irq(APICState *s);
107 
108 /* Find first bit starting from lsb */
109 static int ffs_bit(uint32_t value)
110 {
111     return ctz32(value);
112 }
113 
114 static inline void set_bit(uint32_t *tab, int index)
115 {
116     int i, mask;
117     i = index >> 5;
118     mask = 1 << (index & 0x1f);
119     tab[i] |= mask;
120 }
121 
122 static inline void reset_bit(uint32_t *tab, int index)
123 {
124     int i, mask;
125     i = index >> 5;
126     mask = 1 << (index & 0x1f);
127     tab[i] &= ~mask;
128 }
129 
130 static void apic_local_deliver(CPUState *env, int vector)
131 {
132     APICState *s = env->apic_state;
133     uint32_t lvt = s->lvt[vector];
134     int trigger_mode;
135 
136     if (lvt & APIC_LVT_MASKED)
137         return;
138 
139     switch ((lvt >> 8) & 7) {
140     case APIC_DM_SMI:
141         cpu_interrupt(env, CPU_INTERRUPT_SMI);
142         break;
143 
144     case APIC_DM_NMI:
145         cpu_interrupt(env, CPU_INTERRUPT_NMI);
146         break;
147 
148     case APIC_DM_EXTINT:
149         cpu_interrupt(env, CPU_INTERRUPT_HARD);
150         break;
151 
152     case APIC_DM_FIXED:
153         trigger_mode = APIC_TRIGGER_EDGE;
154         if ((vector == APIC_LVT_LINT0 || vector == APIC_LVT_LINT1) &&
155             (lvt & APIC_LVT_LEVEL_TRIGGER))
156             trigger_mode = APIC_TRIGGER_LEVEL;
157         apic_set_irq(s, lvt & 0xff, trigger_mode);
158     }
159 }
160 
161 void apic_deliver_pic_intr(CPUState *env, int level)
162 {
163     if (level)
164         apic_local_deliver(env, APIC_LVT_LINT0);
165     else {
166         APICState *s = env->apic_state;
167         uint32_t lvt = s->lvt[APIC_LVT_LINT0];
168 
169         switch ((lvt >> 8) & 7) {
170         case APIC_DM_FIXED:
171             if (!(lvt & APIC_LVT_LEVEL_TRIGGER))
172                 break;
173             reset_bit(s->irr, lvt & 0xff);
174             /* fall through */
175         case APIC_DM_EXTINT:
176             cpu_reset_interrupt(env, CPU_INTERRUPT_HARD);
177             break;
178         }
179     }
180 }
181 
182 #define foreach_apic(apic, deliver_bitmask, code) \
183 {\
184     int __i, __j, __mask;\
185     for(__i = 0; __i < MAX_APIC_WORDS; __i++) {\
186         __mask = deliver_bitmask[__i];\
187         if (__mask) {\
188             for(__j = 0; __j < 32; __j++) {\
189                 if (__mask & (1 << __j)) {\
190                     apic = local_apics[__i * 32 + __j];\
191                     if (apic) {\
192                         code;\
193                     }\
194                 }\
195             }\
196         }\
197     }\
198 }
199 
200 static void apic_bus_deliver(const uint32_t *deliver_bitmask,
201                              uint8_t delivery_mode,
202                              uint8_t vector_num, uint8_t polarity,
203                              uint8_t trigger_mode)
204 {
205     APICState *apic_iter;
206 
207     switch (delivery_mode) {
208         case APIC_DM_LOWPRI:
209             /* XXX: search for focus processor, arbitration */
210             {
211                 int i, d;
212                 d = -1;
213                 for(i = 0; i < MAX_APIC_WORDS; i++) {
214                     if (deliver_bitmask[i]) {
215                         d = i * 32 + ffs_bit(deliver_bitmask[i]);
216                         break;
217                     }
218                 }
219                 if (d >= 0) {
220                     apic_iter = local_apics[d];
221                     if (apic_iter) {
222                         apic_set_irq(apic_iter, vector_num, trigger_mode);
223                     }
224                 }
225             }
226             return;
227 
228         case APIC_DM_FIXED:
229             break;
230 
231         case APIC_DM_SMI:
232             foreach_apic(apic_iter, deliver_bitmask,
233                 cpu_interrupt(apic_iter->cpu_env, CPU_INTERRUPT_SMI) );
234             return;
235 
236         case APIC_DM_NMI:
237             foreach_apic(apic_iter, deliver_bitmask,
238                 cpu_interrupt(apic_iter->cpu_env, CPU_INTERRUPT_NMI) );
239             return;
240 
241         case APIC_DM_INIT:
242             /* normal INIT IPI sent to processors */
243             foreach_apic(apic_iter, deliver_bitmask,
244                          apic_init_ipi(apic_iter) );
245             return;
246 
247         case APIC_DM_EXTINT:
248             /* handled in I/O APIC code */
249             break;
250 
251         default:
252             return;
253     }
254 
255     foreach_apic(apic_iter, deliver_bitmask,
256                  apic_set_irq(apic_iter, vector_num, trigger_mode) );
257 }
258 
259 void cpu_set_apic_base(CPUState *env, uint64_t val)
260 {
261     APICState *s = env->apic_state;
262 #ifdef DEBUG_APIC
263     printf("cpu_set_apic_base: %016" PRIx64 "\n", val);
264 #endif
265     s->apicbase = (val & 0xfffff000) |
266         (s->apicbase & (MSR_IA32_APICBASE_BSP | MSR_IA32_APICBASE_ENABLE));
267     /* if disabled, cannot be enabled again */
268     if (!(val & MSR_IA32_APICBASE_ENABLE)) {
269         s->apicbase &= ~MSR_IA32_APICBASE_ENABLE;
270         env->cpuid_features &= ~CPUID_APIC;
271         s->spurious_vec &= ~APIC_SV_ENABLE;
272     }
273 }
274 
275 uint64_t cpu_get_apic_base(CPUState *env)
276 {
277     APICState *s = env->apic_state;
278 #ifdef DEBUG_APIC
279     printf("cpu_get_apic_base: %016" PRIx64 "\n", (uint64_t)s->apicbase);
280 #endif
281     return s->apicbase;
282 }
283 
284 void cpu_set_apic_tpr(CPUX86State *env, uint8_t val)
285 {
286     APICState *s = env->apic_state;
287     s->tpr = (val & 0x0f) << 4;
288     apic_update_irq(s);
289 }
290 
291 uint8_t cpu_get_apic_tpr(CPUX86State *env)
292 {
293     APICState *s = env->apic_state;
294     return s->tpr >> 4;
295 }
296 
297 /* return -1 if no bit is set */
298 static int get_highest_priority_int(uint32_t *tab)
299 {
300     int i;
301     for(i = 7; i >= 0; i--) {
302         if (tab[i] != 0) {
303             return i * 32 + fls(tab[i]);
304         }
305     }
306     return -1;
307 }
308 
309 static int apic_get_ppr(APICState *s)
310 {
311     int tpr, isrv, ppr;
312 
313     tpr = (s->tpr >> 4);
314     isrv = get_highest_priority_int(s->isr);
315     if (isrv < 0)
316         isrv = 0;
317     isrv >>= 4;
318     if (tpr >= isrv)
319         ppr = s->tpr;
320     else
321         ppr = isrv << 4;
322     return ppr;
323 }
324 
325 static int apic_get_arb_pri(APICState *s)
326 {
327     /* XXX: arbitration */
328     return 0;
329 }
330 
331 /* signal the CPU if an irq is pending */
332 static void apic_update_irq(APICState *s)
333 {
334     int irrv, ppr;
335     if (!(s->spurious_vec & APIC_SV_ENABLE))
336         return;
337     irrv = get_highest_priority_int(s->irr);
338     if (irrv < 0)
339         return;
340     ppr = apic_get_ppr(s);
341     if (ppr && (irrv & 0xf0) <= (ppr & 0xf0))
342         return;
343     cpu_interrupt(s->cpu_env, CPU_INTERRUPT_HARD);
344 }
345 
346 static void apic_set_irq(APICState *s, int vector_num, int trigger_mode)
347 {
348     set_bit(s->irr, vector_num);
349     if (trigger_mode)
350         set_bit(s->tmr, vector_num);
351     else
352         reset_bit(s->tmr, vector_num);
353     apic_update_irq(s);
354 }
355 
356 static void apic_eoi(APICState *s)
357 {
358     int isrv;
359     isrv = get_highest_priority_int(s->isr);
360     if (isrv < 0)
361         return;
362     reset_bit(s->isr, isrv);
363     /* XXX: send the EOI packet to the APIC bus to allow the I/O APIC to
364             set the remote IRR bit for level triggered interrupts. */
365     apic_update_irq(s);
366 }
367 
368 static void apic_get_delivery_bitmask(uint32_t *deliver_bitmask,
369                                       uint8_t dest, uint8_t dest_mode)
370 {
371     APICState *apic_iter;
372     int i;
373 
374     if (dest_mode == 0) {
375         if (dest == 0xff) {
376             memset(deliver_bitmask, 0xff, MAX_APIC_WORDS * sizeof(uint32_t));
377         } else {
378             memset(deliver_bitmask, 0x00, MAX_APIC_WORDS * sizeof(uint32_t));
379             set_bit(deliver_bitmask, dest);
380         }
381     } else {
382         /* XXX: cluster mode */
383         memset(deliver_bitmask, 0x00, MAX_APIC_WORDS * sizeof(uint32_t));
384         for(i = 0; i < MAX_APICS; i++) {
385             apic_iter = local_apics[i];
386             if (apic_iter) {
387                 if (apic_iter->dest_mode == 0xf) {
388                     if (dest & apic_iter->log_dest)
389                         set_bit(deliver_bitmask, i);
390                 } else if (apic_iter->dest_mode == 0x0) {
391                     if ((dest & 0xf0) == (apic_iter->log_dest & 0xf0) &&
392                         (dest & apic_iter->log_dest & 0x0f)) {
393                         set_bit(deliver_bitmask, i);
394                     }
395                 }
396             }
397         }
398     }
399 }
400 
401 
402 static void apic_init_ipi(APICState *s)
403 {
404     int i;
405 
406     s->tpr = 0;
407     s->spurious_vec = 0xff;
408     s->log_dest = 0;
409     s->dest_mode = 0xf;
410     memset(s->isr, 0, sizeof(s->isr));
411     memset(s->tmr, 0, sizeof(s->tmr));
412     memset(s->irr, 0, sizeof(s->irr));
413     for(i = 0; i < APIC_LVT_NB; i++)
414         s->lvt[i] = 1 << 16; /* mask LVT */
415     s->esr = 0;
416     memset(s->icr, 0, sizeof(s->icr));
417     s->divide_conf = 0;
418     s->count_shift = 0;
419     s->initial_count = 0;
420     s->initial_count_load_time = 0;
421     s->next_time = 0;
422 
423     cpu_reset(s->cpu_env);
424 
425     if (!(s->apicbase & MSR_IA32_APICBASE_BSP))
426         s->cpu_env->halted = 1;
427 }
428 
429 /* send a SIPI message to the CPU to start it */
430 static void apic_startup(APICState *s, int vector_num)
431 {
432     CPUState *env = s->cpu_env;
433     if (!env->halted)
434         return;
435     env->eip = 0;
436     cpu_x86_load_seg_cache(env, R_CS, vector_num << 8, vector_num << 12,
437                            0xffff, 0);
438     env->halted = 0;
439 }
440 
441 static void apic_deliver(APICState *s, uint8_t dest, uint8_t dest_mode,
442                          uint8_t delivery_mode, uint8_t vector_num,
443                          uint8_t polarity, uint8_t trigger_mode)
444 {
445     uint32_t deliver_bitmask[MAX_APIC_WORDS];
446     int dest_shorthand = (s->icr[0] >> 18) & 3;
447     APICState *apic_iter;
448 
449     switch (dest_shorthand) {
450     case 0:
451         apic_get_delivery_bitmask(deliver_bitmask, dest, dest_mode);
452         break;
453     case 1:
454         memset(deliver_bitmask, 0x00, sizeof(deliver_bitmask));
455         set_bit(deliver_bitmask, s->id);
456         break;
457     case 2:
458         memset(deliver_bitmask, 0xff, sizeof(deliver_bitmask));
459         break;
460     case 3:
461         memset(deliver_bitmask, 0xff, sizeof(deliver_bitmask));
462         reset_bit(deliver_bitmask, s->id);
463         break;
464     }
465 
466     switch (delivery_mode) {
467         case APIC_DM_INIT:
468             {
469                 int trig_mode = (s->icr[0] >> 15) & 1;
470                 int level = (s->icr[0] >> 14) & 1;
471                 if (level == 0 && trig_mode == 1) {
472                     foreach_apic(apic_iter, deliver_bitmask,
473                                  apic_iter->arb_id = apic_iter->id );
474                     return;
475                 }
476             }
477             break;
478 
479         case APIC_DM_SIPI:
480             foreach_apic(apic_iter, deliver_bitmask,
481                          apic_startup(apic_iter, vector_num) );
482             return;
483     }
484 
485     apic_bus_deliver(deliver_bitmask, delivery_mode, vector_num, polarity,
486                      trigger_mode);
487 }
488 
489 int apic_get_interrupt(CPUState *env)
490 {
491     APICState *s = env->apic_state;
492     int intno;
493 
494     /* if the APIC is installed or enabled, we let the 8259 handle the
495        IRQs */
496     if (!s)
497         return -1;
498     if (!(s->spurious_vec & APIC_SV_ENABLE))
499         return -1;
500 
501     /* XXX: spurious IRQ handling */
502     intno = get_highest_priority_int(s->irr);
503     if (intno < 0)
504         return -1;
505     if (s->tpr && intno <= s->tpr)
506         return s->spurious_vec & 0xff;
507     reset_bit(s->irr, intno);
508     set_bit(s->isr, intno);
509     apic_update_irq(s);
510     return intno;
511 }
512 
513 int apic_accept_pic_intr(CPUState *env)
514 {
515     APICState *s = env->apic_state;
516     uint32_t lvt0;
517 
518     if (!s)
519         return -1;
520 
521     lvt0 = s->lvt[APIC_LVT_LINT0];
522 
523     if ((s->apicbase & MSR_IA32_APICBASE_ENABLE) == 0 ||
524         (lvt0 & APIC_LVT_MASKED) == 0)
525         return 1;
526 
527     return 0;
528 }
529 
530 static uint32_t apic_get_current_count(APICState *s)
531 {
532     int64_t d;
533     uint32_t val;
534     d = (qemu_get_clock(vm_clock) - s->initial_count_load_time) >>
535         s->count_shift;
536     if (s->lvt[APIC_LVT_TIMER] & APIC_LVT_TIMER_PERIODIC) {
537         /* periodic */
538         val = s->initial_count - (d % ((uint64_t)s->initial_count + 1));
539     } else {
540         if (d >= s->initial_count)
541             val = 0;
542         else
543             val = s->initial_count - d;
544     }
545     return val;
546 }
547 
548 static void apic_timer_update(APICState *s, int64_t current_time)
549 {
550     int64_t next_time, d;
551 
552     if (!(s->lvt[APIC_LVT_TIMER] & APIC_LVT_MASKED)) {
553         d = (current_time - s->initial_count_load_time) >>
554             s->count_shift;
555         if (s->lvt[APIC_LVT_TIMER] & APIC_LVT_TIMER_PERIODIC) {
556             if (!s->initial_count)
557                 goto no_timer;
558             d = ((d / ((uint64_t)s->initial_count + 1)) + 1) * ((uint64_t)s->initial_count + 1);
559         } else {
560             if (d >= s->initial_count)
561                 goto no_timer;
562             d = (uint64_t)s->initial_count + 1;
563         }
564         next_time = s->initial_count_load_time + (d << s->count_shift);
565         qemu_mod_timer(s->timer, next_time);
566         s->next_time = next_time;
567     } else {
568     no_timer:
569         qemu_del_timer(s->timer);
570     }
571 }
572 
573 static void apic_timer(void *opaque)
574 {
575     APICState *s = opaque;
576 
577     apic_local_deliver(s->cpu_env, APIC_LVT_TIMER);
578     apic_timer_update(s, s->next_time);
579 }
580 
581 static uint32_t apic_mem_readb(void *opaque, target_phys_addr_t addr)
582 {
583     return 0;
584 }
585 
586 static uint32_t apic_mem_readw(void *opaque, target_phys_addr_t addr)
587 {
588     return 0;
589 }
590 
591 static void apic_mem_writeb(void *opaque, target_phys_addr_t addr, uint32_t val)
592 {
593 }
594 
595 static void apic_mem_writew(void *opaque, target_phys_addr_t addr, uint32_t val)
596 {
597 }
598 
599 static uint32_t apic_mem_readl(void *opaque, target_phys_addr_t addr)
600 {
601     CPUState *env;
602     APICState *s;
603     uint32_t val;
604     int index;
605 
606     env = cpu_single_env;
607     if (!env)
608         return 0;
609     s = env->apic_state;
610 
611     index = (addr >> 4) & 0xff;
612     switch(index) {
613     case 0x02: /* id */
614         val = s->id << 24;
615         break;
616     case 0x03: /* version */
617         val = 0x11 | ((APIC_LVT_NB - 1) << 16); /* version 0x11 */
618         break;
619     case 0x08:
620         val = s->tpr;
621         break;
622     case 0x09:
623         val = apic_get_arb_pri(s);
624         break;
625     case 0x0a:
626         /* ppr */
627         val = apic_get_ppr(s);
628         break;
629     case 0x0b:
630         val = 0;
631         break;
632     case 0x0d:
633         val = s->log_dest << 24;
634         break;
635     case 0x0e:
636         val = s->dest_mode << 28;
637         break;
638     case 0x0f:
639         val = s->spurious_vec;
640         break;
641     case 0x10 ... 0x17:
642         val = s->isr[index & 7];
643         break;
644     case 0x18 ... 0x1f:
645         val = s->tmr[index & 7];
646         break;
647     case 0x20 ... 0x27:
648         val = s->irr[index & 7];
649         break;
650     case 0x28:
651         val = s->esr;
652         break;
653     case 0x30:
654     case 0x31:
655         val = s->icr[index & 1];
656         break;
657     case 0x32 ... 0x37:
658         val = s->lvt[index - 0x32];
659         break;
660     case 0x38:
661         val = s->initial_count;
662         break;
663     case 0x39:
664         val = apic_get_current_count(s);
665         break;
666     case 0x3e:
667         val = s->divide_conf;
668         break;
669     default:
670         s->esr |= ESR_ILLEGAL_ADDRESS;
671         val = 0;
672         break;
673     }
674 #ifdef DEBUG_APIC
675     printf("APIC read: %08x = %08x\n", (uint32_t)addr, val);
676 #endif
677     return val;
678 }
679 
680 static void apic_mem_writel(void *opaque, target_phys_addr_t addr, uint32_t val)
681 {
682     CPUState *env;
683     APICState *s;
684     int index;
685 
686     env = cpu_single_env;
687     if (!env)
688         return;
689     s = env->apic_state;
690 
691 #ifdef DEBUG_APIC
692     printf("APIC write: %08x = %08x\n", (uint32_t)addr, val);
693 #endif
694 
695     index = (addr >> 4) & 0xff;
696     switch(index) {
697     case 0x02:
698         s->id = (val >> 24);
699         break;
700     case 0x03:
701         break;
702     case 0x08:
703         s->tpr = val;
704         apic_update_irq(s);
705         break;
706     case 0x09:
707     case 0x0a:
708         break;
709     case 0x0b: /* EOI */
710         apic_eoi(s);
711         break;
712     case 0x0d:
713         s->log_dest = val >> 24;
714         break;
715     case 0x0e:
716         s->dest_mode = val >> 28;
717         break;
718     case 0x0f:
719         s->spurious_vec = val & 0x1ff;
720         apic_update_irq(s);
721         break;
722     case 0x10 ... 0x17:
723     case 0x18 ... 0x1f:
724     case 0x20 ... 0x27:
725     case 0x28:
726         break;
727     case 0x30:
728         s->icr[0] = val;
729         apic_deliver(s, (s->icr[1] >> 24) & 0xff, (s->icr[0] >> 11) & 1,
730                      (s->icr[0] >> 8) & 7, (s->icr[0] & 0xff),
731                      (s->icr[0] >> 14) & 1, (s->icr[0] >> 15) & 1);
732         break;
733     case 0x31:
734         s->icr[1] = val;
735         break;
736     case 0x32 ... 0x37:
737         {
738             int n = index - 0x32;
739             s->lvt[n] = val;
740             if (n == APIC_LVT_TIMER)
741                 apic_timer_update(s, qemu_get_clock(vm_clock));
742         }
743         break;
744     case 0x38:
745         s->initial_count = val;
746         s->initial_count_load_time = qemu_get_clock(vm_clock);
747         apic_timer_update(s, s->initial_count_load_time);
748         break;
749     case 0x39:
750         break;
751     case 0x3e:
752         {
753             int v;
754             s->divide_conf = val & 0xb;
755             v = (s->divide_conf & 3) | ((s->divide_conf >> 1) & 4);
756             s->count_shift = (v + 1) & 7;
757         }
758         break;
759     default:
760         s->esr |= ESR_ILLEGAL_ADDRESS;
761         break;
762     }
763 }
764 
765 static void apic_save(QEMUFile *f, void *opaque)
766 {
767     APICState *s = opaque;
768     int i;
769 
770     qemu_put_be32s(f, &s->apicbase);
771     qemu_put_8s(f, &s->id);
772     qemu_put_8s(f, &s->arb_id);
773     qemu_put_8s(f, &s->tpr);
774     qemu_put_be32s(f, &s->spurious_vec);
775     qemu_put_8s(f, &s->log_dest);
776     qemu_put_8s(f, &s->dest_mode);
777     for (i = 0; i < 8; i++) {
778         qemu_put_be32s(f, &s->isr[i]);
779         qemu_put_be32s(f, &s->tmr[i]);
780         qemu_put_be32s(f, &s->irr[i]);
781     }
782     for (i = 0; i < APIC_LVT_NB; i++) {
783         qemu_put_be32s(f, &s->lvt[i]);
784     }
785     qemu_put_be32s(f, &s->esr);
786     qemu_put_be32s(f, &s->icr[0]);
787     qemu_put_be32s(f, &s->icr[1]);
788     qemu_put_be32s(f, &s->divide_conf);
789     qemu_put_be32(f, s->count_shift);
790     qemu_put_be32s(f, &s->initial_count);
791     qemu_put_be64(f, s->initial_count_load_time);
792     qemu_put_be64(f, s->next_time);
793 
794     qemu_put_timer(f, s->timer);
795 }
796 
797 static int apic_load(QEMUFile *f, void *opaque, int version_id)
798 {
799     APICState *s = opaque;
800     int i;
801 
802     if (version_id > 2)
803         return -EINVAL;
804 
805     /* XXX: what if the base changes? (registered memory regions) */
806     qemu_get_be32s(f, &s->apicbase);
807     qemu_get_8s(f, &s->id);
808     qemu_get_8s(f, &s->arb_id);
809     qemu_get_8s(f, &s->tpr);
810     qemu_get_be32s(f, &s->spurious_vec);
811     qemu_get_8s(f, &s->log_dest);
812     qemu_get_8s(f, &s->dest_mode);
813     for (i = 0; i < 8; i++) {
814         qemu_get_be32s(f, &s->isr[i]);
815         qemu_get_be32s(f, &s->tmr[i]);
816         qemu_get_be32s(f, &s->irr[i]);
817     }
818     for (i = 0; i < APIC_LVT_NB; i++) {
819         qemu_get_be32s(f, &s->lvt[i]);
820     }
821     qemu_get_be32s(f, &s->esr);
822     qemu_get_be32s(f, &s->icr[0]);
823     qemu_get_be32s(f, &s->icr[1]);
824     qemu_get_be32s(f, &s->divide_conf);
825     s->count_shift=qemu_get_be32(f);
826     qemu_get_be32s(f, &s->initial_count);
827     s->initial_count_load_time=qemu_get_be64(f);
828     s->next_time=qemu_get_be64(f);
829 
830     if (version_id >= 2)
831         qemu_get_timer(f, s->timer);
832     return 0;
833 }
834 
835 static void apic_reset(void *opaque)
836 {
837     APICState *s = opaque;
838 
839     s->apicbase = 0xfee00000 |
840         (s->id ? 0 : MSR_IA32_APICBASE_BSP) | MSR_IA32_APICBASE_ENABLE;
841 
842     apic_init_ipi(s);
843 
844     if (s->id == 0) {
845         /*
846          * LINT0 delivery mode on CPU #0 is set to ExtInt at initialization
847          * time typically by BIOS, so PIC interrupt can be delivered to the
848          * processor when local APIC is enabled.
849          */
850         s->lvt[APIC_LVT_LINT0] = 0x700;
851     }
852 }
853 
854 static CPUReadMemoryFunc *apic_mem_read[3] = {
855     apic_mem_readb,
856     apic_mem_readw,
857     apic_mem_readl,
858 };
859 
860 static CPUWriteMemoryFunc *apic_mem_write[3] = {
861     apic_mem_writeb,
862     apic_mem_writew,
863     apic_mem_writel,
864 };
865 
866 int apic_init(CPUState *env)
867 {
868     APICState *s;
869 
870     if (last_apic_id >= MAX_APICS)
871         return -1;
872     s = qemu_mallocz(sizeof(APICState));
873     if (!s)
874         return -1;
875     env->apic_state = s;
876     s->id = last_apic_id++;
877     env->cpuid_apic_id = s->id;
878     s->cpu_env = env;
879 
880     apic_reset(s);
881 
882     /* XXX: mapping more APICs at the same memory location */
883     if (apic_io_memory == 0) {
884         /* NOTE: the APIC is directly connected to the CPU - it is not
885            on the global memory bus. */
886         apic_io_memory = cpu_register_io_memory(0, apic_mem_read,
887                                                 apic_mem_write, NULL);
888         cpu_register_physical_memory(s->apicbase & ~0xfff, 0x1000,
889                                      apic_io_memory);
890     }
891     s->timer = qemu_new_timer(vm_clock, apic_timer, s);
892 
893     register_savevm("apic", s->id, 2, apic_save, apic_load, s);
894     qemu_register_reset(apic_reset, s);
895 
896     local_apics[s->id] = s;
897     return 0;
898 }
899 
900 static void ioapic_service(IOAPICState *s)
901 {
902     uint8_t i;
903     uint8_t trig_mode;
904     uint8_t vector;
905     uint8_t delivery_mode;
906     uint32_t mask;
907     uint64_t entry;
908     uint8_t dest;
909     uint8_t dest_mode;
910     uint8_t polarity;
911     uint32_t deliver_bitmask[MAX_APIC_WORDS];
912 
913     for (i = 0; i < IOAPIC_NUM_PINS; i++) {
914         mask = 1 << i;
915         if (s->irr & mask) {
916             entry = s->ioredtbl[i];
917             if (!(entry & APIC_LVT_MASKED)) {
918                 trig_mode = ((entry >> 15) & 1);
919                 dest = entry >> 56;
920                 dest_mode = (entry >> 11) & 1;
921                 delivery_mode = (entry >> 8) & 7;
922                 polarity = (entry >> 13) & 1;
923                 if (trig_mode == APIC_TRIGGER_EDGE)
924                     s->irr &= ~mask;
925                 if (delivery_mode == APIC_DM_EXTINT)
926                     vector = pic_read_irq(isa_pic);
927                 else
928                     vector = entry & 0xff;
929 
930                 apic_get_delivery_bitmask(deliver_bitmask, dest, dest_mode);
931                 apic_bus_deliver(deliver_bitmask, delivery_mode,
932                                  vector, polarity, trig_mode);
933             }
934         }
935     }
936 }
937 
938 void ioapic_set_irq(void *opaque, int vector, int level)
939 {
940     IOAPICState *s = opaque;
941 
942     if (vector >= 0 && vector < IOAPIC_NUM_PINS) {
943         uint32_t mask = 1 << vector;
944         uint64_t entry = s->ioredtbl[vector];
945 
946         if ((entry >> 15) & 1) {
947             /* level triggered */
948             if (level) {
949                 s->irr |= mask;
950                 ioapic_service(s);
951             } else {
952                 s->irr &= ~mask;
953             }
954         } else {
955             /* edge triggered */
956             if (level) {
957                 s->irr |= mask;
958                 ioapic_service(s);
959             }
960         }
961     }
962 }
963 
964 static uint32_t ioapic_mem_readl(void *opaque, target_phys_addr_t addr)
965 {
966     IOAPICState *s = opaque;
967     int index;
968     uint32_t val = 0;
969 
970     addr &= 0xff;
971     if (addr == 0x00) {
972         val = s->ioregsel;
973     } else if (addr == 0x10) {
974         switch (s->ioregsel) {
975             case 0x00:
976                 val = s->id << 24;
977                 break;
978             case 0x01:
979                 val = 0x11 | ((IOAPIC_NUM_PINS - 1) << 16); /* version 0x11 */
980                 break;
981             case 0x02:
982                 val = 0;
983                 break;
984             default:
985                 index = (s->ioregsel - 0x10) >> 1;
986                 if (index >= 0 && index < IOAPIC_NUM_PINS) {
987                     if (s->ioregsel & 1)
988                         val = s->ioredtbl[index] >> 32;
989                     else
990                         val = s->ioredtbl[index] & 0xffffffff;
991                 }
992         }
993 #ifdef DEBUG_IOAPIC
994         printf("I/O APIC read: %08x = %08x\n", s->ioregsel, val);
995 #endif
996     }
997     return val;
998 }
999 
1000 static void ioapic_mem_writel(void *opaque, target_phys_addr_t addr, uint32_t val)
1001 {
1002     IOAPICState *s = opaque;
1003     int index;
1004 
1005     addr &= 0xff;
1006     if (addr == 0x00)  {
1007         s->ioregsel = val;
1008         return;
1009     } else if (addr == 0x10) {
1010 #ifdef DEBUG_IOAPIC
1011         printf("I/O APIC write: %08x = %08x\n", s->ioregsel, val);
1012 #endif
1013         switch (s->ioregsel) {
1014             case 0x00:
1015                 s->id = (val >> 24) & 0xff;
1016                 return;
1017             case 0x01:
1018             case 0x02:
1019                 return;
1020             default:
1021                 index = (s->ioregsel - 0x10) >> 1;
1022                 if (index >= 0 && index < IOAPIC_NUM_PINS) {
1023                     if (s->ioregsel & 1) {
1024                         s->ioredtbl[index] &= 0xffffffff;
1025                         s->ioredtbl[index] |= (uint64_t)val << 32;
1026                     } else {
1027                         s->ioredtbl[index] &= ~0xffffffffULL;
1028                         s->ioredtbl[index] |= val;
1029                     }
1030                     ioapic_service(s);
1031                 }
1032         }
1033     }
1034 }
1035 
1036 static void ioapic_save(QEMUFile *f, void *opaque)
1037 {
1038     IOAPICState *s = opaque;
1039     int i;
1040 
1041     qemu_put_8s(f, &s->id);
1042     qemu_put_8s(f, &s->ioregsel);
1043     for (i = 0; i < IOAPIC_NUM_PINS; i++) {
1044         qemu_put_be64s(f, &s->ioredtbl[i]);
1045     }
1046 }
1047 
1048 static int ioapic_load(QEMUFile *f, void *opaque, int version_id)
1049 {
1050     IOAPICState *s = opaque;
1051     int i;
1052 
1053     if (version_id != 1)
1054         return -EINVAL;
1055 
1056     qemu_get_8s(f, &s->id);
1057     qemu_get_8s(f, &s->ioregsel);
1058     for (i = 0; i < IOAPIC_NUM_PINS; i++) {
1059         qemu_get_be64s(f, &s->ioredtbl[i]);
1060     }
1061     return 0;
1062 }
1063 
1064 static void ioapic_reset(void *opaque)
1065 {
1066     IOAPICState *s = opaque;
1067     int i;
1068 
1069     memset(s, 0, sizeof(*s));
1070     for(i = 0; i < IOAPIC_NUM_PINS; i++)
1071         s->ioredtbl[i] = 1 << 16; /* mask LVT */
1072 }
1073 
1074 static CPUReadMemoryFunc *ioapic_mem_read[3] = {
1075     ioapic_mem_readl,
1076     ioapic_mem_readl,
1077     ioapic_mem_readl,
1078 };
1079 
1080 static CPUWriteMemoryFunc *ioapic_mem_write[3] = {
1081     ioapic_mem_writel,
1082     ioapic_mem_writel,
1083     ioapic_mem_writel,
1084 };
1085 
1086 IOAPICState *ioapic_init(void)
1087 {
1088     IOAPICState *s;
1089     int io_memory;
1090 
1091     s = qemu_mallocz(sizeof(IOAPICState));
1092     if (!s)
1093         return NULL;
1094     ioapic_reset(s);
1095     s->id = last_apic_id++;
1096 
1097     io_memory = cpu_register_io_memory(0, ioapic_mem_read,
1098                                        ioapic_mem_write, s);
1099     cpu_register_physical_memory(0xfec00000, 0x1000, io_memory);
1100 
1101     register_savevm("ioapic", 0, 1, ioapic_save, ioapic_load, s);
1102     qemu_register_reset(ioapic_reset, s);
1103 
1104     return s;
1105 }
1106