1 /* 2 * APIC support 3 * 4 * Copyright (c) 2004-2005 Fabrice Bellard 5 * 6 * This library is free software; you can redistribute it and/or 7 * modify it under the terms of the GNU Lesser General Public 8 * License as published by the Free Software Foundation; either 9 * version 2 of the License, or (at your option) any later version. 10 * 11 * This library is distributed in the hope that it will be useful, 12 * but WITHOUT ANY WARRANTY; without even the implied warranty of 13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 14 * Lesser General Public License for more details. 15 * 16 * You should have received a copy of the GNU Lesser General Public 17 * License along with this library; if not, write to the Free Software 18 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston MA 02110-1301 USA 19 */ 20 #include "hw.h" 21 #include "pc.h" 22 #include "qemu-timer.h" 23 #include "host-utils.h" 24 25 //#define DEBUG_APIC 26 27 /* APIC Local Vector Table */ 28 #define APIC_LVT_TIMER 0 29 #define APIC_LVT_THERMAL 1 30 #define APIC_LVT_PERFORM 2 31 #define APIC_LVT_LINT0 3 32 #define APIC_LVT_LINT1 4 33 #define APIC_LVT_ERROR 5 34 #define APIC_LVT_NB 6 35 36 /* APIC delivery modes */ 37 #define APIC_DM_FIXED 0 38 #define APIC_DM_LOWPRI 1 39 #define APIC_DM_SMI 2 40 #define APIC_DM_NMI 4 41 #define APIC_DM_INIT 5 42 #define APIC_DM_SIPI 6 43 #define APIC_DM_EXTINT 7 44 45 /* APIC destination mode */ 46 #define APIC_DESTMODE_FLAT 0xf 47 #define APIC_DESTMODE_CLUSTER 1 48 49 #define APIC_TRIGGER_EDGE 0 50 #define APIC_TRIGGER_LEVEL 1 51 52 #define APIC_LVT_TIMER_PERIODIC (1<<17) 53 #define APIC_LVT_MASKED (1<<16) 54 #define APIC_LVT_LEVEL_TRIGGER (1<<15) 55 #define APIC_LVT_REMOTE_IRR (1<<14) 56 #define APIC_INPUT_POLARITY (1<<13) 57 #define APIC_SEND_PENDING (1<<12) 58 59 #define ESR_ILLEGAL_ADDRESS (1 << 7) 60 61 #define APIC_SV_ENABLE (1 << 8) 62 63 #define MAX_APICS 255 64 #define MAX_APIC_WORDS 8 65 66 typedef struct APICState { 67 CPUState *cpu_env; 68 uint32_t apicbase; 69 uint8_t id; 70 uint8_t arb_id; 71 uint8_t tpr; 72 uint32_t spurious_vec; 73 uint8_t log_dest; 74 uint8_t dest_mode; 75 uint32_t isr[8]; /* in service register */ 76 uint32_t tmr[8]; /* trigger mode register */ 77 uint32_t irr[8]; /* interrupt request register */ 78 uint32_t lvt[APIC_LVT_NB]; 79 uint32_t esr; /* error register */ 80 uint32_t icr[2]; 81 82 uint32_t divide_conf; 83 int count_shift; 84 uint32_t initial_count; 85 int64_t initial_count_load_time, next_time; 86 QEMUTimer *timer; 87 } APICState; 88 89 static int apic_io_memory; 90 static APICState *local_apics[MAX_APICS + 1]; 91 static int last_apic_id = 0; 92 static int apic_irq_delivered; 93 94 95 static void apic_init_ipi(APICState *s); 96 static void apic_set_irq(APICState *s, int vector_num, int trigger_mode); 97 static void apic_update_irq(APICState *s); 98 static void apic_get_delivery_bitmask(uint32_t *deliver_bitmask, 99 uint8_t dest, uint8_t dest_mode); 100 101 /* Find first bit starting from msb */ 102 static int fls_bit(uint32_t value) 103 { 104 return 31 - clz32(value); 105 } 106 107 /* Find first bit starting from lsb */ 108 static int ffs_bit(uint32_t value) 109 { 110 return ctz32(value); 111 } 112 113 static inline void set_bit(uint32_t *tab, int index) 114 { 115 int i, mask; 116 i = index >> 5; 117 mask = 1 << (index & 0x1f); 118 tab[i] |= mask; 119 } 120 121 static inline void reset_bit(uint32_t *tab, int index) 122 { 123 int i, mask; 124 i = index >> 5; 125 mask = 1 << (index & 0x1f); 126 tab[i] &= ~mask; 127 } 128 129 static inline int get_bit(uint32_t *tab, int index) 130 { 131 int i, mask; 132 i = index >> 5; 133 mask = 1 << (index & 0x1f); 134 return !!(tab[i] & mask); 135 } 136 137 static void apic_local_deliver(CPUState *env, int vector) 138 { 139 APICState *s = env->apic_state; 140 uint32_t lvt = s->lvt[vector]; 141 int trigger_mode; 142 143 if (lvt & APIC_LVT_MASKED) 144 return; 145 146 switch ((lvt >> 8) & 7) { 147 case APIC_DM_SMI: 148 cpu_interrupt(env, CPU_INTERRUPT_SMI); 149 break; 150 151 case APIC_DM_NMI: 152 cpu_interrupt(env, CPU_INTERRUPT_NMI); 153 break; 154 155 case APIC_DM_EXTINT: 156 cpu_interrupt(env, CPU_INTERRUPT_HARD); 157 break; 158 159 case APIC_DM_FIXED: 160 trigger_mode = APIC_TRIGGER_EDGE; 161 if ((vector == APIC_LVT_LINT0 || vector == APIC_LVT_LINT1) && 162 (lvt & APIC_LVT_LEVEL_TRIGGER)) 163 trigger_mode = APIC_TRIGGER_LEVEL; 164 apic_set_irq(s, lvt & 0xff, trigger_mode); 165 } 166 } 167 168 void apic_deliver_pic_intr(CPUState *env, int level) 169 { 170 if (level) 171 apic_local_deliver(env, APIC_LVT_LINT0); 172 else { 173 APICState *s = env->apic_state; 174 uint32_t lvt = s->lvt[APIC_LVT_LINT0]; 175 176 switch ((lvt >> 8) & 7) { 177 case APIC_DM_FIXED: 178 if (!(lvt & APIC_LVT_LEVEL_TRIGGER)) 179 break; 180 reset_bit(s->irr, lvt & 0xff); 181 /* fall through */ 182 case APIC_DM_EXTINT: 183 cpu_reset_interrupt(env, CPU_INTERRUPT_HARD); 184 break; 185 } 186 } 187 } 188 189 #define foreach_apic(apic, deliver_bitmask, code) \ 190 {\ 191 int __i, __j, __mask;\ 192 for(__i = 0; __i < MAX_APIC_WORDS; __i++) {\ 193 __mask = deliver_bitmask[__i];\ 194 if (__mask) {\ 195 for(__j = 0; __j < 32; __j++) {\ 196 if (__mask & (1 << __j)) {\ 197 apic = local_apics[__i * 32 + __j];\ 198 if (apic) {\ 199 code;\ 200 }\ 201 }\ 202 }\ 203 }\ 204 }\ 205 } 206 207 static void apic_bus_deliver(const uint32_t *deliver_bitmask, 208 uint8_t delivery_mode, 209 uint8_t vector_num, uint8_t polarity, 210 uint8_t trigger_mode) 211 { 212 APICState *apic_iter; 213 214 switch (delivery_mode) { 215 case APIC_DM_LOWPRI: 216 /* XXX: search for focus processor, arbitration */ 217 { 218 int i, d; 219 d = -1; 220 for(i = 0; i < MAX_APIC_WORDS; i++) { 221 if (deliver_bitmask[i]) { 222 d = i * 32 + ffs_bit(deliver_bitmask[i]); 223 break; 224 } 225 } 226 if (d >= 0) { 227 apic_iter = local_apics[d]; 228 if (apic_iter) { 229 apic_set_irq(apic_iter, vector_num, trigger_mode); 230 } 231 } 232 } 233 return; 234 235 case APIC_DM_FIXED: 236 break; 237 238 case APIC_DM_SMI: 239 foreach_apic(apic_iter, deliver_bitmask, 240 cpu_interrupt(apic_iter->cpu_env, CPU_INTERRUPT_SMI) ); 241 return; 242 243 case APIC_DM_NMI: 244 foreach_apic(apic_iter, deliver_bitmask, 245 cpu_interrupt(apic_iter->cpu_env, CPU_INTERRUPT_NMI) ); 246 return; 247 248 case APIC_DM_INIT: 249 /* normal INIT IPI sent to processors */ 250 foreach_apic(apic_iter, deliver_bitmask, 251 apic_init_ipi(apic_iter) ); 252 return; 253 254 case APIC_DM_EXTINT: 255 /* handled in I/O APIC code */ 256 break; 257 258 default: 259 return; 260 } 261 262 foreach_apic(apic_iter, deliver_bitmask, 263 apic_set_irq(apic_iter, vector_num, trigger_mode) ); 264 } 265 266 void apic_deliver_irq(uint8_t dest, uint8_t dest_mode, 267 uint8_t delivery_mode, uint8_t vector_num, 268 uint8_t polarity, uint8_t trigger_mode) 269 { 270 uint32_t deliver_bitmask[MAX_APIC_WORDS]; 271 272 apic_get_delivery_bitmask(deliver_bitmask, dest, dest_mode); 273 apic_bus_deliver(deliver_bitmask, delivery_mode, vector_num, polarity, 274 trigger_mode); 275 } 276 277 void cpu_set_apic_base(CPUState *env, uint64_t val) 278 { 279 APICState *s = env->apic_state; 280 #ifdef DEBUG_APIC 281 printf("cpu_set_apic_base: %016" PRIx64 "\n", val); 282 #endif 283 if (!s) 284 return; 285 s->apicbase = (val & 0xfffff000) | 286 (s->apicbase & (MSR_IA32_APICBASE_BSP | MSR_IA32_APICBASE_ENABLE)); 287 /* if disabled, cannot be enabled again */ 288 if (!(val & MSR_IA32_APICBASE_ENABLE)) { 289 s->apicbase &= ~MSR_IA32_APICBASE_ENABLE; 290 env->cpuid_features &= ~CPUID_APIC; 291 s->spurious_vec &= ~APIC_SV_ENABLE; 292 } 293 } 294 295 uint64_t cpu_get_apic_base(CPUState *env) 296 { 297 APICState *s = env->apic_state; 298 #ifdef DEBUG_APIC 299 printf("cpu_get_apic_base: %016" PRIx64 "\n", 300 s ? (uint64_t)s->apicbase: 0); 301 #endif 302 return s ? s->apicbase : 0; 303 } 304 305 void cpu_set_apic_tpr(CPUX86State *env, uint8_t val) 306 { 307 APICState *s = env->apic_state; 308 if (!s) 309 return; 310 s->tpr = (val & 0x0f) << 4; 311 apic_update_irq(s); 312 } 313 314 uint8_t cpu_get_apic_tpr(CPUX86State *env) 315 { 316 APICState *s = env->apic_state; 317 return s ? s->tpr >> 4 : 0; 318 } 319 320 /* return -1 if no bit is set */ 321 static int get_highest_priority_int(uint32_t *tab) 322 { 323 int i; 324 for(i = 7; i >= 0; i--) { 325 if (tab[i] != 0) { 326 return i * 32 + fls_bit(tab[i]); 327 } 328 } 329 return -1; 330 } 331 332 static int apic_get_ppr(APICState *s) 333 { 334 int tpr, isrv, ppr; 335 336 tpr = (s->tpr >> 4); 337 isrv = get_highest_priority_int(s->isr); 338 if (isrv < 0) 339 isrv = 0; 340 isrv >>= 4; 341 if (tpr >= isrv) 342 ppr = s->tpr; 343 else 344 ppr = isrv << 4; 345 return ppr; 346 } 347 348 static int apic_get_arb_pri(APICState *s) 349 { 350 /* XXX: arbitration */ 351 return 0; 352 } 353 354 /* signal the CPU if an irq is pending */ 355 static void apic_update_irq(APICState *s) 356 { 357 int irrv, ppr; 358 if (!(s->spurious_vec & APIC_SV_ENABLE)) 359 return; 360 irrv = get_highest_priority_int(s->irr); 361 if (irrv < 0) 362 return; 363 ppr = apic_get_ppr(s); 364 if (ppr && (irrv & 0xf0) <= (ppr & 0xf0)) 365 return; 366 cpu_interrupt(s->cpu_env, CPU_INTERRUPT_HARD); 367 } 368 369 void apic_reset_irq_delivered(void) 370 { 371 apic_irq_delivered = 0; 372 } 373 374 int apic_get_irq_delivered(void) 375 { 376 return apic_irq_delivered; 377 } 378 379 static void apic_set_irq(APICState *s, int vector_num, int trigger_mode) 380 { 381 apic_irq_delivered += !get_bit(s->irr, vector_num); 382 383 set_bit(s->irr, vector_num); 384 if (trigger_mode) 385 set_bit(s->tmr, vector_num); 386 else 387 reset_bit(s->tmr, vector_num); 388 apic_update_irq(s); 389 } 390 391 static void apic_eoi(APICState *s) 392 { 393 int isrv; 394 isrv = get_highest_priority_int(s->isr); 395 if (isrv < 0) 396 return; 397 reset_bit(s->isr, isrv); 398 /* XXX: send the EOI packet to the APIC bus to allow the I/O APIC to 399 set the remote IRR bit for level triggered interrupts. */ 400 apic_update_irq(s); 401 } 402 403 static void apic_get_delivery_bitmask(uint32_t *deliver_bitmask, 404 uint8_t dest, uint8_t dest_mode) 405 { 406 APICState *apic_iter; 407 int i; 408 409 if (dest_mode == 0) { 410 if (dest == 0xff) { 411 memset(deliver_bitmask, 0xff, MAX_APIC_WORDS * sizeof(uint32_t)); 412 } else { 413 memset(deliver_bitmask, 0x00, MAX_APIC_WORDS * sizeof(uint32_t)); 414 set_bit(deliver_bitmask, dest); 415 } 416 } else { 417 /* XXX: cluster mode */ 418 memset(deliver_bitmask, 0x00, MAX_APIC_WORDS * sizeof(uint32_t)); 419 for(i = 0; i < MAX_APICS; i++) { 420 apic_iter = local_apics[i]; 421 if (apic_iter) { 422 if (apic_iter->dest_mode == 0xf) { 423 if (dest & apic_iter->log_dest) 424 set_bit(deliver_bitmask, i); 425 } else if (apic_iter->dest_mode == 0x0) { 426 if ((dest & 0xf0) == (apic_iter->log_dest & 0xf0) && 427 (dest & apic_iter->log_dest & 0x0f)) { 428 set_bit(deliver_bitmask, i); 429 } 430 } 431 } 432 } 433 } 434 } 435 436 437 static void apic_init_ipi(APICState *s) 438 { 439 int i; 440 441 s->tpr = 0; 442 s->spurious_vec = 0xff; 443 s->log_dest = 0; 444 s->dest_mode = 0xf; 445 memset(s->isr, 0, sizeof(s->isr)); 446 memset(s->tmr, 0, sizeof(s->tmr)); 447 memset(s->irr, 0, sizeof(s->irr)); 448 for(i = 0; i < APIC_LVT_NB; i++) 449 s->lvt[i] = 1 << 16; /* mask LVT */ 450 s->esr = 0; 451 memset(s->icr, 0, sizeof(s->icr)); 452 s->divide_conf = 0; 453 s->count_shift = 0; 454 s->initial_count = 0; 455 s->initial_count_load_time = 0; 456 s->next_time = 0; 457 458 cpu_reset(s->cpu_env); 459 460 if (!(s->apicbase & MSR_IA32_APICBASE_BSP)) 461 s->cpu_env->halted = 1; 462 } 463 464 /* send a SIPI message to the CPU to start it */ 465 static void apic_startup(APICState *s, int vector_num) 466 { 467 CPUState *env = s->cpu_env; 468 if (!env->halted) 469 return; 470 env->eip = 0; 471 cpu_x86_load_seg_cache(env, R_CS, vector_num << 8, vector_num << 12, 472 0xffff, 0); 473 env->halted = 0; 474 } 475 476 static void apic_deliver(APICState *s, uint8_t dest, uint8_t dest_mode, 477 uint8_t delivery_mode, uint8_t vector_num, 478 uint8_t polarity, uint8_t trigger_mode) 479 { 480 uint32_t deliver_bitmask[MAX_APIC_WORDS]; 481 int dest_shorthand = (s->icr[0] >> 18) & 3; 482 APICState *apic_iter; 483 484 switch (dest_shorthand) { 485 case 0: 486 apic_get_delivery_bitmask(deliver_bitmask, dest, dest_mode); 487 break; 488 case 1: 489 memset(deliver_bitmask, 0x00, sizeof(deliver_bitmask)); 490 set_bit(deliver_bitmask, s->id); 491 break; 492 case 2: 493 memset(deliver_bitmask, 0xff, sizeof(deliver_bitmask)); 494 break; 495 case 3: 496 memset(deliver_bitmask, 0xff, sizeof(deliver_bitmask)); 497 reset_bit(deliver_bitmask, s->id); 498 break; 499 } 500 501 switch (delivery_mode) { 502 case APIC_DM_INIT: 503 { 504 int trig_mode = (s->icr[0] >> 15) & 1; 505 int level = (s->icr[0] >> 14) & 1; 506 if (level == 0 && trig_mode == 1) { 507 foreach_apic(apic_iter, deliver_bitmask, 508 apic_iter->arb_id = apic_iter->id ); 509 return; 510 } 511 } 512 break; 513 514 case APIC_DM_SIPI: 515 foreach_apic(apic_iter, deliver_bitmask, 516 apic_startup(apic_iter, vector_num) ); 517 return; 518 } 519 520 apic_bus_deliver(deliver_bitmask, delivery_mode, vector_num, polarity, 521 trigger_mode); 522 } 523 524 int apic_get_interrupt(CPUState *env) 525 { 526 APICState *s = env->apic_state; 527 int intno; 528 529 /* if the APIC is installed or enabled, we let the 8259 handle the 530 IRQs */ 531 if (!s) 532 return -1; 533 if (!(s->spurious_vec & APIC_SV_ENABLE)) 534 return -1; 535 536 /* XXX: spurious IRQ handling */ 537 intno = get_highest_priority_int(s->irr); 538 if (intno < 0) 539 return -1; 540 if (s->tpr && intno <= s->tpr) 541 return s->spurious_vec & 0xff; 542 reset_bit(s->irr, intno); 543 set_bit(s->isr, intno); 544 apic_update_irq(s); 545 return intno; 546 } 547 548 int apic_accept_pic_intr(CPUState *env) 549 { 550 APICState *s = env->apic_state; 551 uint32_t lvt0; 552 553 if (!s) 554 return -1; 555 556 lvt0 = s->lvt[APIC_LVT_LINT0]; 557 558 if ((s->apicbase & MSR_IA32_APICBASE_ENABLE) == 0 || 559 (lvt0 & APIC_LVT_MASKED) == 0) 560 return 1; 561 562 return 0; 563 } 564 565 static uint32_t apic_get_current_count(APICState *s) 566 { 567 int64_t d; 568 uint32_t val; 569 d = (qemu_get_clock(vm_clock) - s->initial_count_load_time) >> 570 s->count_shift; 571 if (s->lvt[APIC_LVT_TIMER] & APIC_LVT_TIMER_PERIODIC) { 572 /* periodic */ 573 val = s->initial_count - (d % ((uint64_t)s->initial_count + 1)); 574 } else { 575 if (d >= s->initial_count) 576 val = 0; 577 else 578 val = s->initial_count - d; 579 } 580 return val; 581 } 582 583 static void apic_timer_update(APICState *s, int64_t current_time) 584 { 585 int64_t next_time, d; 586 587 if (!(s->lvt[APIC_LVT_TIMER] & APIC_LVT_MASKED)) { 588 d = (current_time - s->initial_count_load_time) >> 589 s->count_shift; 590 if (s->lvt[APIC_LVT_TIMER] & APIC_LVT_TIMER_PERIODIC) { 591 if (!s->initial_count) 592 goto no_timer; 593 d = ((d / ((uint64_t)s->initial_count + 1)) + 1) * ((uint64_t)s->initial_count + 1); 594 } else { 595 if (d >= s->initial_count) 596 goto no_timer; 597 d = (uint64_t)s->initial_count + 1; 598 } 599 next_time = s->initial_count_load_time + (d << s->count_shift); 600 qemu_mod_timer(s->timer, next_time); 601 s->next_time = next_time; 602 } else { 603 no_timer: 604 qemu_del_timer(s->timer); 605 } 606 } 607 608 static void apic_timer(void *opaque) 609 { 610 APICState *s = opaque; 611 612 apic_local_deliver(s->cpu_env, APIC_LVT_TIMER); 613 apic_timer_update(s, s->next_time); 614 } 615 616 static uint32_t apic_mem_readb(void *opaque, target_phys_addr_t addr) 617 { 618 return 0; 619 } 620 621 static uint32_t apic_mem_readw(void *opaque, target_phys_addr_t addr) 622 { 623 return 0; 624 } 625 626 static void apic_mem_writeb(void *opaque, target_phys_addr_t addr, uint32_t val) 627 { 628 } 629 630 static void apic_mem_writew(void *opaque, target_phys_addr_t addr, uint32_t val) 631 { 632 } 633 634 static uint32_t apic_mem_readl(void *opaque, target_phys_addr_t addr) 635 { 636 CPUState *env; 637 APICState *s; 638 uint32_t val; 639 int index; 640 641 env = cpu_single_env; 642 if (!env) 643 return 0; 644 s = env->apic_state; 645 646 index = (addr >> 4) & 0xff; 647 switch(index) { 648 case 0x02: /* id */ 649 val = s->id << 24; 650 break; 651 case 0x03: /* version */ 652 val = 0x11 | ((APIC_LVT_NB - 1) << 16); /* version 0x11 */ 653 break; 654 case 0x08: 655 val = s->tpr; 656 break; 657 case 0x09: 658 val = apic_get_arb_pri(s); 659 break; 660 case 0x0a: 661 /* ppr */ 662 val = apic_get_ppr(s); 663 break; 664 case 0x0b: 665 val = 0; 666 break; 667 case 0x0d: 668 val = s->log_dest << 24; 669 break; 670 case 0x0e: 671 val = s->dest_mode << 28; 672 break; 673 case 0x0f: 674 val = s->spurious_vec; 675 break; 676 case 0x10 ... 0x17: 677 val = s->isr[index & 7]; 678 break; 679 case 0x18 ... 0x1f: 680 val = s->tmr[index & 7]; 681 break; 682 case 0x20 ... 0x27: 683 val = s->irr[index & 7]; 684 break; 685 case 0x28: 686 val = s->esr; 687 break; 688 case 0x30: 689 case 0x31: 690 val = s->icr[index & 1]; 691 break; 692 case 0x32 ... 0x37: 693 val = s->lvt[index - 0x32]; 694 break; 695 case 0x38: 696 val = s->initial_count; 697 break; 698 case 0x39: 699 val = apic_get_current_count(s); 700 break; 701 case 0x3e: 702 val = s->divide_conf; 703 break; 704 default: 705 s->esr |= ESR_ILLEGAL_ADDRESS; 706 val = 0; 707 break; 708 } 709 #ifdef DEBUG_APIC 710 printf("APIC read: %08x = %08x\n", (uint32_t)addr, val); 711 #endif 712 return val; 713 } 714 715 static void apic_mem_writel(void *opaque, target_phys_addr_t addr, uint32_t val) 716 { 717 CPUState *env; 718 APICState *s; 719 int index; 720 721 env = cpu_single_env; 722 if (!env) 723 return; 724 s = env->apic_state; 725 726 #ifdef DEBUG_APIC 727 printf("APIC write: %08x = %08x\n", (uint32_t)addr, val); 728 #endif 729 730 index = (addr >> 4) & 0xff; 731 switch(index) { 732 case 0x02: 733 s->id = (val >> 24); 734 break; 735 case 0x03: 736 break; 737 case 0x08: 738 s->tpr = val; 739 apic_update_irq(s); 740 break; 741 case 0x09: 742 case 0x0a: 743 break; 744 case 0x0b: /* EOI */ 745 apic_eoi(s); 746 break; 747 case 0x0d: 748 s->log_dest = val >> 24; 749 break; 750 case 0x0e: 751 s->dest_mode = val >> 28; 752 break; 753 case 0x0f: 754 s->spurious_vec = val & 0x1ff; 755 apic_update_irq(s); 756 break; 757 case 0x10 ... 0x17: 758 case 0x18 ... 0x1f: 759 case 0x20 ... 0x27: 760 case 0x28: 761 break; 762 case 0x30: 763 s->icr[0] = val; 764 apic_deliver(s, (s->icr[1] >> 24) & 0xff, (s->icr[0] >> 11) & 1, 765 (s->icr[0] >> 8) & 7, (s->icr[0] & 0xff), 766 (s->icr[0] >> 14) & 1, (s->icr[0] >> 15) & 1); 767 break; 768 case 0x31: 769 s->icr[1] = val; 770 break; 771 case 0x32 ... 0x37: 772 { 773 int n = index - 0x32; 774 s->lvt[n] = val; 775 if (n == APIC_LVT_TIMER) 776 apic_timer_update(s, qemu_get_clock(vm_clock)); 777 } 778 break; 779 case 0x38: 780 s->initial_count = val; 781 s->initial_count_load_time = qemu_get_clock(vm_clock); 782 apic_timer_update(s, s->initial_count_load_time); 783 break; 784 case 0x39: 785 break; 786 case 0x3e: 787 { 788 int v; 789 s->divide_conf = val & 0xb; 790 v = (s->divide_conf & 3) | ((s->divide_conf >> 1) & 4); 791 s->count_shift = (v + 1) & 7; 792 } 793 break; 794 default: 795 s->esr |= ESR_ILLEGAL_ADDRESS; 796 break; 797 } 798 } 799 800 static void apic_save(QEMUFile *f, void *opaque) 801 { 802 APICState *s = opaque; 803 int i; 804 805 qemu_put_be32s(f, &s->apicbase); 806 qemu_put_8s(f, &s->id); 807 qemu_put_8s(f, &s->arb_id); 808 qemu_put_8s(f, &s->tpr); 809 qemu_put_be32s(f, &s->spurious_vec); 810 qemu_put_8s(f, &s->log_dest); 811 qemu_put_8s(f, &s->dest_mode); 812 for (i = 0; i < 8; i++) { 813 qemu_put_be32s(f, &s->isr[i]); 814 qemu_put_be32s(f, &s->tmr[i]); 815 qemu_put_be32s(f, &s->irr[i]); 816 } 817 for (i = 0; i < APIC_LVT_NB; i++) { 818 qemu_put_be32s(f, &s->lvt[i]); 819 } 820 qemu_put_be32s(f, &s->esr); 821 qemu_put_be32s(f, &s->icr[0]); 822 qemu_put_be32s(f, &s->icr[1]); 823 qemu_put_be32s(f, &s->divide_conf); 824 qemu_put_be32(f, s->count_shift); 825 qemu_put_be32s(f, &s->initial_count); 826 qemu_put_be64(f, s->initial_count_load_time); 827 qemu_put_be64(f, s->next_time); 828 829 qemu_put_timer(f, s->timer); 830 } 831 832 static int apic_load(QEMUFile *f, void *opaque, int version_id) 833 { 834 APICState *s = opaque; 835 int i; 836 837 if (version_id > 2) 838 return -EINVAL; 839 840 /* XXX: what if the base changes? (registered memory regions) */ 841 qemu_get_be32s(f, &s->apicbase); 842 qemu_get_8s(f, &s->id); 843 qemu_get_8s(f, &s->arb_id); 844 qemu_get_8s(f, &s->tpr); 845 qemu_get_be32s(f, &s->spurious_vec); 846 qemu_get_8s(f, &s->log_dest); 847 qemu_get_8s(f, &s->dest_mode); 848 for (i = 0; i < 8; i++) { 849 qemu_get_be32s(f, &s->isr[i]); 850 qemu_get_be32s(f, &s->tmr[i]); 851 qemu_get_be32s(f, &s->irr[i]); 852 } 853 for (i = 0; i < APIC_LVT_NB; i++) { 854 qemu_get_be32s(f, &s->lvt[i]); 855 } 856 qemu_get_be32s(f, &s->esr); 857 qemu_get_be32s(f, &s->icr[0]); 858 qemu_get_be32s(f, &s->icr[1]); 859 qemu_get_be32s(f, &s->divide_conf); 860 s->count_shift=qemu_get_be32(f); 861 qemu_get_be32s(f, &s->initial_count); 862 s->initial_count_load_time=qemu_get_be64(f); 863 s->next_time=qemu_get_be64(f); 864 865 if (version_id >= 2) 866 qemu_get_timer(f, s->timer); 867 return 0; 868 } 869 870 static void apic_reset(void *opaque) 871 { 872 APICState *s = opaque; 873 874 s->apicbase = 0xfee00000 | 875 (s->id ? 0 : MSR_IA32_APICBASE_BSP) | MSR_IA32_APICBASE_ENABLE; 876 877 apic_init_ipi(s); 878 879 if (s->id == 0) { 880 /* 881 * LINT0 delivery mode on CPU #0 is set to ExtInt at initialization 882 * time typically by BIOS, so PIC interrupt can be delivered to the 883 * processor when local APIC is enabled. 884 */ 885 s->lvt[APIC_LVT_LINT0] = 0x700; 886 } 887 } 888 889 static CPUReadMemoryFunc *apic_mem_read[3] = { 890 apic_mem_readb, 891 apic_mem_readw, 892 apic_mem_readl, 893 }; 894 895 static CPUWriteMemoryFunc *apic_mem_write[3] = { 896 apic_mem_writeb, 897 apic_mem_writew, 898 apic_mem_writel, 899 }; 900 901 int apic_init(CPUState *env) 902 { 903 APICState *s; 904 905 if (last_apic_id >= MAX_APICS) 906 return -1; 907 s = qemu_mallocz(sizeof(APICState)); 908 env->apic_state = s; 909 s->id = last_apic_id++; 910 env->cpuid_apic_id = s->id; 911 s->cpu_env = env; 912 913 apic_reset(s); 914 915 /* XXX: mapping more APICs at the same memory location */ 916 if (apic_io_memory == 0) { 917 /* NOTE: the APIC is directly connected to the CPU - it is not 918 on the global memory bus. */ 919 apic_io_memory = cpu_register_io_memory(0, apic_mem_read, 920 apic_mem_write, NULL); 921 cpu_register_physical_memory(s->apicbase & ~0xfff, 0x1000, 922 apic_io_memory); 923 } 924 s->timer = qemu_new_timer(vm_clock, apic_timer, s); 925 926 register_savevm("apic", s->id, 2, apic_save, apic_load, s); 927 qemu_register_reset(apic_reset, s); 928 929 local_apics[s->id] = s; 930 return 0; 931 } 932 933