1 /* 2 * APIC support 3 * 4 * Copyright (c) 2004-2005 Fabrice Bellard 5 * 6 * This library is free software; you can redistribute it and/or 7 * modify it under the terms of the GNU Lesser General Public 8 * License as published by the Free Software Foundation; either 9 * version 2 of the License, or (at your option) any later version. 10 * 11 * This library is distributed in the hope that it will be useful, 12 * but WITHOUT ANY WARRANTY; without even the implied warranty of 13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 14 * Lesser General Public License for more details. 15 * 16 * You should have received a copy of the GNU Lesser General Public 17 * License along with this library; if not, write to the Free Software 18 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston MA 02110-1301 USA 19 */ 20 #include "hw.h" 21 #include "pc.h" 22 #include "qemu-timer.h" 23 #include "host-utils.h" 24 25 //#define DEBUG_APIC 26 27 /* APIC Local Vector Table */ 28 #define APIC_LVT_TIMER 0 29 #define APIC_LVT_THERMAL 1 30 #define APIC_LVT_PERFORM 2 31 #define APIC_LVT_LINT0 3 32 #define APIC_LVT_LINT1 4 33 #define APIC_LVT_ERROR 5 34 #define APIC_LVT_NB 6 35 36 /* APIC delivery modes */ 37 #define APIC_DM_FIXED 0 38 #define APIC_DM_LOWPRI 1 39 #define APIC_DM_SMI 2 40 #define APIC_DM_NMI 4 41 #define APIC_DM_INIT 5 42 #define APIC_DM_SIPI 6 43 #define APIC_DM_EXTINT 7 44 45 /* APIC destination mode */ 46 #define APIC_DESTMODE_FLAT 0xf 47 #define APIC_DESTMODE_CLUSTER 1 48 49 #define APIC_TRIGGER_EDGE 0 50 #define APIC_TRIGGER_LEVEL 1 51 52 #define APIC_LVT_TIMER_PERIODIC (1<<17) 53 #define APIC_LVT_MASKED (1<<16) 54 #define APIC_LVT_LEVEL_TRIGGER (1<<15) 55 #define APIC_LVT_REMOTE_IRR (1<<14) 56 #define APIC_INPUT_POLARITY (1<<13) 57 #define APIC_SEND_PENDING (1<<12) 58 59 #define ESR_ILLEGAL_ADDRESS (1 << 7) 60 61 #define APIC_SV_ENABLE (1 << 8) 62 63 #define MAX_APICS 255 64 #define MAX_APIC_WORDS 8 65 66 typedef struct APICState { 67 CPUState *cpu_env; 68 uint32_t apicbase; 69 uint8_t id; 70 uint8_t arb_id; 71 uint8_t tpr; 72 uint32_t spurious_vec; 73 uint8_t log_dest; 74 uint8_t dest_mode; 75 uint32_t isr[8]; /* in service register */ 76 uint32_t tmr[8]; /* trigger mode register */ 77 uint32_t irr[8]; /* interrupt request register */ 78 uint32_t lvt[APIC_LVT_NB]; 79 uint32_t esr; /* error register */ 80 uint32_t icr[2]; 81 82 uint32_t divide_conf; 83 int count_shift; 84 uint32_t initial_count; 85 int64_t initial_count_load_time, next_time; 86 uint32_t idx; 87 QEMUTimer *timer; 88 } APICState; 89 90 static int apic_io_memory; 91 static APICState *local_apics[MAX_APICS + 1]; 92 static int last_apic_idx = 0; 93 static int apic_irq_delivered; 94 95 96 static void apic_init_ipi(APICState *s); 97 static void apic_set_irq(APICState *s, int vector_num, int trigger_mode); 98 static void apic_update_irq(APICState *s); 99 static void apic_get_delivery_bitmask(uint32_t *deliver_bitmask, 100 uint8_t dest, uint8_t dest_mode); 101 102 /* Find first bit starting from msb */ 103 static int fls_bit(uint32_t value) 104 { 105 return 31 - clz32(value); 106 } 107 108 /* Find first bit starting from lsb */ 109 static int ffs_bit(uint32_t value) 110 { 111 return ctz32(value); 112 } 113 114 static inline void set_bit(uint32_t *tab, int index) 115 { 116 int i, mask; 117 i = index >> 5; 118 mask = 1 << (index & 0x1f); 119 tab[i] |= mask; 120 } 121 122 static inline void reset_bit(uint32_t *tab, int index) 123 { 124 int i, mask; 125 i = index >> 5; 126 mask = 1 << (index & 0x1f); 127 tab[i] &= ~mask; 128 } 129 130 static inline int get_bit(uint32_t *tab, int index) 131 { 132 int i, mask; 133 i = index >> 5; 134 mask = 1 << (index & 0x1f); 135 return !!(tab[i] & mask); 136 } 137 138 static void apic_local_deliver(CPUState *env, int vector) 139 { 140 APICState *s = env->apic_state; 141 uint32_t lvt = s->lvt[vector]; 142 int trigger_mode; 143 144 if (lvt & APIC_LVT_MASKED) 145 return; 146 147 switch ((lvt >> 8) & 7) { 148 case APIC_DM_SMI: 149 cpu_interrupt(env, CPU_INTERRUPT_SMI); 150 break; 151 152 case APIC_DM_NMI: 153 cpu_interrupt(env, CPU_INTERRUPT_NMI); 154 break; 155 156 case APIC_DM_EXTINT: 157 cpu_interrupt(env, CPU_INTERRUPT_HARD); 158 break; 159 160 case APIC_DM_FIXED: 161 trigger_mode = APIC_TRIGGER_EDGE; 162 if ((vector == APIC_LVT_LINT0 || vector == APIC_LVT_LINT1) && 163 (lvt & APIC_LVT_LEVEL_TRIGGER)) 164 trigger_mode = APIC_TRIGGER_LEVEL; 165 apic_set_irq(s, lvt & 0xff, trigger_mode); 166 } 167 } 168 169 void apic_deliver_pic_intr(CPUState *env, int level) 170 { 171 if (level) 172 apic_local_deliver(env, APIC_LVT_LINT0); 173 else { 174 APICState *s = env->apic_state; 175 uint32_t lvt = s->lvt[APIC_LVT_LINT0]; 176 177 switch ((lvt >> 8) & 7) { 178 case APIC_DM_FIXED: 179 if (!(lvt & APIC_LVT_LEVEL_TRIGGER)) 180 break; 181 reset_bit(s->irr, lvt & 0xff); 182 /* fall through */ 183 case APIC_DM_EXTINT: 184 cpu_reset_interrupt(env, CPU_INTERRUPT_HARD); 185 break; 186 } 187 } 188 } 189 190 #define foreach_apic(apic, deliver_bitmask, code) \ 191 {\ 192 int __i, __j, __mask;\ 193 for(__i = 0; __i < MAX_APIC_WORDS; __i++) {\ 194 __mask = deliver_bitmask[__i];\ 195 if (__mask) {\ 196 for(__j = 0; __j < 32; __j++) {\ 197 if (__mask & (1 << __j)) {\ 198 apic = local_apics[__i * 32 + __j];\ 199 if (apic) {\ 200 code;\ 201 }\ 202 }\ 203 }\ 204 }\ 205 }\ 206 } 207 208 static void apic_bus_deliver(const uint32_t *deliver_bitmask, 209 uint8_t delivery_mode, 210 uint8_t vector_num, uint8_t polarity, 211 uint8_t trigger_mode) 212 { 213 APICState *apic_iter; 214 215 switch (delivery_mode) { 216 case APIC_DM_LOWPRI: 217 /* XXX: search for focus processor, arbitration */ 218 { 219 int i, d; 220 d = -1; 221 for(i = 0; i < MAX_APIC_WORDS; i++) { 222 if (deliver_bitmask[i]) { 223 d = i * 32 + ffs_bit(deliver_bitmask[i]); 224 break; 225 } 226 } 227 if (d >= 0) { 228 apic_iter = local_apics[d]; 229 if (apic_iter) { 230 apic_set_irq(apic_iter, vector_num, trigger_mode); 231 } 232 } 233 } 234 return; 235 236 case APIC_DM_FIXED: 237 break; 238 239 case APIC_DM_SMI: 240 foreach_apic(apic_iter, deliver_bitmask, 241 cpu_interrupt(apic_iter->cpu_env, CPU_INTERRUPT_SMI) ); 242 return; 243 244 case APIC_DM_NMI: 245 foreach_apic(apic_iter, deliver_bitmask, 246 cpu_interrupt(apic_iter->cpu_env, CPU_INTERRUPT_NMI) ); 247 return; 248 249 case APIC_DM_INIT: 250 /* normal INIT IPI sent to processors */ 251 foreach_apic(apic_iter, deliver_bitmask, 252 apic_init_ipi(apic_iter) ); 253 return; 254 255 case APIC_DM_EXTINT: 256 /* handled in I/O APIC code */ 257 break; 258 259 default: 260 return; 261 } 262 263 foreach_apic(apic_iter, deliver_bitmask, 264 apic_set_irq(apic_iter, vector_num, trigger_mode) ); 265 } 266 267 void apic_deliver_irq(uint8_t dest, uint8_t dest_mode, 268 uint8_t delivery_mode, uint8_t vector_num, 269 uint8_t polarity, uint8_t trigger_mode) 270 { 271 uint32_t deliver_bitmask[MAX_APIC_WORDS]; 272 273 apic_get_delivery_bitmask(deliver_bitmask, dest, dest_mode); 274 apic_bus_deliver(deliver_bitmask, delivery_mode, vector_num, polarity, 275 trigger_mode); 276 } 277 278 void cpu_set_apic_base(CPUState *env, uint64_t val) 279 { 280 APICState *s = env->apic_state; 281 #ifdef DEBUG_APIC 282 printf("cpu_set_apic_base: %016" PRIx64 "\n", val); 283 #endif 284 if (!s) 285 return; 286 s->apicbase = (val & 0xfffff000) | 287 (s->apicbase & (MSR_IA32_APICBASE_BSP | MSR_IA32_APICBASE_ENABLE)); 288 /* if disabled, cannot be enabled again */ 289 if (!(val & MSR_IA32_APICBASE_ENABLE)) { 290 s->apicbase &= ~MSR_IA32_APICBASE_ENABLE; 291 env->cpuid_features &= ~CPUID_APIC; 292 s->spurious_vec &= ~APIC_SV_ENABLE; 293 } 294 } 295 296 uint64_t cpu_get_apic_base(CPUState *env) 297 { 298 APICState *s = env->apic_state; 299 #ifdef DEBUG_APIC 300 printf("cpu_get_apic_base: %016" PRIx64 "\n", 301 s ? (uint64_t)s->apicbase: 0); 302 #endif 303 return s ? s->apicbase : 0; 304 } 305 306 void cpu_set_apic_tpr(CPUX86State *env, uint8_t val) 307 { 308 APICState *s = env->apic_state; 309 if (!s) 310 return; 311 s->tpr = (val & 0x0f) << 4; 312 apic_update_irq(s); 313 } 314 315 uint8_t cpu_get_apic_tpr(CPUX86State *env) 316 { 317 APICState *s = env->apic_state; 318 return s ? s->tpr >> 4 : 0; 319 } 320 321 /* return -1 if no bit is set */ 322 static int get_highest_priority_int(uint32_t *tab) 323 { 324 int i; 325 for(i = 7; i >= 0; i--) { 326 if (tab[i] != 0) { 327 return i * 32 + fls_bit(tab[i]); 328 } 329 } 330 return -1; 331 } 332 333 static int apic_get_ppr(APICState *s) 334 { 335 int tpr, isrv, ppr; 336 337 tpr = (s->tpr >> 4); 338 isrv = get_highest_priority_int(s->isr); 339 if (isrv < 0) 340 isrv = 0; 341 isrv >>= 4; 342 if (tpr >= isrv) 343 ppr = s->tpr; 344 else 345 ppr = isrv << 4; 346 return ppr; 347 } 348 349 static int apic_get_arb_pri(APICState *s) 350 { 351 /* XXX: arbitration */ 352 return 0; 353 } 354 355 /* signal the CPU if an irq is pending */ 356 static void apic_update_irq(APICState *s) 357 { 358 int irrv, ppr; 359 if (!(s->spurious_vec & APIC_SV_ENABLE)) 360 return; 361 irrv = get_highest_priority_int(s->irr); 362 if (irrv < 0) 363 return; 364 ppr = apic_get_ppr(s); 365 if (ppr && (irrv & 0xf0) <= (ppr & 0xf0)) 366 return; 367 cpu_interrupt(s->cpu_env, CPU_INTERRUPT_HARD); 368 } 369 370 void apic_reset_irq_delivered(void) 371 { 372 apic_irq_delivered = 0; 373 } 374 375 int apic_get_irq_delivered(void) 376 { 377 return apic_irq_delivered; 378 } 379 380 static void apic_set_irq(APICState *s, int vector_num, int trigger_mode) 381 { 382 apic_irq_delivered += !get_bit(s->irr, vector_num); 383 384 set_bit(s->irr, vector_num); 385 if (trigger_mode) 386 set_bit(s->tmr, vector_num); 387 else 388 reset_bit(s->tmr, vector_num); 389 apic_update_irq(s); 390 } 391 392 static void apic_eoi(APICState *s) 393 { 394 int isrv; 395 isrv = get_highest_priority_int(s->isr); 396 if (isrv < 0) 397 return; 398 reset_bit(s->isr, isrv); 399 /* XXX: send the EOI packet to the APIC bus to allow the I/O APIC to 400 set the remote IRR bit for level triggered interrupts. */ 401 apic_update_irq(s); 402 } 403 404 static int apic_find_dest(uint8_t dest) 405 { 406 APICState *apic = local_apics[dest]; 407 int i; 408 409 if (apic && apic->id == dest) 410 return dest; /* shortcut in case apic->id == apic->idx */ 411 412 for (i = 0; i < MAX_APICS; i++) { 413 apic = local_apics[i]; 414 if (apic && apic->id == dest) 415 return i; 416 } 417 418 return -1; 419 } 420 421 static void apic_get_delivery_bitmask(uint32_t *deliver_bitmask, 422 uint8_t dest, uint8_t dest_mode) 423 { 424 APICState *apic_iter; 425 int i; 426 427 if (dest_mode == 0) { 428 if (dest == 0xff) { 429 memset(deliver_bitmask, 0xff, MAX_APIC_WORDS * sizeof(uint32_t)); 430 } else { 431 int idx = apic_find_dest(dest); 432 memset(deliver_bitmask, 0x00, MAX_APIC_WORDS * sizeof(uint32_t)); 433 if (idx >= 0) 434 set_bit(deliver_bitmask, idx); 435 } 436 } else { 437 /* XXX: cluster mode */ 438 memset(deliver_bitmask, 0x00, MAX_APIC_WORDS * sizeof(uint32_t)); 439 for(i = 0; i < MAX_APICS; i++) { 440 apic_iter = local_apics[i]; 441 if (apic_iter) { 442 if (apic_iter->dest_mode == 0xf) { 443 if (dest & apic_iter->log_dest) 444 set_bit(deliver_bitmask, i); 445 } else if (apic_iter->dest_mode == 0x0) { 446 if ((dest & 0xf0) == (apic_iter->log_dest & 0xf0) && 447 (dest & apic_iter->log_dest & 0x0f)) { 448 set_bit(deliver_bitmask, i); 449 } 450 } 451 } 452 } 453 } 454 } 455 456 457 static void apic_init_ipi(APICState *s) 458 { 459 int i; 460 461 s->tpr = 0; 462 s->spurious_vec = 0xff; 463 s->log_dest = 0; 464 s->dest_mode = 0xf; 465 memset(s->isr, 0, sizeof(s->isr)); 466 memset(s->tmr, 0, sizeof(s->tmr)); 467 memset(s->irr, 0, sizeof(s->irr)); 468 for(i = 0; i < APIC_LVT_NB; i++) 469 s->lvt[i] = 1 << 16; /* mask LVT */ 470 s->esr = 0; 471 memset(s->icr, 0, sizeof(s->icr)); 472 s->divide_conf = 0; 473 s->count_shift = 0; 474 s->initial_count = 0; 475 s->initial_count_load_time = 0; 476 s->next_time = 0; 477 478 cpu_reset(s->cpu_env); 479 480 s->cpu_env->halted = !(s->apicbase & MSR_IA32_APICBASE_BSP); 481 } 482 483 /* send a SIPI message to the CPU to start it */ 484 static void apic_startup(APICState *s, int vector_num) 485 { 486 CPUState *env = s->cpu_env; 487 if (!env->halted) 488 return; 489 env->eip = 0; 490 cpu_x86_load_seg_cache(env, R_CS, vector_num << 8, vector_num << 12, 491 0xffff, 0); 492 env->halted = 0; 493 } 494 495 static void apic_deliver(APICState *s, uint8_t dest, uint8_t dest_mode, 496 uint8_t delivery_mode, uint8_t vector_num, 497 uint8_t polarity, uint8_t trigger_mode) 498 { 499 uint32_t deliver_bitmask[MAX_APIC_WORDS]; 500 int dest_shorthand = (s->icr[0] >> 18) & 3; 501 APICState *apic_iter; 502 503 switch (dest_shorthand) { 504 case 0: 505 apic_get_delivery_bitmask(deliver_bitmask, dest, dest_mode); 506 break; 507 case 1: 508 memset(deliver_bitmask, 0x00, sizeof(deliver_bitmask)); 509 set_bit(deliver_bitmask, s->idx); 510 break; 511 case 2: 512 memset(deliver_bitmask, 0xff, sizeof(deliver_bitmask)); 513 break; 514 case 3: 515 memset(deliver_bitmask, 0xff, sizeof(deliver_bitmask)); 516 reset_bit(deliver_bitmask, s->idx); 517 break; 518 } 519 520 switch (delivery_mode) { 521 case APIC_DM_INIT: 522 { 523 int trig_mode = (s->icr[0] >> 15) & 1; 524 int level = (s->icr[0] >> 14) & 1; 525 if (level == 0 && trig_mode == 1) { 526 foreach_apic(apic_iter, deliver_bitmask, 527 apic_iter->arb_id = apic_iter->id ); 528 return; 529 } 530 } 531 break; 532 533 case APIC_DM_SIPI: 534 foreach_apic(apic_iter, deliver_bitmask, 535 apic_startup(apic_iter, vector_num) ); 536 return; 537 } 538 539 apic_bus_deliver(deliver_bitmask, delivery_mode, vector_num, polarity, 540 trigger_mode); 541 } 542 543 int apic_get_interrupt(CPUState *env) 544 { 545 APICState *s = env->apic_state; 546 int intno; 547 548 /* if the APIC is installed or enabled, we let the 8259 handle the 549 IRQs */ 550 if (!s) 551 return -1; 552 if (!(s->spurious_vec & APIC_SV_ENABLE)) 553 return -1; 554 555 /* XXX: spurious IRQ handling */ 556 intno = get_highest_priority_int(s->irr); 557 if (intno < 0) 558 return -1; 559 if (s->tpr && intno <= s->tpr) 560 return s->spurious_vec & 0xff; 561 reset_bit(s->irr, intno); 562 set_bit(s->isr, intno); 563 apic_update_irq(s); 564 return intno; 565 } 566 567 int apic_accept_pic_intr(CPUState *env) 568 { 569 APICState *s = env->apic_state; 570 uint32_t lvt0; 571 572 if (!s) 573 return -1; 574 575 lvt0 = s->lvt[APIC_LVT_LINT0]; 576 577 if ((s->apicbase & MSR_IA32_APICBASE_ENABLE) == 0 || 578 (lvt0 & APIC_LVT_MASKED) == 0) 579 return 1; 580 581 return 0; 582 } 583 584 static uint32_t apic_get_current_count(APICState *s) 585 { 586 int64_t d; 587 uint32_t val; 588 d = (qemu_get_clock(vm_clock) - s->initial_count_load_time) >> 589 s->count_shift; 590 if (s->lvt[APIC_LVT_TIMER] & APIC_LVT_TIMER_PERIODIC) { 591 /* periodic */ 592 val = s->initial_count - (d % ((uint64_t)s->initial_count + 1)); 593 } else { 594 if (d >= s->initial_count) 595 val = 0; 596 else 597 val = s->initial_count - d; 598 } 599 return val; 600 } 601 602 static void apic_timer_update(APICState *s, int64_t current_time) 603 { 604 int64_t next_time, d; 605 606 if (!(s->lvt[APIC_LVT_TIMER] & APIC_LVT_MASKED)) { 607 d = (current_time - s->initial_count_load_time) >> 608 s->count_shift; 609 if (s->lvt[APIC_LVT_TIMER] & APIC_LVT_TIMER_PERIODIC) { 610 if (!s->initial_count) 611 goto no_timer; 612 d = ((d / ((uint64_t)s->initial_count + 1)) + 1) * ((uint64_t)s->initial_count + 1); 613 } else { 614 if (d >= s->initial_count) 615 goto no_timer; 616 d = (uint64_t)s->initial_count + 1; 617 } 618 next_time = s->initial_count_load_time + (d << s->count_shift); 619 qemu_mod_timer(s->timer, next_time); 620 s->next_time = next_time; 621 } else { 622 no_timer: 623 qemu_del_timer(s->timer); 624 } 625 } 626 627 static void apic_timer(void *opaque) 628 { 629 APICState *s = opaque; 630 631 apic_local_deliver(s->cpu_env, APIC_LVT_TIMER); 632 apic_timer_update(s, s->next_time); 633 } 634 635 static uint32_t apic_mem_readb(void *opaque, target_phys_addr_t addr) 636 { 637 return 0; 638 } 639 640 static uint32_t apic_mem_readw(void *opaque, target_phys_addr_t addr) 641 { 642 return 0; 643 } 644 645 static void apic_mem_writeb(void *opaque, target_phys_addr_t addr, uint32_t val) 646 { 647 } 648 649 static void apic_mem_writew(void *opaque, target_phys_addr_t addr, uint32_t val) 650 { 651 } 652 653 static uint32_t apic_mem_readl(void *opaque, target_phys_addr_t addr) 654 { 655 CPUState *env; 656 APICState *s; 657 uint32_t val; 658 int index; 659 660 env = cpu_single_env; 661 if (!env) 662 return 0; 663 s = env->apic_state; 664 665 index = (addr >> 4) & 0xff; 666 switch(index) { 667 case 0x02: /* id */ 668 val = s->id << 24; 669 break; 670 case 0x03: /* version */ 671 val = 0x11 | ((APIC_LVT_NB - 1) << 16); /* version 0x11 */ 672 break; 673 case 0x08: 674 val = s->tpr; 675 break; 676 case 0x09: 677 val = apic_get_arb_pri(s); 678 break; 679 case 0x0a: 680 /* ppr */ 681 val = apic_get_ppr(s); 682 break; 683 case 0x0b: 684 val = 0; 685 break; 686 case 0x0d: 687 val = s->log_dest << 24; 688 break; 689 case 0x0e: 690 val = s->dest_mode << 28; 691 break; 692 case 0x0f: 693 val = s->spurious_vec; 694 break; 695 case 0x10 ... 0x17: 696 val = s->isr[index & 7]; 697 break; 698 case 0x18 ... 0x1f: 699 val = s->tmr[index & 7]; 700 break; 701 case 0x20 ... 0x27: 702 val = s->irr[index & 7]; 703 break; 704 case 0x28: 705 val = s->esr; 706 break; 707 case 0x30: 708 case 0x31: 709 val = s->icr[index & 1]; 710 break; 711 case 0x32 ... 0x37: 712 val = s->lvt[index - 0x32]; 713 break; 714 case 0x38: 715 val = s->initial_count; 716 break; 717 case 0x39: 718 val = apic_get_current_count(s); 719 break; 720 case 0x3e: 721 val = s->divide_conf; 722 break; 723 default: 724 s->esr |= ESR_ILLEGAL_ADDRESS; 725 val = 0; 726 break; 727 } 728 #ifdef DEBUG_APIC 729 printf("APIC read: %08x = %08x\n", (uint32_t)addr, val); 730 #endif 731 return val; 732 } 733 734 static void apic_mem_writel(void *opaque, target_phys_addr_t addr, uint32_t val) 735 { 736 CPUState *env; 737 APICState *s; 738 int index; 739 740 env = cpu_single_env; 741 if (!env) 742 return; 743 s = env->apic_state; 744 745 #ifdef DEBUG_APIC 746 printf("APIC write: %08x = %08x\n", (uint32_t)addr, val); 747 #endif 748 749 index = (addr >> 4) & 0xff; 750 switch(index) { 751 case 0x02: 752 s->id = (val >> 24); 753 break; 754 case 0x03: 755 break; 756 case 0x08: 757 s->tpr = val; 758 apic_update_irq(s); 759 break; 760 case 0x09: 761 case 0x0a: 762 break; 763 case 0x0b: /* EOI */ 764 apic_eoi(s); 765 break; 766 case 0x0d: 767 s->log_dest = val >> 24; 768 break; 769 case 0x0e: 770 s->dest_mode = val >> 28; 771 break; 772 case 0x0f: 773 s->spurious_vec = val & 0x1ff; 774 apic_update_irq(s); 775 break; 776 case 0x10 ... 0x17: 777 case 0x18 ... 0x1f: 778 case 0x20 ... 0x27: 779 case 0x28: 780 break; 781 case 0x30: 782 s->icr[0] = val; 783 apic_deliver(s, (s->icr[1] >> 24) & 0xff, (s->icr[0] >> 11) & 1, 784 (s->icr[0] >> 8) & 7, (s->icr[0] & 0xff), 785 (s->icr[0] >> 14) & 1, (s->icr[0] >> 15) & 1); 786 break; 787 case 0x31: 788 s->icr[1] = val; 789 break; 790 case 0x32 ... 0x37: 791 { 792 int n = index - 0x32; 793 s->lvt[n] = val; 794 if (n == APIC_LVT_TIMER) 795 apic_timer_update(s, qemu_get_clock(vm_clock)); 796 } 797 break; 798 case 0x38: 799 s->initial_count = val; 800 s->initial_count_load_time = qemu_get_clock(vm_clock); 801 apic_timer_update(s, s->initial_count_load_time); 802 break; 803 case 0x39: 804 break; 805 case 0x3e: 806 { 807 int v; 808 s->divide_conf = val & 0xb; 809 v = (s->divide_conf & 3) | ((s->divide_conf >> 1) & 4); 810 s->count_shift = (v + 1) & 7; 811 } 812 break; 813 default: 814 s->esr |= ESR_ILLEGAL_ADDRESS; 815 break; 816 } 817 } 818 819 static void apic_save(QEMUFile *f, void *opaque) 820 { 821 APICState *s = opaque; 822 int i; 823 824 qemu_put_be32s(f, &s->apicbase); 825 qemu_put_8s(f, &s->id); 826 qemu_put_8s(f, &s->arb_id); 827 qemu_put_8s(f, &s->tpr); 828 qemu_put_be32s(f, &s->spurious_vec); 829 qemu_put_8s(f, &s->log_dest); 830 qemu_put_8s(f, &s->dest_mode); 831 for (i = 0; i < 8; i++) { 832 qemu_put_be32s(f, &s->isr[i]); 833 qemu_put_be32s(f, &s->tmr[i]); 834 qemu_put_be32s(f, &s->irr[i]); 835 } 836 for (i = 0; i < APIC_LVT_NB; i++) { 837 qemu_put_be32s(f, &s->lvt[i]); 838 } 839 qemu_put_be32s(f, &s->esr); 840 qemu_put_be32s(f, &s->icr[0]); 841 qemu_put_be32s(f, &s->icr[1]); 842 qemu_put_be32s(f, &s->divide_conf); 843 qemu_put_be32(f, s->count_shift); 844 qemu_put_be32s(f, &s->initial_count); 845 qemu_put_be64(f, s->initial_count_load_time); 846 qemu_put_be64(f, s->next_time); 847 848 qemu_put_timer(f, s->timer); 849 } 850 851 static int apic_load(QEMUFile *f, void *opaque, int version_id) 852 { 853 APICState *s = opaque; 854 int i; 855 856 if (version_id > 2) 857 return -EINVAL; 858 859 /* XXX: what if the base changes? (registered memory regions) */ 860 qemu_get_be32s(f, &s->apicbase); 861 qemu_get_8s(f, &s->id); 862 qemu_get_8s(f, &s->arb_id); 863 qemu_get_8s(f, &s->tpr); 864 qemu_get_be32s(f, &s->spurious_vec); 865 qemu_get_8s(f, &s->log_dest); 866 qemu_get_8s(f, &s->dest_mode); 867 for (i = 0; i < 8; i++) { 868 qemu_get_be32s(f, &s->isr[i]); 869 qemu_get_be32s(f, &s->tmr[i]); 870 qemu_get_be32s(f, &s->irr[i]); 871 } 872 for (i = 0; i < APIC_LVT_NB; i++) { 873 qemu_get_be32s(f, &s->lvt[i]); 874 } 875 qemu_get_be32s(f, &s->esr); 876 qemu_get_be32s(f, &s->icr[0]); 877 qemu_get_be32s(f, &s->icr[1]); 878 qemu_get_be32s(f, &s->divide_conf); 879 s->count_shift=qemu_get_be32(f); 880 qemu_get_be32s(f, &s->initial_count); 881 s->initial_count_load_time=qemu_get_be64(f); 882 s->next_time=qemu_get_be64(f); 883 884 if (version_id >= 2) 885 qemu_get_timer(f, s->timer); 886 return 0; 887 } 888 889 static void apic_reset(void *opaque) 890 { 891 APICState *s = opaque; 892 int bsp = cpu_is_bsp(s->cpu_env); 893 894 s->apicbase = 0xfee00000 | 895 (bsp ? MSR_IA32_APICBASE_BSP : 0) | MSR_IA32_APICBASE_ENABLE; 896 897 apic_init_ipi(s); 898 899 if (bsp) { 900 /* 901 * LINT0 delivery mode on CPU #0 is set to ExtInt at initialization 902 * time typically by BIOS, so PIC interrupt can be delivered to the 903 * processor when local APIC is enabled. 904 */ 905 s->lvt[APIC_LVT_LINT0] = 0x700; 906 } 907 } 908 909 static CPUReadMemoryFunc *apic_mem_read[3] = { 910 apic_mem_readb, 911 apic_mem_readw, 912 apic_mem_readl, 913 }; 914 915 static CPUWriteMemoryFunc *apic_mem_write[3] = { 916 apic_mem_writeb, 917 apic_mem_writew, 918 apic_mem_writel, 919 }; 920 921 int apic_init(CPUState *env) 922 { 923 APICState *s; 924 925 if (last_apic_idx >= MAX_APICS) 926 return -1; 927 s = qemu_mallocz(sizeof(APICState)); 928 env->apic_state = s; 929 s->idx = last_apic_idx++; 930 s->id = env->cpuid_apic_id; 931 s->cpu_env = env; 932 933 apic_reset(s); 934 935 /* XXX: mapping more APICs at the same memory location */ 936 if (apic_io_memory == 0) { 937 /* NOTE: the APIC is directly connected to the CPU - it is not 938 on the global memory bus. */ 939 apic_io_memory = cpu_register_io_memory(apic_mem_read, 940 apic_mem_write, NULL); 941 cpu_register_physical_memory(s->apicbase & ~0xfff, 0x1000, 942 apic_io_memory); 943 } 944 s->timer = qemu_new_timer(vm_clock, apic_timer, s); 945 946 register_savevm("apic", s->idx, 2, apic_save, apic_load, s); 947 qemu_register_reset(apic_reset, 0, s); 948 949 local_apics[s->idx] = s; 950 return 0; 951 } 952 953