xref: /qemu/hw/intc/apic.c (revision 1437c94b2689c2010362f84d14f14feaa1d8dba3)
1574bbf7bSbellard /*
2574bbf7bSbellard  *  APIC support
3574bbf7bSbellard  *
4574bbf7bSbellard  *  Copyright (c) 2004-2005 Fabrice Bellard
5574bbf7bSbellard  *
6574bbf7bSbellard  * This library is free software; you can redistribute it and/or
7574bbf7bSbellard  * modify it under the terms of the GNU Lesser General Public
8574bbf7bSbellard  * License as published by the Free Software Foundation; either
9574bbf7bSbellard  * version 2 of the License, or (at your option) any later version.
10574bbf7bSbellard  *
11574bbf7bSbellard  * This library is distributed in the hope that it will be useful,
12574bbf7bSbellard  * but WITHOUT ANY WARRANTY; without even the implied warranty of
13574bbf7bSbellard  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
14574bbf7bSbellard  * Lesser General Public License for more details.
15574bbf7bSbellard  *
16574bbf7bSbellard  * You should have received a copy of the GNU Lesser General Public
178167ee88SBlue Swirl  * License along with this library; if not, see <http://www.gnu.org/licenses/>
18574bbf7bSbellard  */
191de7afc9SPaolo Bonzini #include "qemu/thread.h"
200d09e41aSPaolo Bonzini #include "hw/i386/apic_internal.h"
210d09e41aSPaolo Bonzini #include "hw/i386/apic.h"
220d09e41aSPaolo Bonzini #include "hw/i386/ioapic.h"
2383c9f4caSPaolo Bonzini #include "hw/pci/msi.h"
241de7afc9SPaolo Bonzini #include "qemu/host-utils.h"
25d8023f31SBlue Swirl #include "trace.h"
260d09e41aSPaolo Bonzini #include "hw/i386/pc.h"
270d09e41aSPaolo Bonzini #include "hw/i386/apic-msidef.h"
28574bbf7bSbellard 
29d3e9db93Sbellard #define MAX_APIC_WORDS 8
30d3e9db93Sbellard 
31e5ad936bSJan Kiszka #define SYNC_FROM_VAPIC                 0x1
32e5ad936bSJan Kiszka #define SYNC_TO_VAPIC                   0x2
33e5ad936bSJan Kiszka #define SYNC_ISR_IRR_TO_VAPIC           0x4
34e5ad936bSJan Kiszka 
35dae01685SJan Kiszka static APICCommonState *local_apics[MAX_APICS + 1];
3654c96da7SMichael S. Tsirkin 
37dae01685SJan Kiszka static void apic_set_irq(APICCommonState *s, int vector_num, int trigger_mode);
38dae01685SJan Kiszka static void apic_update_irq(APICCommonState *s);
39610626afSaliguori static void apic_get_delivery_bitmask(uint32_t *deliver_bitmask,
40610626afSaliguori                                       uint8_t dest, uint8_t dest_mode);
41d592d303Sbellard 
423b63c04eSaurel32 /* Find first bit starting from msb */
43edf9735eSMichael S. Tsirkin static int apic_fls_bit(uint32_t value)
443b63c04eSaurel32 {
453b63c04eSaurel32     return 31 - clz32(value);
463b63c04eSaurel32 }
473b63c04eSaurel32 
48e95f5491Saurel32 /* Find first bit starting from lsb */
49edf9735eSMichael S. Tsirkin static int apic_ffs_bit(uint32_t value)
50d3e9db93Sbellard {
51bb7e7293Saurel32     return ctz32(value);
52d3e9db93Sbellard }
53d3e9db93Sbellard 
54edf9735eSMichael S. Tsirkin static inline void apic_set_bit(uint32_t *tab, int index)
55d3e9db93Sbellard {
56d3e9db93Sbellard     int i, mask;
57d3e9db93Sbellard     i = index >> 5;
58d3e9db93Sbellard     mask = 1 << (index & 0x1f);
59d3e9db93Sbellard     tab[i] |= mask;
60d3e9db93Sbellard }
61d3e9db93Sbellard 
62edf9735eSMichael S. Tsirkin static inline void apic_reset_bit(uint32_t *tab, int index)
63d3e9db93Sbellard {
64d3e9db93Sbellard     int i, mask;
65d3e9db93Sbellard     i = index >> 5;
66d3e9db93Sbellard     mask = 1 << (index & 0x1f);
67d3e9db93Sbellard     tab[i] &= ~mask;
68d3e9db93Sbellard }
69d3e9db93Sbellard 
70edf9735eSMichael S. Tsirkin static inline int apic_get_bit(uint32_t *tab, int index)
7173822ec8Saliguori {
7273822ec8Saliguori     int i, mask;
7373822ec8Saliguori     i = index >> 5;
7473822ec8Saliguori     mask = 1 << (index & 0x1f);
7573822ec8Saliguori     return !!(tab[i] & mask);
7673822ec8Saliguori }
7773822ec8Saliguori 
78e5ad936bSJan Kiszka /* return -1 if no bit is set */
79e5ad936bSJan Kiszka static int get_highest_priority_int(uint32_t *tab)
80e5ad936bSJan Kiszka {
81e5ad936bSJan Kiszka     int i;
82e5ad936bSJan Kiszka     for (i = 7; i >= 0; i--) {
83e5ad936bSJan Kiszka         if (tab[i] != 0) {
84edf9735eSMichael S. Tsirkin             return i * 32 + apic_fls_bit(tab[i]);
85e5ad936bSJan Kiszka         }
86e5ad936bSJan Kiszka     }
87e5ad936bSJan Kiszka     return -1;
88e5ad936bSJan Kiszka }
89e5ad936bSJan Kiszka 
90e5ad936bSJan Kiszka static void apic_sync_vapic(APICCommonState *s, int sync_type)
91e5ad936bSJan Kiszka {
92e5ad936bSJan Kiszka     VAPICState vapic_state;
93e5ad936bSJan Kiszka     size_t length;
94e5ad936bSJan Kiszka     off_t start;
95e5ad936bSJan Kiszka     int vector;
96e5ad936bSJan Kiszka 
97e5ad936bSJan Kiszka     if (!s->vapic_paddr) {
98e5ad936bSJan Kiszka         return;
99e5ad936bSJan Kiszka     }
100e5ad936bSJan Kiszka     if (sync_type & SYNC_FROM_VAPIC) {
101e5ad936bSJan Kiszka         cpu_physical_memory_rw(s->vapic_paddr, (void *)&vapic_state,
102e5ad936bSJan Kiszka                                sizeof(vapic_state), 0);
103e5ad936bSJan Kiszka         s->tpr = vapic_state.tpr;
104e5ad936bSJan Kiszka     }
105e5ad936bSJan Kiszka     if (sync_type & (SYNC_TO_VAPIC | SYNC_ISR_IRR_TO_VAPIC)) {
106e5ad936bSJan Kiszka         start = offsetof(VAPICState, isr);
107e5ad936bSJan Kiszka         length = offsetof(VAPICState, enabled) - offsetof(VAPICState, isr);
108e5ad936bSJan Kiszka 
109e5ad936bSJan Kiszka         if (sync_type & SYNC_TO_VAPIC) {
11060e82579SAndreas Färber             assert(qemu_cpu_is_self(CPU(s->cpu)));
111e5ad936bSJan Kiszka 
112e5ad936bSJan Kiszka             vapic_state.tpr = s->tpr;
113e5ad936bSJan Kiszka             vapic_state.enabled = 1;
114e5ad936bSJan Kiszka             start = 0;
115e5ad936bSJan Kiszka             length = sizeof(VAPICState);
116e5ad936bSJan Kiszka         }
117e5ad936bSJan Kiszka 
118e5ad936bSJan Kiszka         vector = get_highest_priority_int(s->isr);
119e5ad936bSJan Kiszka         if (vector < 0) {
120e5ad936bSJan Kiszka             vector = 0;
121e5ad936bSJan Kiszka         }
122e5ad936bSJan Kiszka         vapic_state.isr = vector & 0xf0;
123e5ad936bSJan Kiszka 
124e5ad936bSJan Kiszka         vapic_state.zero = 0;
125e5ad936bSJan Kiszka 
126e5ad936bSJan Kiszka         vector = get_highest_priority_int(s->irr);
127e5ad936bSJan Kiszka         if (vector < 0) {
128e5ad936bSJan Kiszka             vector = 0;
129e5ad936bSJan Kiszka         }
130e5ad936bSJan Kiszka         vapic_state.irr = vector & 0xff;
131e5ad936bSJan Kiszka 
132e5ad936bSJan Kiszka         cpu_physical_memory_write_rom(s->vapic_paddr + start,
133e5ad936bSJan Kiszka                                       ((void *)&vapic_state) + start, length);
134e5ad936bSJan Kiszka     }
135e5ad936bSJan Kiszka }
136e5ad936bSJan Kiszka 
137e5ad936bSJan Kiszka static void apic_vapic_base_update(APICCommonState *s)
138e5ad936bSJan Kiszka {
139e5ad936bSJan Kiszka     apic_sync_vapic(s, SYNC_TO_VAPIC);
140e5ad936bSJan Kiszka }
141e5ad936bSJan Kiszka 
142dae01685SJan Kiszka static void apic_local_deliver(APICCommonState *s, int vector)
143a5b38b51Saurel32 {
144a5b38b51Saurel32     uint32_t lvt = s->lvt[vector];
145a5b38b51Saurel32     int trigger_mode;
146a5b38b51Saurel32 
147d8023f31SBlue Swirl     trace_apic_local_deliver(vector, (lvt >> 8) & 7);
148d8023f31SBlue Swirl 
149a5b38b51Saurel32     if (lvt & APIC_LVT_MASKED)
150a5b38b51Saurel32         return;
151a5b38b51Saurel32 
152a5b38b51Saurel32     switch ((lvt >> 8) & 7) {
153a5b38b51Saurel32     case APIC_DM_SMI:
154c3affe56SAndreas Färber         cpu_interrupt(CPU(s->cpu), CPU_INTERRUPT_SMI);
155a5b38b51Saurel32         break;
156a5b38b51Saurel32 
157a5b38b51Saurel32     case APIC_DM_NMI:
158c3affe56SAndreas Färber         cpu_interrupt(CPU(s->cpu), CPU_INTERRUPT_NMI);
159a5b38b51Saurel32         break;
160a5b38b51Saurel32 
161a5b38b51Saurel32     case APIC_DM_EXTINT:
162c3affe56SAndreas Färber         cpu_interrupt(CPU(s->cpu), CPU_INTERRUPT_HARD);
163a5b38b51Saurel32         break;
164a5b38b51Saurel32 
165a5b38b51Saurel32     case APIC_DM_FIXED:
166a5b38b51Saurel32         trigger_mode = APIC_TRIGGER_EDGE;
167a5b38b51Saurel32         if ((vector == APIC_LVT_LINT0 || vector == APIC_LVT_LINT1) &&
168a5b38b51Saurel32             (lvt & APIC_LVT_LEVEL_TRIGGER))
169a5b38b51Saurel32             trigger_mode = APIC_TRIGGER_LEVEL;
170a5b38b51Saurel32         apic_set_irq(s, lvt & 0xff, trigger_mode);
171a5b38b51Saurel32     }
172a5b38b51Saurel32 }
173a5b38b51Saurel32 
17492a16d7aSBlue Swirl void apic_deliver_pic_intr(DeviceState *d, int level)
1751a7de94aSaurel32 {
176dae01685SJan Kiszka     APICCommonState *s = DO_UPCAST(APICCommonState, busdev.qdev, d);
17792a16d7aSBlue Swirl 
178cf6d64bfSBlue Swirl     if (level) {
179cf6d64bfSBlue Swirl         apic_local_deliver(s, APIC_LVT_LINT0);
180cf6d64bfSBlue Swirl     } else {
1811a7de94aSaurel32         uint32_t lvt = s->lvt[APIC_LVT_LINT0];
1821a7de94aSaurel32 
1831a7de94aSaurel32         switch ((lvt >> 8) & 7) {
1841a7de94aSaurel32         case APIC_DM_FIXED:
1851a7de94aSaurel32             if (!(lvt & APIC_LVT_LEVEL_TRIGGER))
1861a7de94aSaurel32                 break;
187edf9735eSMichael S. Tsirkin             apic_reset_bit(s->irr, lvt & 0xff);
1881a7de94aSaurel32             /* fall through */
1891a7de94aSaurel32         case APIC_DM_EXTINT:
190d8ed887bSAndreas Färber             cpu_reset_interrupt(CPU(s->cpu), CPU_INTERRUPT_HARD);
1911a7de94aSaurel32             break;
1921a7de94aSaurel32         }
1931a7de94aSaurel32     }
1941a7de94aSaurel32 }
1951a7de94aSaurel32 
196dae01685SJan Kiszka static void apic_external_nmi(APICCommonState *s)
19702c09195SJan Kiszka {
19802c09195SJan Kiszka     apic_local_deliver(s, APIC_LVT_LINT1);
19902c09195SJan Kiszka }
20002c09195SJan Kiszka 
201d3e9db93Sbellard #define foreach_apic(apic, deliver_bitmask, code) \
202d3e9db93Sbellard {\
203d3e9db93Sbellard     int __i, __j, __mask;\
204d3e9db93Sbellard     for(__i = 0; __i < MAX_APIC_WORDS; __i++) {\
205d3e9db93Sbellard         __mask = deliver_bitmask[__i];\
206d3e9db93Sbellard         if (__mask) {\
207d3e9db93Sbellard             for(__j = 0; __j < 32; __j++) {\
208d3e9db93Sbellard                 if (__mask & (1 << __j)) {\
209d3e9db93Sbellard                     apic = local_apics[__i * 32 + __j];\
210d3e9db93Sbellard                     if (apic) {\
211d3e9db93Sbellard                         code;\
212d3e9db93Sbellard                     }\
213d3e9db93Sbellard                 }\
214d3e9db93Sbellard             }\
215d3e9db93Sbellard         }\
216d3e9db93Sbellard     }\
217d3e9db93Sbellard }
218d3e9db93Sbellard 
219d3e9db93Sbellard static void apic_bus_deliver(const uint32_t *deliver_bitmask,
2201f6f408cSJan Kiszka                              uint8_t delivery_mode, uint8_t vector_num,
221d592d303Sbellard                              uint8_t trigger_mode)
222d592d303Sbellard {
223dae01685SJan Kiszka     APICCommonState *apic_iter;
224d592d303Sbellard 
225d592d303Sbellard     switch (delivery_mode) {
226d592d303Sbellard         case APIC_DM_LOWPRI:
2278dd69b8fSbellard             /* XXX: search for focus processor, arbitration */
228d3e9db93Sbellard             {
229d3e9db93Sbellard                 int i, d;
230d3e9db93Sbellard                 d = -1;
231d3e9db93Sbellard                 for(i = 0; i < MAX_APIC_WORDS; i++) {
232d3e9db93Sbellard                     if (deliver_bitmask[i]) {
233edf9735eSMichael S. Tsirkin                         d = i * 32 + apic_ffs_bit(deliver_bitmask[i]);
2348dd69b8fSbellard                         break;
235d3e9db93Sbellard                     }
236d3e9db93Sbellard                 }
237d3e9db93Sbellard                 if (d >= 0) {
238d3e9db93Sbellard                     apic_iter = local_apics[d];
239d3e9db93Sbellard                     if (apic_iter) {
240d3e9db93Sbellard                         apic_set_irq(apic_iter, vector_num, trigger_mode);
241d3e9db93Sbellard                     }
242d3e9db93Sbellard                 }
243d3e9db93Sbellard             }
244d3e9db93Sbellard             return;
2458dd69b8fSbellard 
246d592d303Sbellard         case APIC_DM_FIXED:
247d592d303Sbellard             break;
248d592d303Sbellard 
249d592d303Sbellard         case APIC_DM_SMI:
250e2eb9d3eSaurel32             foreach_apic(apic_iter, deliver_bitmask,
251c3affe56SAndreas Färber                 cpu_interrupt(CPU(apic_iter->cpu), CPU_INTERRUPT_SMI)
25260671e58SAndreas Färber             );
253e2eb9d3eSaurel32             return;
254e2eb9d3eSaurel32 
255d592d303Sbellard         case APIC_DM_NMI:
256e2eb9d3eSaurel32             foreach_apic(apic_iter, deliver_bitmask,
257c3affe56SAndreas Färber                 cpu_interrupt(CPU(apic_iter->cpu), CPU_INTERRUPT_NMI)
25860671e58SAndreas Färber             );
259e2eb9d3eSaurel32             return;
260d592d303Sbellard 
261d592d303Sbellard         case APIC_DM_INIT:
262d592d303Sbellard             /* normal INIT IPI sent to processors */
263d3e9db93Sbellard             foreach_apic(apic_iter, deliver_bitmask,
264c3affe56SAndreas Färber                          cpu_interrupt(CPU(apic_iter->cpu),
26560671e58SAndreas Färber                                        CPU_INTERRUPT_INIT)
26660671e58SAndreas Färber             );
267d592d303Sbellard             return;
268d592d303Sbellard 
269d592d303Sbellard         case APIC_DM_EXTINT:
270b1fc0348Sbellard             /* handled in I/O APIC code */
271d592d303Sbellard             break;
272d592d303Sbellard 
273d592d303Sbellard         default:
274d592d303Sbellard             return;
275d592d303Sbellard     }
276d592d303Sbellard 
277d3e9db93Sbellard     foreach_apic(apic_iter, deliver_bitmask,
278d3e9db93Sbellard                  apic_set_irq(apic_iter, vector_num, trigger_mode) );
279d592d303Sbellard }
280574bbf7bSbellard 
2811f6f408cSJan Kiszka void apic_deliver_irq(uint8_t dest, uint8_t dest_mode, uint8_t delivery_mode,
2821f6f408cSJan Kiszka                       uint8_t vector_num, uint8_t trigger_mode)
283610626afSaliguori {
284610626afSaliguori     uint32_t deliver_bitmask[MAX_APIC_WORDS];
285610626afSaliguori 
286d8023f31SBlue Swirl     trace_apic_deliver_irq(dest, dest_mode, delivery_mode, vector_num,
2871f6f408cSJan Kiszka                            trigger_mode);
288d8023f31SBlue Swirl 
289610626afSaliguori     apic_get_delivery_bitmask(deliver_bitmask, dest, dest_mode);
2901f6f408cSJan Kiszka     apic_bus_deliver(deliver_bitmask, delivery_mode, vector_num, trigger_mode);
291610626afSaliguori }
292610626afSaliguori 
293dae01685SJan Kiszka static void apic_set_base(APICCommonState *s, uint64_t val)
294574bbf7bSbellard {
295574bbf7bSbellard     s->apicbase = (val & 0xfffff000) |
296574bbf7bSbellard         (s->apicbase & (MSR_IA32_APICBASE_BSP | MSR_IA32_APICBASE_ENABLE));
297574bbf7bSbellard     /* if disabled, cannot be enabled again */
298574bbf7bSbellard     if (!(val & MSR_IA32_APICBASE_ENABLE)) {
299574bbf7bSbellard         s->apicbase &= ~MSR_IA32_APICBASE_ENABLE;
30060671e58SAndreas Färber         cpu_clear_apic_feature(&s->cpu->env);
301574bbf7bSbellard         s->spurious_vec &= ~APIC_SV_ENABLE;
302574bbf7bSbellard     }
303574bbf7bSbellard }
304574bbf7bSbellard 
305dae01685SJan Kiszka static void apic_set_tpr(APICCommonState *s, uint8_t val)
306574bbf7bSbellard {
307e5ad936bSJan Kiszka     /* Updates from cr8 are ignored while the VAPIC is active */
308e5ad936bSJan Kiszka     if (!s->vapic_paddr) {
309e5ad936bSJan Kiszka         s->tpr = val << 4;
310d592d303Sbellard         apic_update_irq(s);
3119230e66eSbellard     }
312e5ad936bSJan Kiszka }
3139230e66eSbellard 
314e5ad936bSJan Kiszka static uint8_t apic_get_tpr(APICCommonState *s)
315d592d303Sbellard {
316e5ad936bSJan Kiszka     apic_sync_vapic(s, SYNC_FROM_VAPIC);
317e5ad936bSJan Kiszka     return s->tpr >> 4;
318d592d303Sbellard }
319d592d303Sbellard 
320dae01685SJan Kiszka static int apic_get_ppr(APICCommonState *s)
321574bbf7bSbellard {
322574bbf7bSbellard     int tpr, isrv, ppr;
323574bbf7bSbellard 
324574bbf7bSbellard     tpr = (s->tpr >> 4);
325574bbf7bSbellard     isrv = get_highest_priority_int(s->isr);
326574bbf7bSbellard     if (isrv < 0)
327574bbf7bSbellard         isrv = 0;
328574bbf7bSbellard     isrv >>= 4;
329574bbf7bSbellard     if (tpr >= isrv)
330574bbf7bSbellard         ppr = s->tpr;
331574bbf7bSbellard     else
332574bbf7bSbellard         ppr = isrv << 4;
333574bbf7bSbellard     return ppr;
334574bbf7bSbellard }
335574bbf7bSbellard 
336dae01685SJan Kiszka static int apic_get_arb_pri(APICCommonState *s)
337d592d303Sbellard {
338d592d303Sbellard     /* XXX: arbitration */
339d592d303Sbellard     return 0;
340d592d303Sbellard }
341d592d303Sbellard 
3420fbfbb59SGleb Natapov 
3430fbfbb59SGleb Natapov /*
3440fbfbb59SGleb Natapov  * <0 - low prio interrupt,
3450fbfbb59SGleb Natapov  * 0  - no interrupt,
3460fbfbb59SGleb Natapov  * >0 - interrupt number
3470fbfbb59SGleb Natapov  */
348dae01685SJan Kiszka static int apic_irq_pending(APICCommonState *s)
3490fbfbb59SGleb Natapov {
3500fbfbb59SGleb Natapov     int irrv, ppr;
3510fbfbb59SGleb Natapov     irrv = get_highest_priority_int(s->irr);
3520fbfbb59SGleb Natapov     if (irrv < 0) {
3530fbfbb59SGleb Natapov         return 0;
3540fbfbb59SGleb Natapov     }
3550fbfbb59SGleb Natapov     ppr = apic_get_ppr(s);
3560fbfbb59SGleb Natapov     if (ppr && (irrv & 0xf0) <= (ppr & 0xf0)) {
3570fbfbb59SGleb Natapov         return -1;
3580fbfbb59SGleb Natapov     }
3590fbfbb59SGleb Natapov 
3600fbfbb59SGleb Natapov     return irrv;
3610fbfbb59SGleb Natapov }
3620fbfbb59SGleb Natapov 
363574bbf7bSbellard /* signal the CPU if an irq is pending */
364dae01685SJan Kiszka static void apic_update_irq(APICCommonState *s)
365574bbf7bSbellard {
366c3affe56SAndreas Färber     CPUState *cpu;
36760e82579SAndreas Färber 
3680fbfbb59SGleb Natapov     if (!(s->spurious_vec & APIC_SV_ENABLE)) {
369d592d303Sbellard         return;
3700fbfbb59SGleb Natapov     }
371c3affe56SAndreas Färber     cpu = CPU(s->cpu);
37260e82579SAndreas Färber     if (!qemu_cpu_is_self(cpu)) {
373c3affe56SAndreas Färber         cpu_interrupt(cpu, CPU_INTERRUPT_POLL);
3745d62c43aSJan Kiszka     } else if (apic_irq_pending(s) > 0) {
375c3affe56SAndreas Färber         cpu_interrupt(cpu, CPU_INTERRUPT_HARD);
376574bbf7bSbellard     }
3770fbfbb59SGleb Natapov }
378574bbf7bSbellard 
379e5ad936bSJan Kiszka void apic_poll_irq(DeviceState *d)
380e5ad936bSJan Kiszka {
381e5ad936bSJan Kiszka     APICCommonState *s = APIC_COMMON(d);
382e5ad936bSJan Kiszka 
383e5ad936bSJan Kiszka     apic_sync_vapic(s, SYNC_FROM_VAPIC);
384e5ad936bSJan Kiszka     apic_update_irq(s);
385e5ad936bSJan Kiszka }
386e5ad936bSJan Kiszka 
387dae01685SJan Kiszka static void apic_set_irq(APICCommonState *s, int vector_num, int trigger_mode)
388574bbf7bSbellard {
389edf9735eSMichael S. Tsirkin     apic_report_irq_delivered(!apic_get_bit(s->irr, vector_num));
39073822ec8Saliguori 
391edf9735eSMichael S. Tsirkin     apic_set_bit(s->irr, vector_num);
392574bbf7bSbellard     if (trigger_mode)
393edf9735eSMichael S. Tsirkin         apic_set_bit(s->tmr, vector_num);
394574bbf7bSbellard     else
395edf9735eSMichael S. Tsirkin         apic_reset_bit(s->tmr, vector_num);
396e5ad936bSJan Kiszka     if (s->vapic_paddr) {
397e5ad936bSJan Kiszka         apic_sync_vapic(s, SYNC_ISR_IRR_TO_VAPIC);
398e5ad936bSJan Kiszka         /*
399e5ad936bSJan Kiszka          * The vcpu thread needs to see the new IRR before we pull its current
400e5ad936bSJan Kiszka          * TPR value. That way, if we miss a lowering of the TRP, the guest
401e5ad936bSJan Kiszka          * has the chance to notice the new IRR and poll for IRQs on its own.
402e5ad936bSJan Kiszka          */
403e5ad936bSJan Kiszka         smp_wmb();
404e5ad936bSJan Kiszka         apic_sync_vapic(s, SYNC_FROM_VAPIC);
405e5ad936bSJan Kiszka     }
406574bbf7bSbellard     apic_update_irq(s);
407574bbf7bSbellard }
408574bbf7bSbellard 
409dae01685SJan Kiszka static void apic_eoi(APICCommonState *s)
410574bbf7bSbellard {
411574bbf7bSbellard     int isrv;
412574bbf7bSbellard     isrv = get_highest_priority_int(s->isr);
413574bbf7bSbellard     if (isrv < 0)
414574bbf7bSbellard         return;
415edf9735eSMichael S. Tsirkin     apic_reset_bit(s->isr, isrv);
416edf9735eSMichael S. Tsirkin     if (!(s->spurious_vec & APIC_SV_DIRECTED_IO) && apic_get_bit(s->tmr, isrv)) {
4170280b571SJan Kiszka         ioapic_eoi_broadcast(isrv);
4180280b571SJan Kiszka     }
419e5ad936bSJan Kiszka     apic_sync_vapic(s, SYNC_FROM_VAPIC | SYNC_TO_VAPIC);
420574bbf7bSbellard     apic_update_irq(s);
421574bbf7bSbellard }
422574bbf7bSbellard 
423678e12ccSGleb Natapov static int apic_find_dest(uint8_t dest)
424678e12ccSGleb Natapov {
425dae01685SJan Kiszka     APICCommonState *apic = local_apics[dest];
426678e12ccSGleb Natapov     int i;
427678e12ccSGleb Natapov 
428678e12ccSGleb Natapov     if (apic && apic->id == dest)
429678e12ccSGleb Natapov         return dest;  /* shortcut in case apic->id == apic->idx */
430678e12ccSGleb Natapov 
431678e12ccSGleb Natapov     for (i = 0; i < MAX_APICS; i++) {
432678e12ccSGleb Natapov         apic = local_apics[i];
433678e12ccSGleb Natapov 	if (apic && apic->id == dest)
434678e12ccSGleb Natapov             return i;
435b538e53eSAlex Williamson         if (!apic)
436b538e53eSAlex Williamson             break;
437678e12ccSGleb Natapov     }
438678e12ccSGleb Natapov 
439678e12ccSGleb Natapov     return -1;
440678e12ccSGleb Natapov }
441678e12ccSGleb Natapov 
442d3e9db93Sbellard static void apic_get_delivery_bitmask(uint32_t *deliver_bitmask,
443d3e9db93Sbellard                                       uint8_t dest, uint8_t dest_mode)
444d592d303Sbellard {
445dae01685SJan Kiszka     APICCommonState *apic_iter;
446d3e9db93Sbellard     int i;
447d592d303Sbellard 
448d592d303Sbellard     if (dest_mode == 0) {
449d3e9db93Sbellard         if (dest == 0xff) {
450d3e9db93Sbellard             memset(deliver_bitmask, 0xff, MAX_APIC_WORDS * sizeof(uint32_t));
451d3e9db93Sbellard         } else {
452678e12ccSGleb Natapov             int idx = apic_find_dest(dest);
453d3e9db93Sbellard             memset(deliver_bitmask, 0x00, MAX_APIC_WORDS * sizeof(uint32_t));
454678e12ccSGleb Natapov             if (idx >= 0)
455edf9735eSMichael S. Tsirkin                 apic_set_bit(deliver_bitmask, idx);
456d3e9db93Sbellard         }
457d592d303Sbellard     } else {
458d592d303Sbellard         /* XXX: cluster mode */
459d3e9db93Sbellard         memset(deliver_bitmask, 0x00, MAX_APIC_WORDS * sizeof(uint32_t));
460d3e9db93Sbellard         for(i = 0; i < MAX_APICS; i++) {
461d3e9db93Sbellard             apic_iter = local_apics[i];
462d3e9db93Sbellard             if (apic_iter) {
463d3e9db93Sbellard                 if (apic_iter->dest_mode == 0xf) {
464d592d303Sbellard                     if (dest & apic_iter->log_dest)
465edf9735eSMichael S. Tsirkin                         apic_set_bit(deliver_bitmask, i);
466d3e9db93Sbellard                 } else if (apic_iter->dest_mode == 0x0) {
467d3e9db93Sbellard                     if ((dest & 0xf0) == (apic_iter->log_dest & 0xf0) &&
468d3e9db93Sbellard                         (dest & apic_iter->log_dest & 0x0f)) {
469edf9735eSMichael S. Tsirkin                         apic_set_bit(deliver_bitmask, i);
470d592d303Sbellard                     }
471d592d303Sbellard                 }
472b538e53eSAlex Williamson             } else {
473b538e53eSAlex Williamson                 break;
474d3e9db93Sbellard             }
475d3e9db93Sbellard         }
476d3e9db93Sbellard     }
477d592d303Sbellard }
478d592d303Sbellard 
479dae01685SJan Kiszka static void apic_startup(APICCommonState *s, int vector_num)
480e0fd8781Sbellard {
481b09ea7d5SGleb Natapov     s->sipi_vector = vector_num;
482c3affe56SAndreas Färber     cpu_interrupt(CPU(s->cpu), CPU_INTERRUPT_SIPI);
483b09ea7d5SGleb Natapov }
484b09ea7d5SGleb Natapov 
48592a16d7aSBlue Swirl void apic_sipi(DeviceState *d)
486b09ea7d5SGleb Natapov {
487dae01685SJan Kiszka     APICCommonState *s = DO_UPCAST(APICCommonState, busdev.qdev, d);
48892a16d7aSBlue Swirl 
489d8ed887bSAndreas Färber     cpu_reset_interrupt(CPU(s->cpu), CPU_INTERRUPT_SIPI);
490b09ea7d5SGleb Natapov 
491b09ea7d5SGleb Natapov     if (!s->wait_for_sipi)
492e0fd8781Sbellard         return;
493e9f9d6b1SAndreas Färber     cpu_x86_load_seg_cache_sipi(s->cpu, s->sipi_vector);
494b09ea7d5SGleb Natapov     s->wait_for_sipi = 0;
495e0fd8781Sbellard }
496e0fd8781Sbellard 
49792a16d7aSBlue Swirl static void apic_deliver(DeviceState *d, uint8_t dest, uint8_t dest_mode,
498d592d303Sbellard                          uint8_t delivery_mode, uint8_t vector_num,
4991f6f408cSJan Kiszka                          uint8_t trigger_mode)
500d592d303Sbellard {
501dae01685SJan Kiszka     APICCommonState *s = DO_UPCAST(APICCommonState, busdev.qdev, d);
502d3e9db93Sbellard     uint32_t deliver_bitmask[MAX_APIC_WORDS];
503d592d303Sbellard     int dest_shorthand = (s->icr[0] >> 18) & 3;
504dae01685SJan Kiszka     APICCommonState *apic_iter;
505d592d303Sbellard 
506e0fd8781Sbellard     switch (dest_shorthand) {
507e0fd8781Sbellard     case 0:
508d3e9db93Sbellard         apic_get_delivery_bitmask(deliver_bitmask, dest, dest_mode);
509e0fd8781Sbellard         break;
510e0fd8781Sbellard     case 1:
511d3e9db93Sbellard         memset(deliver_bitmask, 0x00, sizeof(deliver_bitmask));
512edf9735eSMichael S. Tsirkin         apic_set_bit(deliver_bitmask, s->idx);
513e0fd8781Sbellard         break;
514e0fd8781Sbellard     case 2:
515d3e9db93Sbellard         memset(deliver_bitmask, 0xff, sizeof(deliver_bitmask));
516e0fd8781Sbellard         break;
517e0fd8781Sbellard     case 3:
518d3e9db93Sbellard         memset(deliver_bitmask, 0xff, sizeof(deliver_bitmask));
519edf9735eSMichael S. Tsirkin         apic_reset_bit(deliver_bitmask, s->idx);
520e0fd8781Sbellard         break;
521e0fd8781Sbellard     }
522e0fd8781Sbellard 
523d592d303Sbellard     switch (delivery_mode) {
524d592d303Sbellard         case APIC_DM_INIT:
525d592d303Sbellard             {
526d592d303Sbellard                 int trig_mode = (s->icr[0] >> 15) & 1;
527d592d303Sbellard                 int level = (s->icr[0] >> 14) & 1;
528d592d303Sbellard                 if (level == 0 && trig_mode == 1) {
529d3e9db93Sbellard                     foreach_apic(apic_iter, deliver_bitmask,
530d3e9db93Sbellard                                  apic_iter->arb_id = apic_iter->id );
531d592d303Sbellard                     return;
532d592d303Sbellard                 }
533d592d303Sbellard             }
534d592d303Sbellard             break;
535d592d303Sbellard 
536d592d303Sbellard         case APIC_DM_SIPI:
537d3e9db93Sbellard             foreach_apic(apic_iter, deliver_bitmask,
538d3e9db93Sbellard                          apic_startup(apic_iter, vector_num) );
539d592d303Sbellard             return;
540d592d303Sbellard     }
541d592d303Sbellard 
5421f6f408cSJan Kiszka     apic_bus_deliver(deliver_bitmask, delivery_mode, vector_num, trigger_mode);
543d592d303Sbellard }
544d592d303Sbellard 
545a94820ddSJan Kiszka static bool apic_check_pic(APICCommonState *s)
546a94820ddSJan Kiszka {
547a94820ddSJan Kiszka     if (!apic_accept_pic_intr(&s->busdev.qdev) || !pic_get_output(isa_pic)) {
548a94820ddSJan Kiszka         return false;
549a94820ddSJan Kiszka     }
550a94820ddSJan Kiszka     apic_deliver_pic_intr(&s->busdev.qdev, 1);
551a94820ddSJan Kiszka     return true;
552a94820ddSJan Kiszka }
553a94820ddSJan Kiszka 
55492a16d7aSBlue Swirl int apic_get_interrupt(DeviceState *d)
555574bbf7bSbellard {
556dae01685SJan Kiszka     APICCommonState *s = DO_UPCAST(APICCommonState, busdev.qdev, d);
557574bbf7bSbellard     int intno;
558574bbf7bSbellard 
559574bbf7bSbellard     /* if the APIC is installed or enabled, we let the 8259 handle the
560574bbf7bSbellard        IRQs */
561574bbf7bSbellard     if (!s)
562574bbf7bSbellard         return -1;
563574bbf7bSbellard     if (!(s->spurious_vec & APIC_SV_ENABLE))
564574bbf7bSbellard         return -1;
565574bbf7bSbellard 
566e5ad936bSJan Kiszka     apic_sync_vapic(s, SYNC_FROM_VAPIC);
5670fbfbb59SGleb Natapov     intno = apic_irq_pending(s);
5680fbfbb59SGleb Natapov 
5690fbfbb59SGleb Natapov     if (intno == 0) {
570e5ad936bSJan Kiszka         apic_sync_vapic(s, SYNC_TO_VAPIC);
571574bbf7bSbellard         return -1;
5720fbfbb59SGleb Natapov     } else if (intno < 0) {
573e5ad936bSJan Kiszka         apic_sync_vapic(s, SYNC_TO_VAPIC);
574d592d303Sbellard         return s->spurious_vec & 0xff;
5750fbfbb59SGleb Natapov     }
576edf9735eSMichael S. Tsirkin     apic_reset_bit(s->irr, intno);
577edf9735eSMichael S. Tsirkin     apic_set_bit(s->isr, intno);
578e5ad936bSJan Kiszka     apic_sync_vapic(s, SYNC_TO_VAPIC);
5793db3659bSJan Kiszka 
5803db3659bSJan Kiszka     /* re-inject if there is still a pending PIC interrupt */
581a94820ddSJan Kiszka     apic_check_pic(s);
5823db3659bSJan Kiszka 
583574bbf7bSbellard     apic_update_irq(s);
5843db3659bSJan Kiszka 
585574bbf7bSbellard     return intno;
586574bbf7bSbellard }
587574bbf7bSbellard 
58892a16d7aSBlue Swirl int apic_accept_pic_intr(DeviceState *d)
5890e21e12bSths {
590dae01685SJan Kiszka     APICCommonState *s = DO_UPCAST(APICCommonState, busdev.qdev, d);
5910e21e12bSths     uint32_t lvt0;
5920e21e12bSths 
5930e21e12bSths     if (!s)
5940e21e12bSths         return -1;
5950e21e12bSths 
5960e21e12bSths     lvt0 = s->lvt[APIC_LVT_LINT0];
5970e21e12bSths 
598a5b38b51Saurel32     if ((s->apicbase & MSR_IA32_APICBASE_ENABLE) == 0 ||
599a5b38b51Saurel32         (lvt0 & APIC_LVT_MASKED) == 0)
6000e21e12bSths         return 1;
6010e21e12bSths 
6020e21e12bSths     return 0;
6030e21e12bSths }
6040e21e12bSths 
605dae01685SJan Kiszka static uint32_t apic_get_current_count(APICCommonState *s)
606574bbf7bSbellard {
607574bbf7bSbellard     int64_t d;
608574bbf7bSbellard     uint32_t val;
60974475455SPaolo Bonzini     d = (qemu_get_clock_ns(vm_clock) - s->initial_count_load_time) >>
610574bbf7bSbellard         s->count_shift;
611574bbf7bSbellard     if (s->lvt[APIC_LVT_TIMER] & APIC_LVT_TIMER_PERIODIC) {
612574bbf7bSbellard         /* periodic */
613d592d303Sbellard         val = s->initial_count - (d % ((uint64_t)s->initial_count + 1));
614574bbf7bSbellard     } else {
615574bbf7bSbellard         if (d >= s->initial_count)
616574bbf7bSbellard             val = 0;
617574bbf7bSbellard         else
618574bbf7bSbellard             val = s->initial_count - d;
619574bbf7bSbellard     }
620574bbf7bSbellard     return val;
621574bbf7bSbellard }
622574bbf7bSbellard 
623dae01685SJan Kiszka static void apic_timer_update(APICCommonState *s, int64_t current_time)
624574bbf7bSbellard {
6257a380ca3SJan Kiszka     if (apic_next_timer(s, current_time)) {
6267a380ca3SJan Kiszka         qemu_mod_timer(s->timer, s->next_time);
627574bbf7bSbellard     } else {
628574bbf7bSbellard         qemu_del_timer(s->timer);
629574bbf7bSbellard     }
630574bbf7bSbellard }
631574bbf7bSbellard 
632574bbf7bSbellard static void apic_timer(void *opaque)
633574bbf7bSbellard {
634dae01685SJan Kiszka     APICCommonState *s = opaque;
635574bbf7bSbellard 
636cf6d64bfSBlue Swirl     apic_local_deliver(s, APIC_LVT_TIMER);
637574bbf7bSbellard     apic_timer_update(s, s->next_time);
638574bbf7bSbellard }
639574bbf7bSbellard 
640a8170e5eSAvi Kivity static uint32_t apic_mem_readb(void *opaque, hwaddr addr)
641574bbf7bSbellard {
642574bbf7bSbellard     return 0;
643574bbf7bSbellard }
644574bbf7bSbellard 
645a8170e5eSAvi Kivity static uint32_t apic_mem_readw(void *opaque, hwaddr addr)
646574bbf7bSbellard {
647574bbf7bSbellard     return 0;
648574bbf7bSbellard }
649574bbf7bSbellard 
650a8170e5eSAvi Kivity static void apic_mem_writeb(void *opaque, hwaddr addr, uint32_t val)
651574bbf7bSbellard {
652574bbf7bSbellard }
653574bbf7bSbellard 
654a8170e5eSAvi Kivity static void apic_mem_writew(void *opaque, hwaddr addr, uint32_t val)
655574bbf7bSbellard {
656574bbf7bSbellard }
657574bbf7bSbellard 
658a8170e5eSAvi Kivity static uint32_t apic_mem_readl(void *opaque, hwaddr addr)
659574bbf7bSbellard {
66092a16d7aSBlue Swirl     DeviceState *d;
661dae01685SJan Kiszka     APICCommonState *s;
662574bbf7bSbellard     uint32_t val;
663574bbf7bSbellard     int index;
664574bbf7bSbellard 
66592a16d7aSBlue Swirl     d = cpu_get_current_apic();
66692a16d7aSBlue Swirl     if (!d) {
667574bbf7bSbellard         return 0;
6680e26b7b8SBlue Swirl     }
669dae01685SJan Kiszka     s = DO_UPCAST(APICCommonState, busdev.qdev, d);
670574bbf7bSbellard 
671574bbf7bSbellard     index = (addr >> 4) & 0xff;
672574bbf7bSbellard     switch(index) {
673574bbf7bSbellard     case 0x02: /* id */
674574bbf7bSbellard         val = s->id << 24;
675574bbf7bSbellard         break;
676574bbf7bSbellard     case 0x03: /* version */
677574bbf7bSbellard         val = 0x11 | ((APIC_LVT_NB - 1) << 16); /* version 0x11 */
678574bbf7bSbellard         break;
679574bbf7bSbellard     case 0x08:
680e5ad936bSJan Kiszka         apic_sync_vapic(s, SYNC_FROM_VAPIC);
681e5ad936bSJan Kiszka         if (apic_report_tpr_access) {
68260671e58SAndreas Färber             cpu_report_tpr_access(&s->cpu->env, TPR_ACCESS_READ);
683e5ad936bSJan Kiszka         }
684574bbf7bSbellard         val = s->tpr;
685574bbf7bSbellard         break;
686d592d303Sbellard     case 0x09:
687d592d303Sbellard         val = apic_get_arb_pri(s);
688d592d303Sbellard         break;
689574bbf7bSbellard     case 0x0a:
690574bbf7bSbellard         /* ppr */
691574bbf7bSbellard         val = apic_get_ppr(s);
692574bbf7bSbellard         break;
693b237db36Saurel32     case 0x0b:
694b237db36Saurel32         val = 0;
695b237db36Saurel32         break;
696d592d303Sbellard     case 0x0d:
697d592d303Sbellard         val = s->log_dest << 24;
698d592d303Sbellard         break;
699d592d303Sbellard     case 0x0e:
700d592d303Sbellard         val = s->dest_mode << 28;
701d592d303Sbellard         break;
702574bbf7bSbellard     case 0x0f:
703574bbf7bSbellard         val = s->spurious_vec;
704574bbf7bSbellard         break;
705574bbf7bSbellard     case 0x10 ... 0x17:
706574bbf7bSbellard         val = s->isr[index & 7];
707574bbf7bSbellard         break;
708574bbf7bSbellard     case 0x18 ... 0x1f:
709574bbf7bSbellard         val = s->tmr[index & 7];
710574bbf7bSbellard         break;
711574bbf7bSbellard     case 0x20 ... 0x27:
712574bbf7bSbellard         val = s->irr[index & 7];
713574bbf7bSbellard         break;
714574bbf7bSbellard     case 0x28:
715574bbf7bSbellard         val = s->esr;
716574bbf7bSbellard         break;
717574bbf7bSbellard     case 0x30:
718574bbf7bSbellard     case 0x31:
719574bbf7bSbellard         val = s->icr[index & 1];
720574bbf7bSbellard         break;
721e0fd8781Sbellard     case 0x32 ... 0x37:
722e0fd8781Sbellard         val = s->lvt[index - 0x32];
723e0fd8781Sbellard         break;
724574bbf7bSbellard     case 0x38:
725574bbf7bSbellard         val = s->initial_count;
726574bbf7bSbellard         break;
727574bbf7bSbellard     case 0x39:
728574bbf7bSbellard         val = apic_get_current_count(s);
729574bbf7bSbellard         break;
730574bbf7bSbellard     case 0x3e:
731574bbf7bSbellard         val = s->divide_conf;
732574bbf7bSbellard         break;
733574bbf7bSbellard     default:
734574bbf7bSbellard         s->esr |= ESR_ILLEGAL_ADDRESS;
735574bbf7bSbellard         val = 0;
736574bbf7bSbellard         break;
737574bbf7bSbellard     }
738d8023f31SBlue Swirl     trace_apic_mem_readl(addr, val);
739574bbf7bSbellard     return val;
740574bbf7bSbellard }
741574bbf7bSbellard 
742a8170e5eSAvi Kivity static void apic_send_msi(hwaddr addr, uint32_t data)
74354c96da7SMichael S. Tsirkin {
74454c96da7SMichael S. Tsirkin     uint8_t dest = (addr & MSI_ADDR_DEST_ID_MASK) >> MSI_ADDR_DEST_ID_SHIFT;
74554c96da7SMichael S. Tsirkin     uint8_t vector = (data & MSI_DATA_VECTOR_MASK) >> MSI_DATA_VECTOR_SHIFT;
74654c96da7SMichael S. Tsirkin     uint8_t dest_mode = (addr >> MSI_ADDR_DEST_MODE_SHIFT) & 0x1;
74754c96da7SMichael S. Tsirkin     uint8_t trigger_mode = (data >> MSI_DATA_TRIGGER_SHIFT) & 0x1;
74854c96da7SMichael S. Tsirkin     uint8_t delivery = (data >> MSI_DATA_DELIVERY_MODE_SHIFT) & 0x7;
74954c96da7SMichael S. Tsirkin     /* XXX: Ignore redirection hint. */
7501f6f408cSJan Kiszka     apic_deliver_irq(dest, dest_mode, delivery, vector, trigger_mode);
75154c96da7SMichael S. Tsirkin }
75254c96da7SMichael S. Tsirkin 
753a8170e5eSAvi Kivity static void apic_mem_writel(void *opaque, hwaddr addr, uint32_t val)
754574bbf7bSbellard {
75592a16d7aSBlue Swirl     DeviceState *d;
756dae01685SJan Kiszka     APICCommonState *s;
75754c96da7SMichael S. Tsirkin     int index = (addr >> 4) & 0xff;
75854c96da7SMichael S. Tsirkin     if (addr > 0xfff || !index) {
75954c96da7SMichael S. Tsirkin         /* MSI and MMIO APIC are at the same memory location,
76054c96da7SMichael S. Tsirkin          * but actually not on the global bus: MSI is on PCI bus
76154c96da7SMichael S. Tsirkin          * APIC is connected directly to the CPU.
76254c96da7SMichael S. Tsirkin          * Mapping them on the global bus happens to work because
76354c96da7SMichael S. Tsirkin          * MSI registers are reserved in APIC MMIO and vice versa. */
76454c96da7SMichael S. Tsirkin         apic_send_msi(addr, val);
76554c96da7SMichael S. Tsirkin         return;
76654c96da7SMichael S. Tsirkin     }
767574bbf7bSbellard 
76892a16d7aSBlue Swirl     d = cpu_get_current_apic();
76992a16d7aSBlue Swirl     if (!d) {
770574bbf7bSbellard         return;
7710e26b7b8SBlue Swirl     }
772dae01685SJan Kiszka     s = DO_UPCAST(APICCommonState, busdev.qdev, d);
773574bbf7bSbellard 
774d8023f31SBlue Swirl     trace_apic_mem_writel(addr, val);
775574bbf7bSbellard 
776574bbf7bSbellard     switch(index) {
777574bbf7bSbellard     case 0x02:
778574bbf7bSbellard         s->id = (val >> 24);
779574bbf7bSbellard         break;
780e0fd8781Sbellard     case 0x03:
781e0fd8781Sbellard         break;
782574bbf7bSbellard     case 0x08:
783e5ad936bSJan Kiszka         if (apic_report_tpr_access) {
78460671e58SAndreas Färber             cpu_report_tpr_access(&s->cpu->env, TPR_ACCESS_WRITE);
785e5ad936bSJan Kiszka         }
786574bbf7bSbellard         s->tpr = val;
787e5ad936bSJan Kiszka         apic_sync_vapic(s, SYNC_TO_VAPIC);
788d592d303Sbellard         apic_update_irq(s);
789574bbf7bSbellard         break;
790e0fd8781Sbellard     case 0x09:
791e0fd8781Sbellard     case 0x0a:
792e0fd8781Sbellard         break;
793574bbf7bSbellard     case 0x0b: /* EOI */
794574bbf7bSbellard         apic_eoi(s);
795574bbf7bSbellard         break;
796d592d303Sbellard     case 0x0d:
797d592d303Sbellard         s->log_dest = val >> 24;
798d592d303Sbellard         break;
799d592d303Sbellard     case 0x0e:
800d592d303Sbellard         s->dest_mode = val >> 28;
801d592d303Sbellard         break;
802574bbf7bSbellard     case 0x0f:
803574bbf7bSbellard         s->spurious_vec = val & 0x1ff;
804d592d303Sbellard         apic_update_irq(s);
805574bbf7bSbellard         break;
806e0fd8781Sbellard     case 0x10 ... 0x17:
807e0fd8781Sbellard     case 0x18 ... 0x1f:
808e0fd8781Sbellard     case 0x20 ... 0x27:
809e0fd8781Sbellard     case 0x28:
810e0fd8781Sbellard         break;
811574bbf7bSbellard     case 0x30:
812d592d303Sbellard         s->icr[0] = val;
81392a16d7aSBlue Swirl         apic_deliver(d, (s->icr[1] >> 24) & 0xff, (s->icr[0] >> 11) & 1,
814d592d303Sbellard                      (s->icr[0] >> 8) & 7, (s->icr[0] & 0xff),
8151f6f408cSJan Kiszka                      (s->icr[0] >> 15) & 1);
816d592d303Sbellard         break;
817574bbf7bSbellard     case 0x31:
818d592d303Sbellard         s->icr[1] = val;
819574bbf7bSbellard         break;
820574bbf7bSbellard     case 0x32 ... 0x37:
821574bbf7bSbellard         {
822574bbf7bSbellard             int n = index - 0x32;
823574bbf7bSbellard             s->lvt[n] = val;
824a94820ddSJan Kiszka             if (n == APIC_LVT_TIMER) {
82574475455SPaolo Bonzini                 apic_timer_update(s, qemu_get_clock_ns(vm_clock));
826a94820ddSJan Kiszka             } else if (n == APIC_LVT_LINT0 && apic_check_pic(s)) {
827a94820ddSJan Kiszka                 apic_update_irq(s);
828a94820ddSJan Kiszka             }
829574bbf7bSbellard         }
830574bbf7bSbellard         break;
831574bbf7bSbellard     case 0x38:
832574bbf7bSbellard         s->initial_count = val;
83374475455SPaolo Bonzini         s->initial_count_load_time = qemu_get_clock_ns(vm_clock);
834574bbf7bSbellard         apic_timer_update(s, s->initial_count_load_time);
835574bbf7bSbellard         break;
836e0fd8781Sbellard     case 0x39:
837e0fd8781Sbellard         break;
838574bbf7bSbellard     case 0x3e:
839574bbf7bSbellard         {
840574bbf7bSbellard             int v;
841574bbf7bSbellard             s->divide_conf = val & 0xb;
842574bbf7bSbellard             v = (s->divide_conf & 3) | ((s->divide_conf >> 1) & 4);
843574bbf7bSbellard             s->count_shift = (v + 1) & 7;
844574bbf7bSbellard         }
845574bbf7bSbellard         break;
846574bbf7bSbellard     default:
847574bbf7bSbellard         s->esr |= ESR_ILLEGAL_ADDRESS;
848574bbf7bSbellard         break;
849574bbf7bSbellard     }
850574bbf7bSbellard }
851574bbf7bSbellard 
852e5ad936bSJan Kiszka static void apic_pre_save(APICCommonState *s)
853e5ad936bSJan Kiszka {
854e5ad936bSJan Kiszka     apic_sync_vapic(s, SYNC_FROM_VAPIC);
855e5ad936bSJan Kiszka }
856e5ad936bSJan Kiszka 
8577a380ca3SJan Kiszka static void apic_post_load(APICCommonState *s)
8587a380ca3SJan Kiszka {
8597a380ca3SJan Kiszka     if (s->timer_expiry != -1) {
8607a380ca3SJan Kiszka         qemu_mod_timer(s->timer, s->timer_expiry);
8617a380ca3SJan Kiszka     } else {
8627a380ca3SJan Kiszka         qemu_del_timer(s->timer);
8637a380ca3SJan Kiszka     }
8647a380ca3SJan Kiszka }
8657a380ca3SJan Kiszka 
866312b4234SAvi Kivity static const MemoryRegionOps apic_io_ops = {
867312b4234SAvi Kivity     .old_mmio = {
868312b4234SAvi Kivity         .read = { apic_mem_readb, apic_mem_readw, apic_mem_readl, },
869312b4234SAvi Kivity         .write = { apic_mem_writeb, apic_mem_writew, apic_mem_writel, },
870312b4234SAvi Kivity     },
871312b4234SAvi Kivity     .endianness = DEVICE_NATIVE_ENDIAN,
872574bbf7bSbellard };
873574bbf7bSbellard 
874dae01685SJan Kiszka static void apic_init(APICCommonState *s)
8758546b099SBlue Swirl {
876*1437c94bSPaolo Bonzini     memory_region_init_io(&s->io_memory, OBJECT(s), &apic_io_ops, s, "apic-msi",
877baaeda08SIgor Mammedov                           APIC_SPACE_SIZE);
8788546b099SBlue Swirl 
87974475455SPaolo Bonzini     s->timer = qemu_new_timer_ns(vm_clock, apic_timer, s);
8808546b099SBlue Swirl     local_apics[s->idx] = s;
88108a82ac0SJan Kiszka 
88208a82ac0SJan Kiszka     msi_supported = true;
8838546b099SBlue Swirl }
8848546b099SBlue Swirl 
885999e12bbSAnthony Liguori static void apic_class_init(ObjectClass *klass, void *data)
886999e12bbSAnthony Liguori {
887999e12bbSAnthony Liguori     APICCommonClass *k = APIC_COMMON_CLASS(klass);
888999e12bbSAnthony Liguori 
889999e12bbSAnthony Liguori     k->init = apic_init;
890999e12bbSAnthony Liguori     k->set_base = apic_set_base;
891999e12bbSAnthony Liguori     k->set_tpr = apic_set_tpr;
892e5ad936bSJan Kiszka     k->get_tpr = apic_get_tpr;
893e5ad936bSJan Kiszka     k->vapic_base_update = apic_vapic_base_update;
894999e12bbSAnthony Liguori     k->external_nmi = apic_external_nmi;
895e5ad936bSJan Kiszka     k->pre_save = apic_pre_save;
896999e12bbSAnthony Liguori     k->post_load = apic_post_load;
897999e12bbSAnthony Liguori }
898999e12bbSAnthony Liguori 
8998c43a6f0SAndreas Färber static const TypeInfo apic_info = {
900999e12bbSAnthony Liguori     .name          = "apic",
90139bffca2SAnthony Liguori     .instance_size = sizeof(APICCommonState),
90239bffca2SAnthony Liguori     .parent        = TYPE_APIC_COMMON,
903999e12bbSAnthony Liguori     .class_init    = apic_class_init,
9048546b099SBlue Swirl };
9058546b099SBlue Swirl 
90683f7d43aSAndreas Färber static void apic_register_types(void)
9078546b099SBlue Swirl {
90839bffca2SAnthony Liguori     type_register_static(&apic_info);
9098546b099SBlue Swirl }
9108546b099SBlue Swirl 
91183f7d43aSAndreas Färber type_init(apic_register_types)
912