1 /* 2 * Allwinner A10 interrupt controller device emulation 3 * 4 * Copyright (C) 2013 Li Guang 5 * Written by Li Guang <lig.fnst@cn.fujitsu.com> 6 * 7 * This program is free software; you can redistribute it and/or modify it 8 * under the terms of the GNU General Public License as published by the 9 * Free Software Foundation; either version 2 of the License, or 10 * (at your option) any later version. 11 * 12 * This program is distributed in the hope that it will be useful, but WITHOUT 13 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 14 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License 15 * for more details. 16 */ 17 18 #include "hw/sysbus.h" 19 #include "hw/devices.h" 20 #include "sysemu/sysemu.h" 21 #include "hw/intc/allwinner-a10-pic.h" 22 23 static void aw_a10_pic_update(AwA10PICState *s) 24 { 25 uint8_t i; 26 int irq = 0, fiq = 0, pending; 27 28 s->vector = 0; 29 30 for (i = 0; i < AW_A10_PIC_REG_NUM; i++) { 31 irq |= s->irq_pending[i] & ~s->mask[i]; 32 fiq |= s->select[i] & s->irq_pending[i] & ~s->mask[i]; 33 34 if (!s->vector) { 35 pending = ffs(s->irq_pending[i] & ~s->mask[i]); 36 if (pending) { 37 s->vector = (i * 32 + pending - 1) * 4; 38 } 39 } 40 } 41 42 qemu_set_irq(s->parent_irq, !!irq); 43 qemu_set_irq(s->parent_fiq, !!fiq); 44 } 45 46 static void aw_a10_pic_set_irq(void *opaque, int irq, int level) 47 { 48 AwA10PICState *s = opaque; 49 50 if (level) { 51 set_bit(irq % 32, (void *)&s->irq_pending[irq / 32]); 52 } 53 aw_a10_pic_update(s); 54 } 55 56 static uint64_t aw_a10_pic_read(void *opaque, hwaddr offset, unsigned size) 57 { 58 AwA10PICState *s = opaque; 59 uint8_t index = (offset & 0xc) / 4; 60 61 switch (offset) { 62 case AW_A10_PIC_VECTOR: 63 return s->vector; 64 case AW_A10_PIC_BASE_ADDR: 65 return s->base_addr; 66 case AW_A10_PIC_PROTECT: 67 return s->protect; 68 case AW_A10_PIC_NMI: 69 return s->nmi; 70 case AW_A10_PIC_IRQ_PENDING ... AW_A10_PIC_IRQ_PENDING + 8: 71 return s->irq_pending[index]; 72 case AW_A10_PIC_FIQ_PENDING ... AW_A10_PIC_FIQ_PENDING + 8: 73 return s->fiq_pending[index]; 74 case AW_A10_PIC_SELECT ... AW_A10_PIC_SELECT + 8: 75 return s->select[index]; 76 case AW_A10_PIC_ENABLE ... AW_A10_PIC_ENABLE + 8: 77 return s->enable[index]; 78 case AW_A10_PIC_MASK ... AW_A10_PIC_MASK + 8: 79 return s->mask[index]; 80 default: 81 qemu_log_mask(LOG_GUEST_ERROR, 82 "%s: Bad offset 0x%x\n", __func__, (int)offset); 83 break; 84 } 85 86 return 0; 87 } 88 89 static void aw_a10_pic_write(void *opaque, hwaddr offset, uint64_t value, 90 unsigned size) 91 { 92 AwA10PICState *s = opaque; 93 uint8_t index = (offset & 0xc) / 4; 94 95 switch (offset) { 96 case AW_A10_PIC_BASE_ADDR: 97 s->base_addr = value & ~0x3; 98 case AW_A10_PIC_PROTECT: 99 s->protect = value; 100 break; 101 case AW_A10_PIC_NMI: 102 s->nmi = value; 103 break; 104 case AW_A10_PIC_IRQ_PENDING ... AW_A10_PIC_IRQ_PENDING + 8: 105 s->irq_pending[index] &= ~value; 106 break; 107 case AW_A10_PIC_FIQ_PENDING ... AW_A10_PIC_FIQ_PENDING + 8: 108 s->fiq_pending[index] &= ~value; 109 break; 110 case AW_A10_PIC_SELECT ... AW_A10_PIC_SELECT + 8: 111 s->select[index] = value; 112 break; 113 case AW_A10_PIC_ENABLE ... AW_A10_PIC_ENABLE + 8: 114 s->enable[index] = value; 115 break; 116 case AW_A10_PIC_MASK ... AW_A10_PIC_MASK + 8: 117 s->mask[index] = value; 118 break; 119 default: 120 qemu_log_mask(LOG_GUEST_ERROR, 121 "%s: Bad offset 0x%x\n", __func__, (int)offset); 122 break; 123 } 124 125 aw_a10_pic_update(s); 126 } 127 128 static const MemoryRegionOps aw_a10_pic_ops = { 129 .read = aw_a10_pic_read, 130 .write = aw_a10_pic_write, 131 .endianness = DEVICE_NATIVE_ENDIAN, 132 }; 133 134 static const VMStateDescription vmstate_aw_a10_pic = { 135 .name = "a10.pic", 136 .version_id = 1, 137 .minimum_version_id = 1, 138 .minimum_version_id_old = 1, 139 .fields = (VMStateField[]) { 140 VMSTATE_UINT32(vector, AwA10PICState), 141 VMSTATE_UINT32(base_addr, AwA10PICState), 142 VMSTATE_UINT32(protect, AwA10PICState), 143 VMSTATE_UINT32(nmi, AwA10PICState), 144 VMSTATE_UINT32_ARRAY(irq_pending, AwA10PICState, AW_A10_PIC_REG_NUM), 145 VMSTATE_UINT32_ARRAY(fiq_pending, AwA10PICState, AW_A10_PIC_REG_NUM), 146 VMSTATE_UINT32_ARRAY(enable, AwA10PICState, AW_A10_PIC_REG_NUM), 147 VMSTATE_UINT32_ARRAY(select, AwA10PICState, AW_A10_PIC_REG_NUM), 148 VMSTATE_UINT32_ARRAY(mask, AwA10PICState, AW_A10_PIC_REG_NUM), 149 VMSTATE_END_OF_LIST() 150 } 151 }; 152 153 static void aw_a10_pic_init(Object *obj) 154 { 155 AwA10PICState *s = AW_A10_PIC(obj); 156 SysBusDevice *dev = SYS_BUS_DEVICE(obj); 157 158 qdev_init_gpio_in(DEVICE(dev), aw_a10_pic_set_irq, AW_A10_PIC_INT_NR); 159 sysbus_init_irq(dev, &s->parent_irq); 160 sysbus_init_irq(dev, &s->parent_fiq); 161 memory_region_init_io(&s->iomem, OBJECT(s), &aw_a10_pic_ops, s, 162 TYPE_AW_A10_PIC, 0x400); 163 sysbus_init_mmio(dev, &s->iomem); 164 } 165 166 static void aw_a10_pic_reset(DeviceState *d) 167 { 168 AwA10PICState *s = AW_A10_PIC(d); 169 uint8_t i; 170 171 s->base_addr = 0; 172 s->protect = 0; 173 s->nmi = 0; 174 s->vector = 0; 175 for (i = 0; i < AW_A10_PIC_REG_NUM; i++) { 176 s->irq_pending[i] = 0; 177 s->fiq_pending[i] = 0; 178 s->select[i] = 0; 179 s->enable[i] = 0; 180 s->mask[i] = 0; 181 } 182 } 183 184 static void aw_a10_pic_class_init(ObjectClass *klass, void *data) 185 { 186 DeviceClass *dc = DEVICE_CLASS(klass); 187 188 dc->reset = aw_a10_pic_reset; 189 dc->desc = "allwinner a10 pic"; 190 dc->vmsd = &vmstate_aw_a10_pic; 191 } 192 193 static const TypeInfo aw_a10_pic_info = { 194 .name = TYPE_AW_A10_PIC, 195 .parent = TYPE_SYS_BUS_DEVICE, 196 .instance_size = sizeof(AwA10PICState), 197 .instance_init = aw_a10_pic_init, 198 .class_init = aw_a10_pic_class_init, 199 }; 200 201 static void aw_a10_register_types(void) 202 { 203 type_register_static(&aw_a10_pic_info); 204 } 205 206 type_init(aw_a10_register_types); 207