1 /* 2 * QEMU HP Lasi PS/2 interface emulation 3 * 4 * Copyright (c) 2019 Sven Schnelle 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a copy 7 * of this software and associated documentation files (the "Software"), to deal 8 * in the Software without restriction, including without limitation the rights 9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 10 * copies of the Software, and to permit persons to whom the Software is 11 * furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice shall be included in 14 * all copies or substantial portions of the Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN 22 * THE SOFTWARE. 23 */ 24 #include "qemu/osdep.h" 25 #include "qemu/log.h" 26 #include "hw/qdev-properties.h" 27 #include "hw/input/ps2.h" 28 #include "hw/input/lasips2.h" 29 #include "hw/sysbus.h" 30 #include "exec/hwaddr.h" 31 #include "sysemu/sysemu.h" 32 #include "trace.h" 33 #include "exec/address-spaces.h" 34 #include "migration/vmstate.h" 35 #include "hw/irq.h" 36 37 38 struct LASIPS2State; 39 typedef struct LASIPS2Port { 40 struct LASIPS2State *parent; 41 MemoryRegion reg; 42 void *dev; 43 uint8_t id; 44 uint8_t control; 45 uint8_t buf; 46 bool loopback_rbne; 47 bool irq; 48 } LASIPS2Port; 49 50 typedef struct LASIPS2State { 51 LASIPS2Port kbd; 52 LASIPS2Port mouse; 53 qemu_irq irq; 54 } LASIPS2State; 55 56 static const VMStateDescription vmstate_lasips2 = { 57 .name = "lasips2", 58 .version_id = 0, 59 .minimum_version_id = 0, 60 .fields = (VMStateField[]) { 61 VMSTATE_UINT8(kbd.control, LASIPS2State), 62 VMSTATE_UINT8(kbd.id, LASIPS2State), 63 VMSTATE_BOOL(kbd.irq, LASIPS2State), 64 VMSTATE_UINT8(mouse.control, LASIPS2State), 65 VMSTATE_UINT8(mouse.id, LASIPS2State), 66 VMSTATE_BOOL(mouse.irq, LASIPS2State), 67 VMSTATE_END_OF_LIST() 68 } 69 }; 70 71 typedef enum { 72 REG_PS2_ID = 0, 73 REG_PS2_RCVDATA = 4, 74 REG_PS2_CONTROL = 8, 75 REG_PS2_STATUS = 12, 76 } lasips2_read_reg_t; 77 78 typedef enum { 79 REG_PS2_RESET = 0, 80 REG_PS2_XMTDATA = 4, 81 } lasips2_write_reg_t; 82 83 typedef enum { 84 LASIPS2_CONTROL_ENABLE = 0x01, 85 LASIPS2_CONTROL_LOOPBACK = 0x02, 86 LASIPS2_CONTROL_DIAG = 0x20, 87 LASIPS2_CONTROL_DATDIR = 0x40, 88 LASIPS2_CONTROL_CLKDIR = 0x80, 89 } lasips2_control_reg_t; 90 91 typedef enum { 92 LASIPS2_STATUS_RBNE = 0x01, 93 LASIPS2_STATUS_TBNE = 0x02, 94 LASIPS2_STATUS_TERR = 0x04, 95 LASIPS2_STATUS_PERR = 0x08, 96 LASIPS2_STATUS_CMPINTR = 0x10, 97 LASIPS2_STATUS_DATSHD = 0x40, 98 LASIPS2_STATUS_CLKSHD = 0x80, 99 } lasips2_status_reg_t; 100 101 static const char *artist_read_reg_name(uint64_t addr) 102 { 103 switch (addr & 0xc) { 104 case REG_PS2_ID: 105 return " PS2_ID"; 106 107 case REG_PS2_RCVDATA: 108 return " PS2_RCVDATA"; 109 110 case REG_PS2_CONTROL: 111 return " PS2_CONTROL"; 112 113 case REG_PS2_STATUS: 114 return " PS2_STATUS"; 115 116 default: 117 return ""; 118 } 119 } 120 121 static const char *artist_write_reg_name(uint64_t addr) 122 { 123 switch (addr & 0x0c) { 124 case REG_PS2_RESET: 125 return " PS2_RESET"; 126 127 case REG_PS2_XMTDATA: 128 return " PS2_XMTDATA"; 129 130 case REG_PS2_CONTROL: 131 return " PS2_CONTROL"; 132 133 default: 134 return ""; 135 } 136 } 137 138 static void lasips2_update_irq(LASIPS2State *s) 139 { 140 trace_lasips2_intr(s->kbd.irq | s->mouse.irq); 141 qemu_set_irq(s->irq, s->kbd.irq | s->mouse.irq); 142 } 143 144 static void lasips2_reg_write(void *opaque, hwaddr addr, uint64_t val, 145 unsigned size) 146 { 147 LASIPS2Port *port = opaque; 148 149 trace_lasips2_reg_write(size, port->id, addr, 150 artist_write_reg_name(addr), val); 151 152 switch (addr & 0xc) { 153 case REG_PS2_CONTROL: 154 port->control = val; 155 break; 156 157 case REG_PS2_XMTDATA: 158 if (port->control & LASIPS2_CONTROL_LOOPBACK) { 159 port->buf = val; 160 port->irq = true; 161 port->loopback_rbne = true; 162 lasips2_update_irq(port->parent); 163 break; 164 } 165 166 if (port->id) { 167 ps2_write_mouse(port->dev, val); 168 } else { 169 ps2_write_keyboard(port->dev, val); 170 } 171 break; 172 173 case REG_PS2_RESET: 174 break; 175 176 default: 177 qemu_log_mask(LOG_UNIMP, "%s: unknown register 0x%02" HWADDR_PRIx "\n", 178 __func__, addr); 179 break; 180 } 181 } 182 183 static uint64_t lasips2_reg_read(void *opaque, hwaddr addr, unsigned size) 184 { 185 LASIPS2Port *port = opaque; 186 uint64_t ret = 0; 187 188 switch (addr & 0xc) { 189 case REG_PS2_ID: 190 ret = port->id; 191 break; 192 193 case REG_PS2_RCVDATA: 194 if (port->control & LASIPS2_CONTROL_LOOPBACK) { 195 port->irq = false; 196 port->loopback_rbne = false; 197 lasips2_update_irq(port->parent); 198 ret = port->buf; 199 break; 200 } 201 202 ret = ps2_read_data(port->dev); 203 break; 204 205 case REG_PS2_CONTROL: 206 ret = port->control; 207 break; 208 209 case REG_PS2_STATUS: 210 211 ret = LASIPS2_STATUS_DATSHD | LASIPS2_STATUS_CLKSHD; 212 213 if (port->control & LASIPS2_CONTROL_DIAG) { 214 if (!(port->control & LASIPS2_CONTROL_DATDIR)) { 215 ret &= ~LASIPS2_STATUS_DATSHD; 216 } 217 218 if (!(port->control & LASIPS2_CONTROL_CLKDIR)) { 219 ret &= ~LASIPS2_STATUS_CLKSHD; 220 } 221 } 222 223 if (port->control & LASIPS2_CONTROL_LOOPBACK) { 224 if (port->loopback_rbne) { 225 ret |= LASIPS2_STATUS_RBNE; 226 } 227 } else { 228 if (!ps2_queue_empty(port->dev)) { 229 ret |= LASIPS2_STATUS_RBNE; 230 } 231 } 232 233 if (port->parent->kbd.irq || port->parent->mouse.irq) { 234 ret |= LASIPS2_STATUS_CMPINTR; 235 } 236 break; 237 238 default: 239 qemu_log_mask(LOG_UNIMP, "%s: unknown register 0x%02" HWADDR_PRIx "\n", 240 __func__, addr); 241 break; 242 } 243 trace_lasips2_reg_read(size, port->id, addr, 244 artist_read_reg_name(addr), ret); 245 246 return ret; 247 } 248 249 static const MemoryRegionOps lasips2_reg_ops = { 250 .read = lasips2_reg_read, 251 .write = lasips2_reg_write, 252 .impl = { 253 .min_access_size = 1, 254 .max_access_size = 4, 255 }, 256 .endianness = DEVICE_NATIVE_ENDIAN, 257 }; 258 259 static void ps2dev_update_irq(void *opaque, int level) 260 { 261 LASIPS2Port *port = opaque; 262 port->irq = level; 263 lasips2_update_irq(port->parent); 264 } 265 266 void lasips2_init(MemoryRegion *address_space, 267 hwaddr base, qemu_irq irq) 268 { 269 LASIPS2State *s; 270 271 s = g_malloc0(sizeof(LASIPS2State)); 272 273 s->irq = irq; 274 s->mouse.id = 1; 275 s->kbd.parent = s; 276 s->mouse.parent = s; 277 278 vmstate_register(NULL, base, &vmstate_lasips2, s); 279 280 s->kbd.dev = ps2_kbd_init(ps2dev_update_irq, &s->kbd); 281 s->mouse.dev = ps2_mouse_init(ps2dev_update_irq, &s->mouse); 282 283 memory_region_init_io(&s->kbd.reg, NULL, &lasips2_reg_ops, &s->kbd, 284 "lasips2-kbd", 0x100); 285 memory_region_add_subregion(address_space, base, &s->kbd.reg); 286 287 memory_region_init_io(&s->mouse.reg, NULL, &lasips2_reg_ops, &s->mouse, 288 "lasips2-mouse", 0x100); 289 memory_region_add_subregion(address_space, base + 0x100, &s->mouse.reg); 290 } 291