1 /* 2 * QEMU HP Lasi PS/2 interface emulation 3 * 4 * Copyright (c) 2019 Sven Schnelle 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a copy 7 * of this software and associated documentation files (the "Software"), to deal 8 * in the Software without restriction, including without limitation the rights 9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 10 * copies of the Software, and to permit persons to whom the Software is 11 * furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice shall be included in 14 * all copies or substantial portions of the Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN 22 * THE SOFTWARE. 23 */ 24 #include "qemu/osdep.h" 25 #include "qemu/log.h" 26 #include "hw/qdev-properties.h" 27 #include "hw/sysbus.h" 28 #include "hw/input/ps2.h" 29 #include "hw/input/lasips2.h" 30 #include "exec/hwaddr.h" 31 #include "trace.h" 32 #include "exec/address-spaces.h" 33 #include "migration/vmstate.h" 34 #include "hw/irq.h" 35 #include "qapi/error.h" 36 37 38 static const VMStateDescription vmstate_lasips2 = { 39 .name = "lasips2", 40 .version_id = 0, 41 .minimum_version_id = 0, 42 .fields = (VMStateField[]) { 43 VMSTATE_UINT8(kbd_port.parent_obj.control, LASIPS2State), 44 VMSTATE_UINT8(kbd_port.parent_obj.id, LASIPS2State), 45 VMSTATE_BOOL(kbd_port.parent_obj.birq, LASIPS2State), 46 VMSTATE_UINT8(mouse_port.parent_obj.control, LASIPS2State), 47 VMSTATE_UINT8(mouse_port.parent_obj.id, LASIPS2State), 48 VMSTATE_BOOL(mouse_port.parent_obj.birq, LASIPS2State), 49 VMSTATE_END_OF_LIST() 50 } 51 }; 52 53 typedef enum { 54 REG_PS2_ID = 0, 55 REG_PS2_RCVDATA = 4, 56 REG_PS2_CONTROL = 8, 57 REG_PS2_STATUS = 12, 58 } lasips2_read_reg_t; 59 60 typedef enum { 61 REG_PS2_RESET = 0, 62 REG_PS2_XMTDATA = 4, 63 } lasips2_write_reg_t; 64 65 typedef enum { 66 LASIPS2_CONTROL_ENABLE = 0x01, 67 LASIPS2_CONTROL_LOOPBACK = 0x02, 68 LASIPS2_CONTROL_DIAG = 0x20, 69 LASIPS2_CONTROL_DATDIR = 0x40, 70 LASIPS2_CONTROL_CLKDIR = 0x80, 71 } lasips2_control_reg_t; 72 73 typedef enum { 74 LASIPS2_STATUS_RBNE = 0x01, 75 LASIPS2_STATUS_TBNE = 0x02, 76 LASIPS2_STATUS_TERR = 0x04, 77 LASIPS2_STATUS_PERR = 0x08, 78 LASIPS2_STATUS_CMPINTR = 0x10, 79 LASIPS2_STATUS_DATSHD = 0x40, 80 LASIPS2_STATUS_CLKSHD = 0x80, 81 } lasips2_status_reg_t; 82 83 static const char *lasips2_read_reg_name(uint64_t addr) 84 { 85 switch (addr & 0xc) { 86 case REG_PS2_ID: 87 return " PS2_ID"; 88 89 case REG_PS2_RCVDATA: 90 return " PS2_RCVDATA"; 91 92 case REG_PS2_CONTROL: 93 return " PS2_CONTROL"; 94 95 case REG_PS2_STATUS: 96 return " PS2_STATUS"; 97 98 default: 99 return ""; 100 } 101 } 102 103 static const char *lasips2_write_reg_name(uint64_t addr) 104 { 105 switch (addr & 0x0c) { 106 case REG_PS2_RESET: 107 return " PS2_RESET"; 108 109 case REG_PS2_XMTDATA: 110 return " PS2_XMTDATA"; 111 112 case REG_PS2_CONTROL: 113 return " PS2_CONTROL"; 114 115 default: 116 return ""; 117 } 118 } 119 120 static void lasips2_update_irq(LASIPS2State *s) 121 { 122 trace_lasips2_intr(s->kbd_port.parent_obj.birq | 123 s->mouse_port.parent_obj.birq); 124 qemu_set_irq(s->irq, s->kbd_port.parent_obj.birq | 125 s->mouse_port.parent_obj.birq); 126 } 127 128 static void lasips2_reg_write(void *opaque, hwaddr addr, uint64_t val, 129 unsigned size) 130 { 131 LASIPS2Port *port = opaque; 132 133 trace_lasips2_reg_write(size, port->id, addr, 134 lasips2_write_reg_name(addr), val); 135 136 switch (addr & 0xc) { 137 case REG_PS2_CONTROL: 138 port->control = val; 139 break; 140 141 case REG_PS2_XMTDATA: 142 if (port->control & LASIPS2_CONTROL_LOOPBACK) { 143 port->buf = val; 144 port->birq = true; 145 port->loopback_rbne = true; 146 lasips2_update_irq(port->parent); 147 break; 148 } 149 150 if (port->id) { 151 ps2_write_mouse(PS2_MOUSE_DEVICE(port->ps2dev), val); 152 } else { 153 ps2_write_keyboard(PS2_KBD_DEVICE(port->ps2dev), val); 154 } 155 break; 156 157 case REG_PS2_RESET: 158 break; 159 160 default: 161 qemu_log_mask(LOG_UNIMP, "%s: unknown register 0x%02" HWADDR_PRIx "\n", 162 __func__, addr); 163 break; 164 } 165 } 166 167 static uint64_t lasips2_reg_read(void *opaque, hwaddr addr, unsigned size) 168 { 169 LASIPS2Port *port = opaque; 170 uint64_t ret = 0; 171 172 switch (addr & 0xc) { 173 case REG_PS2_ID: 174 ret = port->id; 175 break; 176 177 case REG_PS2_RCVDATA: 178 if (port->control & LASIPS2_CONTROL_LOOPBACK) { 179 port->birq = false; 180 port->loopback_rbne = false; 181 lasips2_update_irq(port->parent); 182 ret = port->buf; 183 break; 184 } 185 186 ret = ps2_read_data(port->ps2dev); 187 break; 188 189 case REG_PS2_CONTROL: 190 ret = port->control; 191 break; 192 193 case REG_PS2_STATUS: 194 ret = LASIPS2_STATUS_DATSHD | LASIPS2_STATUS_CLKSHD; 195 196 if (port->control & LASIPS2_CONTROL_DIAG) { 197 if (!(port->control & LASIPS2_CONTROL_DATDIR)) { 198 ret &= ~LASIPS2_STATUS_DATSHD; 199 } 200 201 if (!(port->control & LASIPS2_CONTROL_CLKDIR)) { 202 ret &= ~LASIPS2_STATUS_CLKSHD; 203 } 204 } 205 206 if (port->control & LASIPS2_CONTROL_LOOPBACK) { 207 if (port->loopback_rbne) { 208 ret |= LASIPS2_STATUS_RBNE; 209 } 210 } else { 211 if (!ps2_queue_empty(port->ps2dev)) { 212 ret |= LASIPS2_STATUS_RBNE; 213 } 214 } 215 216 if (port->parent->kbd_port.parent_obj.birq || 217 port->parent->mouse_port.parent_obj.birq) { 218 ret |= LASIPS2_STATUS_CMPINTR; 219 } 220 break; 221 222 default: 223 qemu_log_mask(LOG_UNIMP, "%s: unknown register 0x%02" HWADDR_PRIx "\n", 224 __func__, addr); 225 break; 226 } 227 228 trace_lasips2_reg_read(size, port->id, addr, 229 lasips2_read_reg_name(addr), ret); 230 return ret; 231 } 232 233 static const MemoryRegionOps lasips2_reg_ops = { 234 .read = lasips2_reg_read, 235 .write = lasips2_reg_write, 236 .impl = { 237 .min_access_size = 1, 238 .max_access_size = 4, 239 }, 240 .endianness = DEVICE_NATIVE_ENDIAN, 241 }; 242 243 static void lasips2_set_kbd_irq(void *opaque, int n, int level) 244 { 245 LASIPS2State *s = LASIPS2(opaque); 246 LASIPS2Port *port = LASIPS2_PORT(&s->kbd_port); 247 248 port->birq = level; 249 lasips2_update_irq(port->parent); 250 } 251 252 static void lasips2_set_mouse_irq(void *opaque, int n, int level) 253 { 254 LASIPS2State *s = LASIPS2(opaque); 255 LASIPS2Port *port = LASIPS2_PORT(&s->mouse_port); 256 257 port->birq = level; 258 lasips2_update_irq(port->parent); 259 } 260 261 static void lasips2_realize(DeviceState *dev, Error **errp) 262 { 263 LASIPS2State *s = LASIPS2(dev); 264 LASIPS2Port *lp; 265 266 lp = LASIPS2_PORT(&s->kbd_port); 267 if (!(qdev_realize(DEVICE(lp), NULL, errp))) { 268 return; 269 } 270 271 qdev_connect_gpio_out(DEVICE(lp->ps2dev), PS2_DEVICE_IRQ, 272 qdev_get_gpio_in_named(dev, "ps2-kbd-input-irq", 273 0)); 274 275 lp = LASIPS2_PORT(&s->mouse_port); 276 if (!(qdev_realize(DEVICE(lp), NULL, errp))) { 277 return; 278 } 279 280 qdev_connect_gpio_out(DEVICE(lp->ps2dev), PS2_DEVICE_IRQ, 281 qdev_get_gpio_in_named(dev, "ps2-mouse-input-irq", 282 0)); 283 } 284 285 static void lasips2_init(Object *obj) 286 { 287 LASIPS2State *s = LASIPS2(obj); 288 LASIPS2Port *lp; 289 290 object_initialize_child(obj, "lasips2-kbd-port", &s->kbd_port, 291 TYPE_LASIPS2_KBD_PORT); 292 object_initialize_child(obj, "lasips2-mouse-port", &s->mouse_port, 293 TYPE_LASIPS2_MOUSE_PORT); 294 295 lp = LASIPS2_PORT(&s->kbd_port); 296 sysbus_init_mmio(SYS_BUS_DEVICE(obj), &lp->reg); 297 lp = LASIPS2_PORT(&s->mouse_port); 298 sysbus_init_mmio(SYS_BUS_DEVICE(obj), &lp->reg); 299 300 sysbus_init_irq(SYS_BUS_DEVICE(obj), &s->irq); 301 302 qdev_init_gpio_in_named(DEVICE(obj), lasips2_set_kbd_irq, 303 "ps2-kbd-input-irq", 1); 304 qdev_init_gpio_in_named(DEVICE(obj), lasips2_set_mouse_irq, 305 "ps2-mouse-input-irq", 1); 306 } 307 308 static void lasips2_class_init(ObjectClass *klass, void *data) 309 { 310 DeviceClass *dc = DEVICE_CLASS(klass); 311 312 dc->realize = lasips2_realize; 313 dc->vmsd = &vmstate_lasips2; 314 set_bit(DEVICE_CATEGORY_INPUT, dc->categories); 315 } 316 317 static const TypeInfo lasips2_info = { 318 .name = TYPE_LASIPS2, 319 .parent = TYPE_SYS_BUS_DEVICE, 320 .instance_init = lasips2_init, 321 .instance_size = sizeof(LASIPS2State), 322 .class_init = lasips2_class_init, 323 }; 324 325 static void lasips2_port_set_irq(void *opaque, int n, int level) 326 { 327 LASIPS2Port *s = LASIPS2_PORT(opaque); 328 329 qemu_set_irq(s->irq, level); 330 } 331 332 static void lasips2_port_realize(DeviceState *dev, Error **errp) 333 { 334 LASIPS2Port *s = LASIPS2_PORT(dev); 335 336 qdev_connect_gpio_out(DEVICE(s->ps2dev), PS2_DEVICE_IRQ, 337 qdev_get_gpio_in_named(dev, "ps2-input-irq", 0)); 338 } 339 340 static void lasips2_port_init(Object *obj) 341 { 342 LASIPS2Port *s = LASIPS2_PORT(obj); 343 344 qdev_init_gpio_out(DEVICE(obj), &s->irq, 1); 345 qdev_init_gpio_in_named(DEVICE(obj), lasips2_port_set_irq, 346 "ps2-input-irq", 1); 347 } 348 349 static void lasips2_port_class_init(ObjectClass *klass, void *data) 350 { 351 DeviceClass *dc = DEVICE_CLASS(klass); 352 353 dc->realize = lasips2_port_realize; 354 } 355 356 static const TypeInfo lasips2_port_info = { 357 .name = TYPE_LASIPS2_PORT, 358 .parent = TYPE_DEVICE, 359 .instance_init = lasips2_port_init, 360 .instance_size = sizeof(LASIPS2Port), 361 .class_init = lasips2_port_class_init, 362 .class_size = sizeof(LASIPS2PortDeviceClass), 363 .abstract = true, 364 }; 365 366 static void lasips2_kbd_port_realize(DeviceState *dev, Error **errp) 367 { 368 LASIPS2Port *lp = LASIPS2_PORT(dev); 369 370 lp->ps2dev = ps2_kbd_init(); 371 } 372 373 static void lasips2_kbd_port_init(Object *obj) 374 { 375 LASIPS2KbdPort *s = LASIPS2_KBD_PORT(obj); 376 LASIPS2Port *lp = LASIPS2_PORT(obj); 377 378 memory_region_init_io(&lp->reg, obj, &lasips2_reg_ops, lp, "lasips2-kbd", 379 0x100); 380 lp->id = 0; 381 lp->parent = container_of(s, LASIPS2State, kbd_port); 382 } 383 384 static void lasips2_kbd_port_class_init(ObjectClass *klass, void *data) 385 { 386 DeviceClass *dc = DEVICE_CLASS(klass); 387 LASIPS2PortDeviceClass *lpdc = LASIPS2_PORT_CLASS(klass); 388 389 device_class_set_parent_realize(dc, lasips2_kbd_port_realize, 390 &lpdc->parent_realize); 391 } 392 393 static const TypeInfo lasips2_kbd_port_info = { 394 .name = TYPE_LASIPS2_KBD_PORT, 395 .parent = TYPE_LASIPS2_PORT, 396 .instance_size = sizeof(LASIPS2KbdPort), 397 .instance_init = lasips2_kbd_port_init, 398 .class_init = lasips2_kbd_port_class_init, 399 }; 400 401 static void lasips2_mouse_port_realize(DeviceState *dev, Error **errp) 402 { 403 LASIPS2Port *lp = LASIPS2_PORT(dev); 404 405 lp->ps2dev = ps2_mouse_init(); 406 } 407 408 static void lasips2_mouse_port_init(Object *obj) 409 { 410 LASIPS2MousePort *s = LASIPS2_MOUSE_PORT(obj); 411 LASIPS2Port *lp = LASIPS2_PORT(obj); 412 413 memory_region_init_io(&lp->reg, obj, &lasips2_reg_ops, lp, "lasips2-mouse", 414 0x100); 415 lp->id = 1; 416 lp->parent = container_of(s, LASIPS2State, mouse_port); 417 } 418 419 static void lasips2_mouse_port_class_init(ObjectClass *klass, void *data) 420 { 421 DeviceClass *dc = DEVICE_CLASS(klass); 422 LASIPS2PortDeviceClass *lpdc = LASIPS2_PORT_CLASS(klass); 423 424 device_class_set_parent_realize(dc, lasips2_mouse_port_realize, 425 &lpdc->parent_realize); 426 } 427 428 static const TypeInfo lasips2_mouse_port_info = { 429 .name = TYPE_LASIPS2_MOUSE_PORT, 430 .parent = TYPE_LASIPS2_PORT, 431 .instance_size = sizeof(LASIPS2MousePort), 432 .instance_init = lasips2_mouse_port_init, 433 .class_init = lasips2_mouse_port_class_init, 434 }; 435 436 static void lasips2_register_types(void) 437 { 438 type_register_static(&lasips2_info); 439 type_register_static(&lasips2_port_info); 440 type_register_static(&lasips2_kbd_port_info); 441 type_register_static(&lasips2_mouse_port_info); 442 } 443 444 type_init(lasips2_register_types) 445