1 /* 2 * QEMU IDE Emulation: PCI PIIX3/4 support. 3 * 4 * Copyright (c) 2003 Fabrice Bellard 5 * Copyright (c) 2006 Openedhand Ltd. 6 * 7 * Permission is hereby granted, free of charge, to any person obtaining a copy 8 * of this software and associated documentation files (the "Software"), to deal 9 * in the Software without restriction, including without limitation the rights 10 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 11 * copies of the Software, and to permit persons to whom the Software is 12 * furnished to do so, subject to the following conditions: 13 * 14 * The above copyright notice and this permission notice shall be included in 15 * all copies or substantial portions of the Software. 16 * 17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 19 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 20 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 21 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 22 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN 23 * THE SOFTWARE. 24 */ 25 26 #include "qemu/osdep.h" 27 #include "hw/hw.h" 28 #include "hw/pci/pci.h" 29 #include "migration/vmstate.h" 30 #include "qemu/module.h" 31 #include "sysemu/block-backend.h" 32 #include "sysemu/sysemu.h" 33 #include "sysemu/blockdev.h" 34 #include "sysemu/dma.h" 35 #include "sysemu/reset.h" 36 37 #include "hw/ide/pci.h" 38 #include "trace.h" 39 40 static uint64_t bmdma_read(void *opaque, hwaddr addr, unsigned size) 41 { 42 BMDMAState *bm = opaque; 43 uint32_t val; 44 45 if (size != 1) { 46 return ((uint64_t)1 << (size * 8)) - 1; 47 } 48 49 switch(addr & 3) { 50 case 0: 51 val = bm->cmd; 52 break; 53 case 2: 54 val = bm->status; 55 break; 56 default: 57 val = 0xff; 58 break; 59 } 60 61 trace_bmdma_read(addr, val); 62 return val; 63 } 64 65 static void bmdma_write(void *opaque, hwaddr addr, 66 uint64_t val, unsigned size) 67 { 68 BMDMAState *bm = opaque; 69 70 if (size != 1) { 71 return; 72 } 73 74 trace_bmdma_write(addr, val); 75 76 switch(addr & 3) { 77 case 0: 78 bmdma_cmd_writeb(bm, val); 79 break; 80 case 2: 81 bm->status = (val & 0x60) | (bm->status & 1) | (bm->status & ~val & 0x06); 82 break; 83 } 84 } 85 86 static const MemoryRegionOps piix_bmdma_ops = { 87 .read = bmdma_read, 88 .write = bmdma_write, 89 }; 90 91 static void bmdma_setup_bar(PCIIDEState *d) 92 { 93 int i; 94 95 memory_region_init(&d->bmdma_bar, OBJECT(d), "piix-bmdma-container", 16); 96 for(i = 0;i < 2; i++) { 97 BMDMAState *bm = &d->bmdma[i]; 98 99 memory_region_init_io(&bm->extra_io, OBJECT(d), &piix_bmdma_ops, bm, 100 "piix-bmdma", 4); 101 memory_region_add_subregion(&d->bmdma_bar, i * 8, &bm->extra_io); 102 memory_region_init_io(&bm->addr_ioport, OBJECT(d), 103 &bmdma_addr_ioport_ops, bm, "bmdma", 4); 104 memory_region_add_subregion(&d->bmdma_bar, i * 8 + 4, &bm->addr_ioport); 105 } 106 } 107 108 static void piix3_reset(void *opaque) 109 { 110 PCIIDEState *d = opaque; 111 PCIDevice *pd = PCI_DEVICE(d); 112 uint8_t *pci_conf = pd->config; 113 int i; 114 115 for (i = 0; i < 2; i++) { 116 ide_bus_reset(&d->bus[i]); 117 } 118 119 /* TODO: this is the default. do not override. */ 120 pci_conf[PCI_COMMAND] = 0x00; 121 /* TODO: this is the default. do not override. */ 122 pci_conf[PCI_COMMAND + 1] = 0x00; 123 /* TODO: use pci_set_word */ 124 pci_conf[PCI_STATUS] = PCI_STATUS_FAST_BACK; 125 pci_conf[PCI_STATUS + 1] = PCI_STATUS_DEVSEL_MEDIUM >> 8; 126 pci_conf[0x20] = 0x01; /* BMIBA: 20-23h */ 127 } 128 129 static void pci_piix_init_ports(PCIIDEState *d) { 130 static const struct { 131 int iobase; 132 int iobase2; 133 int isairq; 134 } port_info[] = { 135 {0x1f0, 0x3f6, 14}, 136 {0x170, 0x376, 15}, 137 }; 138 int i; 139 140 for (i = 0; i < 2; i++) { 141 ide_bus_new(&d->bus[i], sizeof(d->bus[i]), DEVICE(d), i, 2); 142 ide_init_ioport(&d->bus[i], NULL, port_info[i].iobase, 143 port_info[i].iobase2); 144 ide_init2(&d->bus[i], isa_get_irq(NULL, port_info[i].isairq)); 145 146 bmdma_init(&d->bus[i], &d->bmdma[i], d); 147 d->bmdma[i].bus = &d->bus[i]; 148 ide_register_restart_cb(&d->bus[i]); 149 } 150 } 151 152 static void pci_piix_ide_realize(PCIDevice *dev, Error **errp) 153 { 154 PCIIDEState *d = PCI_IDE(dev); 155 uint8_t *pci_conf = dev->config; 156 157 pci_conf[PCI_CLASS_PROG] = 0x80; // legacy ATA mode 158 159 qemu_register_reset(piix3_reset, d); 160 161 bmdma_setup_bar(d); 162 pci_register_bar(dev, 4, PCI_BASE_ADDRESS_SPACE_IO, &d->bmdma_bar); 163 164 vmstate_register(DEVICE(dev), 0, &vmstate_ide_pci, d); 165 166 pci_piix_init_ports(d); 167 } 168 169 int pci_piix3_xen_ide_unplug(DeviceState *dev, bool aux) 170 { 171 PCIIDEState *pci_ide; 172 DriveInfo *di; 173 int i; 174 IDEDevice *idedev; 175 176 pci_ide = PCI_IDE(dev); 177 178 for (i = aux ? 1 : 0; i < 4; i++) { 179 di = drive_get_by_index(IF_IDE, i); 180 if (di != NULL && !di->media_cd) { 181 BlockBackend *blk = blk_by_legacy_dinfo(di); 182 DeviceState *ds = blk_get_attached_dev(blk); 183 184 blk_drain(blk); 185 blk_flush(blk); 186 187 if (ds) { 188 blk_detach_dev(blk, ds); 189 } 190 pci_ide->bus[di->bus].ifs[di->unit].blk = NULL; 191 if (!(i % 2)) { 192 idedev = pci_ide->bus[di->bus].master; 193 } else { 194 idedev = pci_ide->bus[di->bus].slave; 195 } 196 idedev->conf.blk = NULL; 197 monitor_remove_blk(blk); 198 blk_unref(blk); 199 } 200 } 201 qdev_reset_all(DEVICE(dev)); 202 return 0; 203 } 204 205 PCIDevice *pci_piix3_xen_ide_init(PCIBus *bus, DriveInfo **hd_table, int devfn) 206 { 207 PCIDevice *dev; 208 209 dev = pci_create_simple(bus, devfn, "piix3-ide-xen"); 210 pci_ide_create_devs(dev, hd_table); 211 return dev; 212 } 213 214 static void pci_piix_ide_exitfn(PCIDevice *dev) 215 { 216 PCIIDEState *d = PCI_IDE(dev); 217 unsigned i; 218 219 for (i = 0; i < 2; ++i) { 220 memory_region_del_subregion(&d->bmdma_bar, &d->bmdma[i].extra_io); 221 memory_region_del_subregion(&d->bmdma_bar, &d->bmdma[i].addr_ioport); 222 } 223 } 224 225 /* hd_table must contain 4 block drivers */ 226 /* NOTE: for the PIIX3, the IRQs and IOports are hardcoded */ 227 PCIDevice *pci_piix3_ide_init(PCIBus *bus, DriveInfo **hd_table, int devfn) 228 { 229 PCIDevice *dev; 230 231 dev = pci_create_simple(bus, devfn, "piix3-ide"); 232 pci_ide_create_devs(dev, hd_table); 233 return dev; 234 } 235 236 /* hd_table must contain 4 block drivers */ 237 /* NOTE: for the PIIX4, the IRQs and IOports are hardcoded */ 238 PCIDevice *pci_piix4_ide_init(PCIBus *bus, DriveInfo **hd_table, int devfn) 239 { 240 PCIDevice *dev; 241 242 dev = pci_create_simple(bus, devfn, "piix4-ide"); 243 pci_ide_create_devs(dev, hd_table); 244 return dev; 245 } 246 247 static void piix3_ide_class_init(ObjectClass *klass, void *data) 248 { 249 DeviceClass *dc = DEVICE_CLASS(klass); 250 PCIDeviceClass *k = PCI_DEVICE_CLASS(klass); 251 252 k->realize = pci_piix_ide_realize; 253 k->exit = pci_piix_ide_exitfn; 254 k->vendor_id = PCI_VENDOR_ID_INTEL; 255 k->device_id = PCI_DEVICE_ID_INTEL_82371SB_1; 256 k->class_id = PCI_CLASS_STORAGE_IDE; 257 set_bit(DEVICE_CATEGORY_STORAGE, dc->categories); 258 dc->hotpluggable = false; 259 } 260 261 static const TypeInfo piix3_ide_info = { 262 .name = "piix3-ide", 263 .parent = TYPE_PCI_IDE, 264 .class_init = piix3_ide_class_init, 265 }; 266 267 static const TypeInfo piix3_ide_xen_info = { 268 .name = "piix3-ide-xen", 269 .parent = TYPE_PCI_IDE, 270 .class_init = piix3_ide_class_init, 271 }; 272 273 static void piix4_ide_class_init(ObjectClass *klass, void *data) 274 { 275 DeviceClass *dc = DEVICE_CLASS(klass); 276 PCIDeviceClass *k = PCI_DEVICE_CLASS(klass); 277 278 k->realize = pci_piix_ide_realize; 279 k->exit = pci_piix_ide_exitfn; 280 k->vendor_id = PCI_VENDOR_ID_INTEL; 281 k->device_id = PCI_DEVICE_ID_INTEL_82371AB; 282 k->class_id = PCI_CLASS_STORAGE_IDE; 283 set_bit(DEVICE_CATEGORY_STORAGE, dc->categories); 284 dc->hotpluggable = false; 285 } 286 287 static const TypeInfo piix4_ide_info = { 288 .name = "piix4-ide", 289 .parent = TYPE_PCI_IDE, 290 .class_init = piix4_ide_class_init, 291 }; 292 293 static void piix_ide_register_types(void) 294 { 295 type_register_static(&piix3_ide_info); 296 type_register_static(&piix3_ide_xen_info); 297 type_register_static(&piix4_ide_info); 298 } 299 300 type_init(piix_ide_register_types) 301