1 /* 2 * QEMU IDE Emulation: PCI PIIX3/4 support. 3 * 4 * Copyright (c) 2003 Fabrice Bellard 5 * Copyright (c) 2006 Openedhand Ltd. 6 * 7 * Permission is hereby granted, free of charge, to any person obtaining a copy 8 * of this software and associated documentation files (the "Software"), to deal 9 * in the Software without restriction, including without limitation the rights 10 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 11 * copies of the Software, and to permit persons to whom the Software is 12 * furnished to do so, subject to the following conditions: 13 * 14 * The above copyright notice and this permission notice shall be included in 15 * all copies or substantial portions of the Software. 16 * 17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 19 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 20 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 21 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 22 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN 23 * THE SOFTWARE. 24 * 25 * References: 26 * [1] 82371FB (PIIX) AND 82371SB (PIIX3) PCI ISA IDE XCELERATOR, 27 * 290550-002, Intel Corporation, April 1997. 28 */ 29 30 #include "qemu/osdep.h" 31 #include "hw/pci/pci.h" 32 #include "migration/vmstate.h" 33 #include "qapi/error.h" 34 #include "qemu/module.h" 35 #include "sysemu/block-backend.h" 36 #include "sysemu/blockdev.h" 37 #include "sysemu/dma.h" 38 39 #include "hw/ide/piix.h" 40 #include "hw/ide/pci.h" 41 #include "trace.h" 42 43 static uint64_t bmdma_read(void *opaque, hwaddr addr, unsigned size) 44 { 45 BMDMAState *bm = opaque; 46 uint32_t val; 47 48 if (size != 1) { 49 return ((uint64_t)1 << (size * 8)) - 1; 50 } 51 52 switch(addr & 3) { 53 case 0: 54 val = bm->cmd; 55 break; 56 case 2: 57 val = bm->status; 58 break; 59 default: 60 val = 0xff; 61 break; 62 } 63 64 trace_bmdma_read(addr, val); 65 return val; 66 } 67 68 static void bmdma_write(void *opaque, hwaddr addr, 69 uint64_t val, unsigned size) 70 { 71 BMDMAState *bm = opaque; 72 73 if (size != 1) { 74 return; 75 } 76 77 trace_bmdma_write(addr, val); 78 79 switch(addr & 3) { 80 case 0: 81 bmdma_cmd_writeb(bm, val); 82 break; 83 case 2: 84 bm->status = (val & 0x60) | (bm->status & 1) | (bm->status & ~val & 0x06); 85 break; 86 } 87 } 88 89 static const MemoryRegionOps piix_bmdma_ops = { 90 .read = bmdma_read, 91 .write = bmdma_write, 92 }; 93 94 static void bmdma_setup_bar(PCIIDEState *d) 95 { 96 int i; 97 98 memory_region_init(&d->bmdma_bar, OBJECT(d), "piix-bmdma-container", 16); 99 for(i = 0;i < 2; i++) { 100 BMDMAState *bm = &d->bmdma[i]; 101 102 memory_region_init_io(&bm->extra_io, OBJECT(d), &piix_bmdma_ops, bm, 103 "piix-bmdma", 4); 104 memory_region_add_subregion(&d->bmdma_bar, i * 8, &bm->extra_io); 105 memory_region_init_io(&bm->addr_ioport, OBJECT(d), 106 &bmdma_addr_ioport_ops, bm, "bmdma", 4); 107 memory_region_add_subregion(&d->bmdma_bar, i * 8 + 4, &bm->addr_ioport); 108 } 109 } 110 111 static void piix_ide_reset(DeviceState *dev) 112 { 113 PCIIDEState *d = PCI_IDE(dev); 114 PCIDevice *pd = PCI_DEVICE(d); 115 uint8_t *pci_conf = pd->config; 116 int i; 117 118 for (i = 0; i < 2; i++) { 119 ide_bus_reset(&d->bus[i]); 120 } 121 122 /* PCI command register default value (0000h) per [1, p.48]. */ 123 pci_set_word(pci_conf + PCI_COMMAND, 0x0000); 124 pci_set_word(pci_conf + PCI_STATUS, 125 PCI_STATUS_DEVSEL_MEDIUM | PCI_STATUS_FAST_BACK); 126 pci_set_byte(pci_conf + 0x20, 0x01); /* BMIBA: 20-23h */ 127 } 128 129 static int pci_piix_init_ports(PCIIDEState *d) 130 { 131 static const struct { 132 int iobase; 133 int iobase2; 134 int isairq; 135 } port_info[] = { 136 {0x1f0, 0x3f6, 14}, 137 {0x170, 0x376, 15}, 138 }; 139 int i, ret; 140 141 for (i = 0; i < 2; i++) { 142 ide_bus_init(&d->bus[i], sizeof(d->bus[i]), DEVICE(d), i, 2); 143 ret = ide_init_ioport(&d->bus[i], NULL, port_info[i].iobase, 144 port_info[i].iobase2); 145 if (ret) { 146 return ret; 147 } 148 ide_bus_init_output_irq(&d->bus[i], 149 isa_get_irq(NULL, port_info[i].isairq)); 150 151 bmdma_init(&d->bus[i], &d->bmdma[i], d); 152 d->bmdma[i].bus = &d->bus[i]; 153 ide_bus_register_restart_cb(&d->bus[i]); 154 } 155 156 return 0; 157 } 158 159 static void pci_piix_ide_realize(PCIDevice *dev, Error **errp) 160 { 161 PCIIDEState *d = PCI_IDE(dev); 162 uint8_t *pci_conf = dev->config; 163 int rc; 164 165 pci_conf[PCI_CLASS_PROG] = 0x80; // legacy ATA mode 166 167 bmdma_setup_bar(d); 168 pci_register_bar(dev, 4, PCI_BASE_ADDRESS_SPACE_IO, &d->bmdma_bar); 169 170 vmstate_register(VMSTATE_IF(dev), 0, &vmstate_ide_pci, d); 171 172 rc = pci_piix_init_ports(d); 173 if (rc) { 174 error_setg_errno(errp, -rc, "Failed to realize %s", 175 object_get_typename(OBJECT(dev))); 176 } 177 } 178 179 static void pci_piix_ide_exitfn(PCIDevice *dev) 180 { 181 PCIIDEState *d = PCI_IDE(dev); 182 unsigned i; 183 184 for (i = 0; i < 2; ++i) { 185 memory_region_del_subregion(&d->bmdma_bar, &d->bmdma[i].extra_io); 186 memory_region_del_subregion(&d->bmdma_bar, &d->bmdma[i].addr_ioport); 187 } 188 } 189 190 /* NOTE: for the PIIX3, the IRQs and IOports are hardcoded */ 191 static void piix3_ide_class_init(ObjectClass *klass, void *data) 192 { 193 DeviceClass *dc = DEVICE_CLASS(klass); 194 PCIDeviceClass *k = PCI_DEVICE_CLASS(klass); 195 196 dc->reset = piix_ide_reset; 197 k->realize = pci_piix_ide_realize; 198 k->exit = pci_piix_ide_exitfn; 199 k->vendor_id = PCI_VENDOR_ID_INTEL; 200 k->device_id = PCI_DEVICE_ID_INTEL_82371SB_1; 201 k->class_id = PCI_CLASS_STORAGE_IDE; 202 set_bit(DEVICE_CATEGORY_STORAGE, dc->categories); 203 dc->hotpluggable = false; 204 } 205 206 static const TypeInfo piix3_ide_info = { 207 .name = TYPE_PIIX3_IDE, 208 .parent = TYPE_PCI_IDE, 209 .class_init = piix3_ide_class_init, 210 }; 211 212 /* NOTE: for the PIIX4, the IRQs and IOports are hardcoded */ 213 static void piix4_ide_class_init(ObjectClass *klass, void *data) 214 { 215 DeviceClass *dc = DEVICE_CLASS(klass); 216 PCIDeviceClass *k = PCI_DEVICE_CLASS(klass); 217 218 dc->reset = piix_ide_reset; 219 k->realize = pci_piix_ide_realize; 220 k->exit = pci_piix_ide_exitfn; 221 k->vendor_id = PCI_VENDOR_ID_INTEL; 222 k->device_id = PCI_DEVICE_ID_INTEL_82371AB; 223 k->class_id = PCI_CLASS_STORAGE_IDE; 224 set_bit(DEVICE_CATEGORY_STORAGE, dc->categories); 225 dc->hotpluggable = false; 226 } 227 228 static const TypeInfo piix4_ide_info = { 229 .name = TYPE_PIIX4_IDE, 230 .parent = TYPE_PCI_IDE, 231 .class_init = piix4_ide_class_init, 232 }; 233 234 static void piix_ide_register_types(void) 235 { 236 type_register_static(&piix3_ide_info); 237 type_register_static(&piix4_ide_info); 238 } 239 240 type_init(piix_ide_register_types) 241