1 /* 2 * QEMU IDE Emulation: PCI PIIX3/4 support. 3 * 4 * Copyright (c) 2003 Fabrice Bellard 5 * Copyright (c) 2006 Openedhand Ltd. 6 * 7 * Permission is hereby granted, free of charge, to any person obtaining a copy 8 * of this software and associated documentation files (the "Software"), to deal 9 * in the Software without restriction, including without limitation the rights 10 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 11 * copies of the Software, and to permit persons to whom the Software is 12 * furnished to do so, subject to the following conditions: 13 * 14 * The above copyright notice and this permission notice shall be included in 15 * all copies or substantial portions of the Software. 16 * 17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 19 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 20 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 21 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 22 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN 23 * THE SOFTWARE. 24 */ 25 #include <hw/hw.h> 26 #include <hw/pc.h> 27 #include <hw/pci.h> 28 #include <hw/isa.h> 29 #include "block.h" 30 #include "block_int.h" 31 #include "sysemu.h" 32 #include "dma.h" 33 34 #include <hw/ide/pci.h> 35 36 static uint32_t bmdma_readb(void *opaque, uint32_t addr) 37 { 38 BMDMAState *bm = opaque; 39 uint32_t val; 40 41 switch(addr & 3) { 42 case 0: 43 val = bm->cmd; 44 break; 45 case 2: 46 val = bm->status; 47 break; 48 default: 49 val = 0xff; 50 break; 51 } 52 #ifdef DEBUG_IDE 53 printf("bmdma: readb 0x%02x : 0x%02x\n", addr, val); 54 #endif 55 return val; 56 } 57 58 static void bmdma_writeb(void *opaque, uint32_t addr, uint32_t val) 59 { 60 BMDMAState *bm = opaque; 61 #ifdef DEBUG_IDE 62 printf("bmdma: writeb 0x%02x : 0x%02x\n", addr, val); 63 #endif 64 switch(addr & 3) { 65 case 2: 66 bm->status = (val & 0x60) | (bm->status & 1) | (bm->status & ~val & 0x06); 67 break; 68 } 69 } 70 71 static void bmdma_map(PCIDevice *pci_dev, int region_num, 72 uint32_t addr, uint32_t size, int type) 73 { 74 PCIIDEState *d = DO_UPCAST(PCIIDEState, dev, pci_dev); 75 int i; 76 77 for(i = 0;i < 2; i++) { 78 BMDMAState *bm = &d->bmdma[i]; 79 d->bus[i].bmdma = bm; 80 bm->pci_dev = DO_UPCAST(PCIIDEState, dev, pci_dev); 81 bm->bus = d->bus+i; 82 qemu_add_vm_change_state_handler(ide_dma_restart_cb, bm); 83 84 register_ioport_write(addr, 1, 1, bmdma_cmd_writeb, bm); 85 86 register_ioport_write(addr + 1, 3, 1, bmdma_writeb, bm); 87 register_ioport_read(addr, 4, 1, bmdma_readb, bm); 88 89 register_ioport_write(addr + 4, 4, 1, bmdma_addr_writeb, bm); 90 register_ioport_read(addr + 4, 4, 1, bmdma_addr_readb, bm); 91 register_ioport_write(addr + 4, 4, 2, bmdma_addr_writew, bm); 92 register_ioport_read(addr + 4, 4, 2, bmdma_addr_readw, bm); 93 register_ioport_write(addr + 4, 4, 4, bmdma_addr_writel, bm); 94 register_ioport_read(addr + 4, 4, 4, bmdma_addr_readl, bm); 95 addr += 8; 96 } 97 } 98 99 static void piix3_reset(void *opaque) 100 { 101 PCIIDEState *d = opaque; 102 uint8_t *pci_conf = d->dev.config; 103 int i; 104 105 for (i = 0; i < 2; i++) 106 ide_dma_cancel(&d->bmdma[i]); 107 108 pci_conf[0x04] = 0x00; 109 pci_conf[0x05] = 0x00; 110 pci_conf[0x06] = 0x80; /* FBC */ 111 pci_conf[0x07] = 0x02; // PCI_status_devsel_medium 112 pci_conf[0x20] = 0x01; /* BMIBA: 20-23h */ 113 } 114 115 static int pci_piix_ide_initfn(PCIIDEState *d) 116 { 117 uint8_t *pci_conf = d->dev.config; 118 119 pci_conf[0x09] = 0x80; // legacy ATA mode 120 pci_config_set_class(pci_conf, PCI_CLASS_STORAGE_IDE); 121 pci_conf[PCI_HEADER_TYPE] = PCI_HEADER_TYPE_NORMAL; // header_type 122 123 qemu_register_reset(piix3_reset, d); 124 piix3_reset(d); 125 126 pci_register_bar(&d->dev, 4, 0x10, PCI_ADDRESS_SPACE_IO, bmdma_map); 127 128 register_savevm("ide", 0, 3, pci_ide_save, pci_ide_load, d); 129 130 ide_bus_new(&d->bus[0], &d->dev.qdev); 131 ide_bus_new(&d->bus[1], &d->dev.qdev); 132 ide_init_ioport(&d->bus[0], 0x1f0, 0x3f6); 133 ide_init_ioport(&d->bus[1], 0x170, 0x376); 134 135 ide_init2(&d->bus[0], NULL, NULL, isa_reserve_irq(14)); 136 ide_init2(&d->bus[1], NULL, NULL, isa_reserve_irq(15)); 137 return 0; 138 } 139 140 static int pci_piix3_ide_initfn(PCIDevice *dev) 141 { 142 PCIIDEState *d = DO_UPCAST(PCIIDEState, dev, dev); 143 144 d->type = IDE_TYPE_PIIX3; 145 pci_config_set_vendor_id(d->dev.config, PCI_VENDOR_ID_INTEL); 146 pci_config_set_device_id(d->dev.config, PCI_DEVICE_ID_INTEL_82371SB_1); 147 return pci_piix_ide_initfn(d); 148 } 149 150 static int pci_piix4_ide_initfn(PCIDevice *dev) 151 { 152 PCIIDEState *d = DO_UPCAST(PCIIDEState, dev, dev); 153 154 d->type = IDE_TYPE_PIIX4; 155 pci_config_set_vendor_id(d->dev.config, PCI_VENDOR_ID_INTEL); 156 pci_config_set_device_id(d->dev.config, PCI_DEVICE_ID_INTEL_82371AB); 157 return pci_piix_ide_initfn(d); 158 } 159 160 /* hd_table must contain 4 block drivers */ 161 /* NOTE: for the PIIX3, the IRQs and IOports are hardcoded */ 162 void pci_piix3_ide_init(PCIBus *bus, DriveInfo **hd_table, int devfn) 163 { 164 PCIDevice *dev; 165 166 dev = pci_create_simple(bus, devfn, "PIIX3 IDE"); 167 pci_ide_create_devs(dev, hd_table); 168 } 169 170 /* hd_table must contain 4 block drivers */ 171 /* NOTE: for the PIIX4, the IRQs and IOports are hardcoded */ 172 void pci_piix4_ide_init(PCIBus *bus, DriveInfo **hd_table, int devfn) 173 { 174 PCIDevice *dev; 175 176 dev = pci_create_simple(bus, devfn, "PIIX4 IDE"); 177 pci_ide_create_devs(dev, hd_table); 178 } 179 180 static PCIDeviceInfo piix_ide_info[] = { 181 { 182 .qdev.name = "PIIX3 IDE", 183 .qdev.size = sizeof(PCIIDEState), 184 .init = pci_piix3_ide_initfn, 185 },{ 186 .qdev.name = "PIIX4 IDE", 187 .qdev.size = sizeof(PCIIDEState), 188 .init = pci_piix4_ide_initfn, 189 },{ 190 /* end of list */ 191 } 192 }; 193 194 static void piix_ide_register(void) 195 { 196 pci_qdev_register_many(piix_ide_info); 197 } 198 device_init(piix_ide_register); 199