1 /* 2 * QEMU IDE Emulation: PCI cmd646 support. 3 * 4 * Copyright (c) 2003 Fabrice Bellard 5 * Copyright (c) 2006 Openedhand Ltd. 6 * 7 * Permission is hereby granted, free of charge, to any person obtaining a copy 8 * of this software and associated documentation files (the "Software"), to deal 9 * in the Software without restriction, including without limitation the rights 10 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 11 * copies of the Software, and to permit persons to whom the Software is 12 * furnished to do so, subject to the following conditions: 13 * 14 * The above copyright notice and this permission notice shall be included in 15 * all copies or substantial portions of the Software. 16 * 17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 19 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 20 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 21 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 22 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN 23 * THE SOFTWARE. 24 */ 25 #include "qemu/osdep.h" 26 #include "hw/hw.h" 27 #include "hw/pci/pci.h" 28 #include "hw/isa/isa.h" 29 #include "sysemu/sysemu.h" 30 #include "sysemu/dma.h" 31 32 #include "hw/ide/pci.h" 33 #include "trace.h" 34 35 /* CMD646 specific */ 36 #define CFR 0x50 37 #define CFR_INTR_CH0 0x04 38 #define CNTRL 0x51 39 #define CNTRL_EN_CH0 0x04 40 #define CNTRL_EN_CH1 0x08 41 #define ARTTIM23 0x57 42 #define ARTTIM23_INTR_CH1 0x10 43 #define MRDMODE 0x71 44 #define MRDMODE_INTR_CH0 0x04 45 #define MRDMODE_INTR_CH1 0x08 46 #define MRDMODE_BLK_CH0 0x10 47 #define MRDMODE_BLK_CH1 0x20 48 #define UDIDETCR0 0x73 49 #define UDIDETCR1 0x7B 50 51 static void cmd646_update_irq(PCIDevice *pd); 52 53 static uint64_t cmd646_cmd_read(void *opaque, hwaddr addr, 54 unsigned size) 55 { 56 IDEBus *bus = opaque; 57 58 if (addr != 2 || size != 1) { 59 return ((uint64_t)1 << (size * 8)) - 1; 60 } 61 return ide_status_read(bus, addr + 2); 62 } 63 64 static void cmd646_cmd_write(void *opaque, hwaddr addr, 65 uint64_t data, unsigned size) 66 { 67 IDEBus *bus = opaque; 68 69 if (addr != 2 || size != 1) { 70 return; 71 } 72 ide_cmd_write(bus, addr + 2, data); 73 } 74 75 static const MemoryRegionOps cmd646_cmd_ops = { 76 .read = cmd646_cmd_read, 77 .write = cmd646_cmd_write, 78 .endianness = DEVICE_LITTLE_ENDIAN, 79 }; 80 81 static uint64_t cmd646_data_read(void *opaque, hwaddr addr, 82 unsigned size) 83 { 84 IDEBus *bus = opaque; 85 86 if (size == 1) { 87 return ide_ioport_read(bus, addr); 88 } else if (addr == 0) { 89 if (size == 2) { 90 return ide_data_readw(bus, addr); 91 } else { 92 return ide_data_readl(bus, addr); 93 } 94 } 95 return ((uint64_t)1 << (size * 8)) - 1; 96 } 97 98 static void cmd646_data_write(void *opaque, hwaddr addr, 99 uint64_t data, unsigned size) 100 { 101 IDEBus *bus = opaque; 102 103 if (size == 1) { 104 ide_ioport_write(bus, addr, data); 105 } else if (addr == 0) { 106 if (size == 2) { 107 ide_data_writew(bus, addr, data); 108 } else { 109 ide_data_writel(bus, addr, data); 110 } 111 } 112 } 113 114 static const MemoryRegionOps cmd646_data_ops = { 115 .read = cmd646_data_read, 116 .write = cmd646_data_write, 117 .endianness = DEVICE_LITTLE_ENDIAN, 118 }; 119 120 static void setup_cmd646_bar(PCIIDEState *d, int bus_num) 121 { 122 IDEBus *bus = &d->bus[bus_num]; 123 CMD646BAR *bar = &d->cmd646_bar[bus_num]; 124 125 memory_region_init_io(&bar->cmd, OBJECT(d), &cmd646_cmd_ops, bus, 126 "cmd646-cmd", 4); 127 memory_region_init_io(&bar->data, OBJECT(d), &cmd646_data_ops, bus, 128 "cmd646-data", 8); 129 } 130 131 static void cmd646_update_dma_interrupts(PCIDevice *pd) 132 { 133 /* Sync DMA interrupt status from UDMA interrupt status */ 134 if (pd->config[MRDMODE] & MRDMODE_INTR_CH0) { 135 pd->config[CFR] |= CFR_INTR_CH0; 136 } else { 137 pd->config[CFR] &= ~CFR_INTR_CH0; 138 } 139 140 if (pd->config[MRDMODE] & MRDMODE_INTR_CH1) { 141 pd->config[ARTTIM23] |= ARTTIM23_INTR_CH1; 142 } else { 143 pd->config[ARTTIM23] &= ~ARTTIM23_INTR_CH1; 144 } 145 } 146 147 static void cmd646_update_udma_interrupts(PCIDevice *pd) 148 { 149 /* Sync UDMA interrupt status from DMA interrupt status */ 150 if (pd->config[CFR] & CFR_INTR_CH0) { 151 pd->config[MRDMODE] |= MRDMODE_INTR_CH0; 152 } else { 153 pd->config[MRDMODE] &= ~MRDMODE_INTR_CH0; 154 } 155 156 if (pd->config[ARTTIM23] & ARTTIM23_INTR_CH1) { 157 pd->config[MRDMODE] |= MRDMODE_INTR_CH1; 158 } else { 159 pd->config[MRDMODE] &= ~MRDMODE_INTR_CH1; 160 } 161 } 162 163 static uint64_t bmdma_read(void *opaque, hwaddr addr, 164 unsigned size) 165 { 166 BMDMAState *bm = opaque; 167 PCIDevice *pci_dev = PCI_DEVICE(bm->pci_dev); 168 uint32_t val; 169 170 if (size != 1) { 171 return ((uint64_t)1 << (size * 8)) - 1; 172 } 173 174 switch(addr & 3) { 175 case 0: 176 val = bm->cmd; 177 break; 178 case 1: 179 val = pci_dev->config[MRDMODE]; 180 break; 181 case 2: 182 val = bm->status; 183 break; 184 case 3: 185 if (bm == &bm->pci_dev->bmdma[0]) { 186 val = pci_dev->config[UDIDETCR0]; 187 } else { 188 val = pci_dev->config[UDIDETCR1]; 189 } 190 break; 191 default: 192 val = 0xff; 193 break; 194 } 195 196 trace_bmdma_read_cmd646(addr, val); 197 return val; 198 } 199 200 static void bmdma_write(void *opaque, hwaddr addr, 201 uint64_t val, unsigned size) 202 { 203 BMDMAState *bm = opaque; 204 PCIDevice *pci_dev = PCI_DEVICE(bm->pci_dev); 205 206 if (size != 1) { 207 return; 208 } 209 210 trace_bmdma_write_cmd646(addr, val); 211 switch(addr & 3) { 212 case 0: 213 bmdma_cmd_writeb(bm, val); 214 break; 215 case 1: 216 pci_dev->config[MRDMODE] = 217 (pci_dev->config[MRDMODE] & ~0x30) | (val & 0x30); 218 cmd646_update_dma_interrupts(pci_dev); 219 cmd646_update_irq(pci_dev); 220 break; 221 case 2: 222 bm->status = (val & 0x60) | (bm->status & 1) | (bm->status & ~val & 0x06); 223 break; 224 case 3: 225 if (bm == &bm->pci_dev->bmdma[0]) { 226 pci_dev->config[UDIDETCR0] = val; 227 } else { 228 pci_dev->config[UDIDETCR1] = val; 229 } 230 break; 231 } 232 } 233 234 static const MemoryRegionOps cmd646_bmdma_ops = { 235 .read = bmdma_read, 236 .write = bmdma_write, 237 }; 238 239 static void bmdma_setup_bar(PCIIDEState *d) 240 { 241 BMDMAState *bm; 242 int i; 243 244 memory_region_init(&d->bmdma_bar, OBJECT(d), "cmd646-bmdma", 16); 245 for(i = 0;i < 2; i++) { 246 bm = &d->bmdma[i]; 247 memory_region_init_io(&bm->extra_io, OBJECT(d), &cmd646_bmdma_ops, bm, 248 "cmd646-bmdma-bus", 4); 249 memory_region_add_subregion(&d->bmdma_bar, i * 8, &bm->extra_io); 250 memory_region_init_io(&bm->addr_ioport, OBJECT(d), 251 &bmdma_addr_ioport_ops, bm, 252 "cmd646-bmdma-ioport", 4); 253 memory_region_add_subregion(&d->bmdma_bar, i * 8 + 4, &bm->addr_ioport); 254 } 255 } 256 257 static void cmd646_update_irq(PCIDevice *pd) 258 { 259 int pci_level; 260 261 pci_level = ((pd->config[MRDMODE] & MRDMODE_INTR_CH0) && 262 !(pd->config[MRDMODE] & MRDMODE_BLK_CH0)) || 263 ((pd->config[MRDMODE] & MRDMODE_INTR_CH1) && 264 !(pd->config[MRDMODE] & MRDMODE_BLK_CH1)); 265 pci_set_irq(pd, pci_level); 266 } 267 268 /* the PCI irq level is the logical OR of the two channels */ 269 static void cmd646_set_irq(void *opaque, int channel, int level) 270 { 271 PCIIDEState *d = opaque; 272 PCIDevice *pd = PCI_DEVICE(d); 273 int irq_mask; 274 275 irq_mask = MRDMODE_INTR_CH0 << channel; 276 if (level) { 277 pd->config[MRDMODE] |= irq_mask; 278 } else { 279 pd->config[MRDMODE] &= ~irq_mask; 280 } 281 cmd646_update_dma_interrupts(pd); 282 cmd646_update_irq(pd); 283 } 284 285 static void cmd646_reset(void *opaque) 286 { 287 PCIIDEState *d = opaque; 288 unsigned int i; 289 290 for (i = 0; i < 2; i++) { 291 ide_bus_reset(&d->bus[i]); 292 } 293 } 294 295 static uint32_t cmd646_pci_config_read(PCIDevice *d, 296 uint32_t address, int len) 297 { 298 return pci_default_read_config(d, address, len); 299 } 300 301 static void cmd646_pci_config_write(PCIDevice *d, uint32_t addr, uint32_t val, 302 int l) 303 { 304 uint32_t i; 305 306 pci_default_write_config(d, addr, val, l); 307 308 for (i = addr; i < addr + l; i++) { 309 switch (i) { 310 case CFR: 311 case ARTTIM23: 312 cmd646_update_udma_interrupts(d); 313 break; 314 case MRDMODE: 315 cmd646_update_dma_interrupts(d); 316 break; 317 } 318 } 319 320 cmd646_update_irq(d); 321 } 322 323 /* CMD646 PCI IDE controller */ 324 static void pci_cmd646_ide_realize(PCIDevice *dev, Error **errp) 325 { 326 PCIIDEState *d = PCI_IDE(dev); 327 uint8_t *pci_conf = dev->config; 328 qemu_irq *irq; 329 int i; 330 331 pci_conf[PCI_CLASS_PROG] = 0x8f; 332 333 pci_conf[CNTRL] = CNTRL_EN_CH0; // enable IDE0 334 if (d->secondary) { 335 /* XXX: if not enabled, really disable the seconday IDE controller */ 336 pci_conf[CNTRL] |= CNTRL_EN_CH1; /* enable IDE1 */ 337 } 338 339 /* Set write-to-clear interrupt bits */ 340 dev->wmask[CFR] = 0x0; 341 dev->w1cmask[CFR] = CFR_INTR_CH0; 342 dev->wmask[ARTTIM23] = 0x0; 343 dev->w1cmask[ARTTIM23] = ARTTIM23_INTR_CH1; 344 dev->wmask[MRDMODE] = 0x0; 345 dev->w1cmask[MRDMODE] = MRDMODE_INTR_CH0 | MRDMODE_INTR_CH1; 346 347 setup_cmd646_bar(d, 0); 348 setup_cmd646_bar(d, 1); 349 pci_register_bar(dev, 0, PCI_BASE_ADDRESS_SPACE_IO, &d->cmd646_bar[0].data); 350 pci_register_bar(dev, 1, PCI_BASE_ADDRESS_SPACE_IO, &d->cmd646_bar[0].cmd); 351 pci_register_bar(dev, 2, PCI_BASE_ADDRESS_SPACE_IO, &d->cmd646_bar[1].data); 352 pci_register_bar(dev, 3, PCI_BASE_ADDRESS_SPACE_IO, &d->cmd646_bar[1].cmd); 353 bmdma_setup_bar(d); 354 pci_register_bar(dev, 4, PCI_BASE_ADDRESS_SPACE_IO, &d->bmdma_bar); 355 356 /* TODO: RST# value should be 0 */ 357 pci_conf[PCI_INTERRUPT_PIN] = 0x01; // interrupt on pin 1 358 359 irq = qemu_allocate_irqs(cmd646_set_irq, d, 2); 360 for (i = 0; i < 2; i++) { 361 ide_bus_new(&d->bus[i], sizeof(d->bus[i]), DEVICE(dev), i, 2); 362 ide_init2(&d->bus[i], irq[i]); 363 364 bmdma_init(&d->bus[i], &d->bmdma[i], d); 365 d->bmdma[i].bus = &d->bus[i]; 366 ide_register_restart_cb(&d->bus[i]); 367 } 368 369 vmstate_register(DEVICE(dev), 0, &vmstate_ide_pci, d); 370 qemu_register_reset(cmd646_reset, d); 371 } 372 373 static void pci_cmd646_ide_exitfn(PCIDevice *dev) 374 { 375 PCIIDEState *d = PCI_IDE(dev); 376 unsigned i; 377 378 for (i = 0; i < 2; ++i) { 379 memory_region_del_subregion(&d->bmdma_bar, &d->bmdma[i].extra_io); 380 memory_region_del_subregion(&d->bmdma_bar, &d->bmdma[i].addr_ioport); 381 } 382 } 383 384 void pci_cmd646_ide_init(PCIBus *bus, DriveInfo **hd_table, 385 int secondary_ide_enabled) 386 { 387 PCIDevice *dev; 388 389 dev = pci_create(bus, -1, "cmd646-ide"); 390 qdev_prop_set_uint32(&dev->qdev, "secondary", secondary_ide_enabled); 391 qdev_init_nofail(&dev->qdev); 392 393 pci_ide_create_devs(dev, hd_table); 394 } 395 396 static Property cmd646_ide_properties[] = { 397 DEFINE_PROP_UINT32("secondary", PCIIDEState, secondary, 0), 398 DEFINE_PROP_END_OF_LIST(), 399 }; 400 401 static void cmd646_ide_class_init(ObjectClass *klass, void *data) 402 { 403 DeviceClass *dc = DEVICE_CLASS(klass); 404 PCIDeviceClass *k = PCI_DEVICE_CLASS(klass); 405 406 k->realize = pci_cmd646_ide_realize; 407 k->exit = pci_cmd646_ide_exitfn; 408 k->vendor_id = PCI_VENDOR_ID_CMD; 409 k->device_id = PCI_DEVICE_ID_CMD_646; 410 k->revision = 0x07; 411 k->class_id = PCI_CLASS_STORAGE_IDE; 412 k->config_read = cmd646_pci_config_read; 413 k->config_write = cmd646_pci_config_write; 414 dc->props = cmd646_ide_properties; 415 set_bit(DEVICE_CATEGORY_STORAGE, dc->categories); 416 } 417 418 static const TypeInfo cmd646_ide_info = { 419 .name = "cmd646-ide", 420 .parent = TYPE_PCI_IDE, 421 .class_init = cmd646_ide_class_init, 422 }; 423 424 static void cmd646_ide_register_types(void) 425 { 426 type_register_static(&cmd646_ide_info); 427 } 428 429 type_init(cmd646_ide_register_types) 430