1 /* 2 * QEMU IDE Emulation: PCI cmd646 support. 3 * 4 * Copyright (c) 2003 Fabrice Bellard 5 * Copyright (c) 2006 Openedhand Ltd. 6 * 7 * Permission is hereby granted, free of charge, to any person obtaining a copy 8 * of this software and associated documentation files (the "Software"), to deal 9 * in the Software without restriction, including without limitation the rights 10 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 11 * copies of the Software, and to permit persons to whom the Software is 12 * furnished to do so, subject to the following conditions: 13 * 14 * The above copyright notice and this permission notice shall be included in 15 * all copies or substantial portions of the Software. 16 * 17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 19 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 20 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 21 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 22 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN 23 * THE SOFTWARE. 24 */ 25 #include "qemu/osdep.h" 26 #include "hw/hw.h" 27 #include "hw/pci/pci.h" 28 #include "hw/isa/isa.h" 29 #include "sysemu/sysemu.h" 30 #include "sysemu/dma.h" 31 32 #include "hw/ide/pci.h" 33 #include "trace.h" 34 35 /* CMD646 specific */ 36 #define CFR 0x50 37 #define CFR_INTR_CH0 0x04 38 #define CNTRL 0x51 39 #define CNTRL_EN_CH0 0x04 40 #define CNTRL_EN_CH1 0x08 41 #define ARTTIM23 0x57 42 #define ARTTIM23_INTR_CH1 0x10 43 #define MRDMODE 0x71 44 #define MRDMODE_INTR_CH0 0x04 45 #define MRDMODE_INTR_CH1 0x08 46 #define MRDMODE_BLK_CH0 0x10 47 #define MRDMODE_BLK_CH1 0x20 48 #define UDIDETCR0 0x73 49 #define UDIDETCR1 0x7B 50 51 static void cmd646_update_irq(PCIDevice *pd); 52 53 static void setup_cmd646_bar(PCIIDEState *d, int bus_num) 54 { 55 IDEBus *bus = &d->bus[bus_num]; 56 CMD646BAR *bar = &d->cmd646_bar[bus_num]; 57 58 memory_region_init_io(&bar->cmd, OBJECT(d), &pci_ide_cmd_le_ops, bus, 59 "cmd646-cmd", 4); 60 memory_region_init_io(&bar->data, OBJECT(d), &pci_ide_data_le_ops, bus, 61 "cmd646-data", 8); 62 } 63 64 static void cmd646_update_dma_interrupts(PCIDevice *pd) 65 { 66 /* Sync DMA interrupt status from UDMA interrupt status */ 67 if (pd->config[MRDMODE] & MRDMODE_INTR_CH0) { 68 pd->config[CFR] |= CFR_INTR_CH0; 69 } else { 70 pd->config[CFR] &= ~CFR_INTR_CH0; 71 } 72 73 if (pd->config[MRDMODE] & MRDMODE_INTR_CH1) { 74 pd->config[ARTTIM23] |= ARTTIM23_INTR_CH1; 75 } else { 76 pd->config[ARTTIM23] &= ~ARTTIM23_INTR_CH1; 77 } 78 } 79 80 static void cmd646_update_udma_interrupts(PCIDevice *pd) 81 { 82 /* Sync UDMA interrupt status from DMA interrupt status */ 83 if (pd->config[CFR] & CFR_INTR_CH0) { 84 pd->config[MRDMODE] |= MRDMODE_INTR_CH0; 85 } else { 86 pd->config[MRDMODE] &= ~MRDMODE_INTR_CH0; 87 } 88 89 if (pd->config[ARTTIM23] & ARTTIM23_INTR_CH1) { 90 pd->config[MRDMODE] |= MRDMODE_INTR_CH1; 91 } else { 92 pd->config[MRDMODE] &= ~MRDMODE_INTR_CH1; 93 } 94 } 95 96 static uint64_t bmdma_read(void *opaque, hwaddr addr, 97 unsigned size) 98 { 99 BMDMAState *bm = opaque; 100 PCIDevice *pci_dev = PCI_DEVICE(bm->pci_dev); 101 uint32_t val; 102 103 if (size != 1) { 104 return ((uint64_t)1 << (size * 8)) - 1; 105 } 106 107 switch(addr & 3) { 108 case 0: 109 val = bm->cmd; 110 break; 111 case 1: 112 val = pci_dev->config[MRDMODE]; 113 break; 114 case 2: 115 val = bm->status; 116 break; 117 case 3: 118 if (bm == &bm->pci_dev->bmdma[0]) { 119 val = pci_dev->config[UDIDETCR0]; 120 } else { 121 val = pci_dev->config[UDIDETCR1]; 122 } 123 break; 124 default: 125 val = 0xff; 126 break; 127 } 128 129 trace_bmdma_read_cmd646(addr, val); 130 return val; 131 } 132 133 static void bmdma_write(void *opaque, hwaddr addr, 134 uint64_t val, unsigned size) 135 { 136 BMDMAState *bm = opaque; 137 PCIDevice *pci_dev = PCI_DEVICE(bm->pci_dev); 138 139 if (size != 1) { 140 return; 141 } 142 143 trace_bmdma_write_cmd646(addr, val); 144 switch(addr & 3) { 145 case 0: 146 bmdma_cmd_writeb(bm, val); 147 break; 148 case 1: 149 pci_dev->config[MRDMODE] = 150 (pci_dev->config[MRDMODE] & ~0x30) | (val & 0x30); 151 cmd646_update_dma_interrupts(pci_dev); 152 cmd646_update_irq(pci_dev); 153 break; 154 case 2: 155 bm->status = (val & 0x60) | (bm->status & 1) | (bm->status & ~val & 0x06); 156 break; 157 case 3: 158 if (bm == &bm->pci_dev->bmdma[0]) { 159 pci_dev->config[UDIDETCR0] = val; 160 } else { 161 pci_dev->config[UDIDETCR1] = val; 162 } 163 break; 164 } 165 } 166 167 static const MemoryRegionOps cmd646_bmdma_ops = { 168 .read = bmdma_read, 169 .write = bmdma_write, 170 }; 171 172 static void bmdma_setup_bar(PCIIDEState *d) 173 { 174 BMDMAState *bm; 175 int i; 176 177 memory_region_init(&d->bmdma_bar, OBJECT(d), "cmd646-bmdma", 16); 178 for(i = 0;i < 2; i++) { 179 bm = &d->bmdma[i]; 180 memory_region_init_io(&bm->extra_io, OBJECT(d), &cmd646_bmdma_ops, bm, 181 "cmd646-bmdma-bus", 4); 182 memory_region_add_subregion(&d->bmdma_bar, i * 8, &bm->extra_io); 183 memory_region_init_io(&bm->addr_ioport, OBJECT(d), 184 &bmdma_addr_ioport_ops, bm, 185 "cmd646-bmdma-ioport", 4); 186 memory_region_add_subregion(&d->bmdma_bar, i * 8 + 4, &bm->addr_ioport); 187 } 188 } 189 190 static void cmd646_update_irq(PCIDevice *pd) 191 { 192 int pci_level; 193 194 pci_level = ((pd->config[MRDMODE] & MRDMODE_INTR_CH0) && 195 !(pd->config[MRDMODE] & MRDMODE_BLK_CH0)) || 196 ((pd->config[MRDMODE] & MRDMODE_INTR_CH1) && 197 !(pd->config[MRDMODE] & MRDMODE_BLK_CH1)); 198 pci_set_irq(pd, pci_level); 199 } 200 201 /* the PCI irq level is the logical OR of the two channels */ 202 static void cmd646_set_irq(void *opaque, int channel, int level) 203 { 204 PCIIDEState *d = opaque; 205 PCIDevice *pd = PCI_DEVICE(d); 206 int irq_mask; 207 208 irq_mask = MRDMODE_INTR_CH0 << channel; 209 if (level) { 210 pd->config[MRDMODE] |= irq_mask; 211 } else { 212 pd->config[MRDMODE] &= ~irq_mask; 213 } 214 cmd646_update_dma_interrupts(pd); 215 cmd646_update_irq(pd); 216 } 217 218 static void cmd646_reset(void *opaque) 219 { 220 PCIIDEState *d = opaque; 221 unsigned int i; 222 223 for (i = 0; i < 2; i++) { 224 ide_bus_reset(&d->bus[i]); 225 } 226 } 227 228 static uint32_t cmd646_pci_config_read(PCIDevice *d, 229 uint32_t address, int len) 230 { 231 return pci_default_read_config(d, address, len); 232 } 233 234 static void cmd646_pci_config_write(PCIDevice *d, uint32_t addr, uint32_t val, 235 int l) 236 { 237 uint32_t i; 238 239 pci_default_write_config(d, addr, val, l); 240 241 for (i = addr; i < addr + l; i++) { 242 switch (i) { 243 case CFR: 244 case ARTTIM23: 245 cmd646_update_udma_interrupts(d); 246 break; 247 case MRDMODE: 248 cmd646_update_dma_interrupts(d); 249 break; 250 } 251 } 252 253 cmd646_update_irq(d); 254 } 255 256 /* CMD646 PCI IDE controller */ 257 static void pci_cmd646_ide_realize(PCIDevice *dev, Error **errp) 258 { 259 PCIIDEState *d = PCI_IDE(dev); 260 uint8_t *pci_conf = dev->config; 261 qemu_irq *irq; 262 int i; 263 264 pci_conf[PCI_CLASS_PROG] = 0x8f; 265 266 pci_conf[CNTRL] = CNTRL_EN_CH0; // enable IDE0 267 if (d->secondary) { 268 /* XXX: if not enabled, really disable the seconday IDE controller */ 269 pci_conf[CNTRL] |= CNTRL_EN_CH1; /* enable IDE1 */ 270 } 271 272 /* Set write-to-clear interrupt bits */ 273 dev->wmask[CFR] = 0x0; 274 dev->w1cmask[CFR] = CFR_INTR_CH0; 275 dev->wmask[ARTTIM23] = 0x0; 276 dev->w1cmask[ARTTIM23] = ARTTIM23_INTR_CH1; 277 dev->wmask[MRDMODE] = 0x0; 278 dev->w1cmask[MRDMODE] = MRDMODE_INTR_CH0 | MRDMODE_INTR_CH1; 279 280 setup_cmd646_bar(d, 0); 281 setup_cmd646_bar(d, 1); 282 pci_register_bar(dev, 0, PCI_BASE_ADDRESS_SPACE_IO, &d->cmd646_bar[0].data); 283 pci_register_bar(dev, 1, PCI_BASE_ADDRESS_SPACE_IO, &d->cmd646_bar[0].cmd); 284 pci_register_bar(dev, 2, PCI_BASE_ADDRESS_SPACE_IO, &d->cmd646_bar[1].data); 285 pci_register_bar(dev, 3, PCI_BASE_ADDRESS_SPACE_IO, &d->cmd646_bar[1].cmd); 286 bmdma_setup_bar(d); 287 pci_register_bar(dev, 4, PCI_BASE_ADDRESS_SPACE_IO, &d->bmdma_bar); 288 289 /* TODO: RST# value should be 0 */ 290 pci_conf[PCI_INTERRUPT_PIN] = 0x01; // interrupt on pin 1 291 292 irq = qemu_allocate_irqs(cmd646_set_irq, d, 2); 293 for (i = 0; i < 2; i++) { 294 ide_bus_new(&d->bus[i], sizeof(d->bus[i]), DEVICE(dev), i, 2); 295 ide_init2(&d->bus[i], irq[i]); 296 297 bmdma_init(&d->bus[i], &d->bmdma[i], d); 298 d->bmdma[i].bus = &d->bus[i]; 299 ide_register_restart_cb(&d->bus[i]); 300 } 301 302 vmstate_register(DEVICE(dev), 0, &vmstate_ide_pci, d); 303 qemu_register_reset(cmd646_reset, d); 304 } 305 306 static void pci_cmd646_ide_exitfn(PCIDevice *dev) 307 { 308 PCIIDEState *d = PCI_IDE(dev); 309 unsigned i; 310 311 for (i = 0; i < 2; ++i) { 312 memory_region_del_subregion(&d->bmdma_bar, &d->bmdma[i].extra_io); 313 memory_region_del_subregion(&d->bmdma_bar, &d->bmdma[i].addr_ioport); 314 } 315 } 316 317 void pci_cmd646_ide_init(PCIBus *bus, DriveInfo **hd_table, 318 int secondary_ide_enabled) 319 { 320 PCIDevice *dev; 321 322 dev = pci_create(bus, -1, "cmd646-ide"); 323 qdev_prop_set_uint32(&dev->qdev, "secondary", secondary_ide_enabled); 324 qdev_init_nofail(&dev->qdev); 325 326 pci_ide_create_devs(dev, hd_table); 327 } 328 329 static Property cmd646_ide_properties[] = { 330 DEFINE_PROP_UINT32("secondary", PCIIDEState, secondary, 0), 331 DEFINE_PROP_END_OF_LIST(), 332 }; 333 334 static void cmd646_ide_class_init(ObjectClass *klass, void *data) 335 { 336 DeviceClass *dc = DEVICE_CLASS(klass); 337 PCIDeviceClass *k = PCI_DEVICE_CLASS(klass); 338 339 k->realize = pci_cmd646_ide_realize; 340 k->exit = pci_cmd646_ide_exitfn; 341 k->vendor_id = PCI_VENDOR_ID_CMD; 342 k->device_id = PCI_DEVICE_ID_CMD_646; 343 k->revision = 0x07; 344 k->class_id = PCI_CLASS_STORAGE_IDE; 345 k->config_read = cmd646_pci_config_read; 346 k->config_write = cmd646_pci_config_write; 347 dc->props = cmd646_ide_properties; 348 set_bit(DEVICE_CATEGORY_STORAGE, dc->categories); 349 } 350 351 static const TypeInfo cmd646_ide_info = { 352 .name = "cmd646-ide", 353 .parent = TYPE_PCI_IDE, 354 .class_init = cmd646_ide_class_init, 355 }; 356 357 static void cmd646_ide_register_types(void) 358 { 359 type_register_static(&cmd646_ide_info); 360 } 361 362 type_init(cmd646_ide_register_types) 363