1 /* 2 * QEMU IDE Emulation: PCI cmd646 support. 3 * 4 * Copyright (c) 2003 Fabrice Bellard 5 * Copyright (c) 2006 Openedhand Ltd. 6 * 7 * Permission is hereby granted, free of charge, to any person obtaining a copy 8 * of this software and associated documentation files (the "Software"), to deal 9 * in the Software without restriction, including without limitation the rights 10 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 11 * copies of the Software, and to permit persons to whom the Software is 12 * furnished to do so, subject to the following conditions: 13 * 14 * The above copyright notice and this permission notice shall be included in 15 * all copies or substantial portions of the Software. 16 * 17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 19 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 20 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 21 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 22 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN 23 * THE SOFTWARE. 24 */ 25 #include <hw/hw.h> 26 #include <hw/pc.h> 27 #include <hw/pci.h> 28 #include <hw/isa.h> 29 #include "block.h" 30 #include "block_int.h" 31 #include "sysemu.h" 32 #include "dma.h" 33 34 #include <hw/ide/pci.h> 35 36 /* CMD646 specific */ 37 #define MRDMODE 0x71 38 #define MRDMODE_INTR_CH0 0x04 39 #define MRDMODE_INTR_CH1 0x08 40 #define MRDMODE_BLK_CH0 0x10 41 #define MRDMODE_BLK_CH1 0x20 42 #define UDIDETCR0 0x73 43 #define UDIDETCR1 0x7B 44 45 static void cmd646_update_irq(PCIIDEState *d); 46 47 static void ide_map(PCIDevice *pci_dev, int region_num, 48 uint32_t addr, uint32_t size, int type) 49 { 50 PCIIDEState *d = DO_UPCAST(PCIIDEState, dev, pci_dev); 51 IDEBus *bus; 52 53 if (region_num <= 3) { 54 bus = &d->bus[(region_num >> 1)]; 55 if (region_num & 1) { 56 register_ioport_read(addr + 2, 1, 1, ide_status_read, bus); 57 register_ioport_write(addr + 2, 1, 1, ide_cmd_write, bus); 58 } else { 59 register_ioport_write(addr, 8, 1, ide_ioport_write, bus); 60 register_ioport_read(addr, 8, 1, ide_ioport_read, bus); 61 62 /* data ports */ 63 register_ioport_write(addr, 2, 2, ide_data_writew, bus); 64 register_ioport_read(addr, 2, 2, ide_data_readw, bus); 65 register_ioport_write(addr, 4, 4, ide_data_writel, bus); 66 register_ioport_read(addr, 4, 4, ide_data_readl, bus); 67 } 68 } 69 } 70 71 static uint32_t bmdma_readb(void *opaque, uint32_t addr) 72 { 73 BMDMAState *bm = opaque; 74 PCIIDEState *pci_dev; 75 uint32_t val; 76 77 switch(addr & 3) { 78 case 0: 79 val = bm->cmd; 80 break; 81 case 1: 82 pci_dev = bm->pci_dev; 83 val = pci_dev->dev.config[MRDMODE]; 84 break; 85 case 2: 86 val = bm->status; 87 break; 88 case 3: 89 pci_dev = bm->pci_dev; 90 if (bm == &pci_dev->bmdma[0]) { 91 val = pci_dev->dev.config[UDIDETCR0]; 92 } else { 93 val = pci_dev->dev.config[UDIDETCR1]; 94 } 95 break; 96 default: 97 val = 0xff; 98 break; 99 } 100 #ifdef DEBUG_IDE 101 printf("bmdma: readb 0x%02x : 0x%02x\n", addr, val); 102 #endif 103 return val; 104 } 105 106 static void bmdma_writeb(void *opaque, uint32_t addr, uint32_t val) 107 { 108 BMDMAState *bm = opaque; 109 PCIIDEState *pci_dev; 110 #ifdef DEBUG_IDE 111 printf("bmdma: writeb 0x%02x : 0x%02x\n", addr, val); 112 #endif 113 switch(addr & 3) { 114 case 1: 115 pci_dev = bm->pci_dev; 116 pci_dev->dev.config[MRDMODE] = 117 (pci_dev->dev.config[MRDMODE] & ~0x30) | (val & 0x30); 118 cmd646_update_irq(pci_dev); 119 break; 120 case 2: 121 bm->status = (val & 0x60) | (bm->status & 1) | (bm->status & ~val & 0x06); 122 break; 123 case 3: 124 pci_dev = bm->pci_dev; 125 if (bm == &pci_dev->bmdma[0]) 126 pci_dev->dev.config[UDIDETCR0] = val; 127 else 128 pci_dev->dev.config[UDIDETCR1] = val; 129 break; 130 } 131 } 132 133 static void bmdma_map(PCIDevice *pci_dev, int region_num, 134 uint32_t addr, uint32_t size, int type) 135 { 136 PCIIDEState *d = DO_UPCAST(PCIIDEState, dev, pci_dev); 137 int i; 138 139 for(i = 0;i < 2; i++) { 140 BMDMAState *bm = &d->bmdma[i]; 141 d->bus[i].bmdma = bm; 142 bm->pci_dev = DO_UPCAST(PCIIDEState, dev, pci_dev); 143 bm->bus = d->bus+i; 144 qemu_add_vm_change_state_handler(ide_dma_restart_cb, bm); 145 146 register_ioport_write(addr, 1, 1, bmdma_cmd_writeb, bm); 147 148 register_ioport_write(addr + 1, 3, 1, bmdma_writeb, bm); 149 register_ioport_read(addr, 4, 1, bmdma_readb, bm); 150 151 register_ioport_write(addr + 4, 4, 1, bmdma_addr_writeb, bm); 152 register_ioport_read(addr + 4, 4, 1, bmdma_addr_readb, bm); 153 register_ioport_write(addr + 4, 4, 2, bmdma_addr_writew, bm); 154 register_ioport_read(addr + 4, 4, 2, bmdma_addr_readw, bm); 155 register_ioport_write(addr + 4, 4, 4, bmdma_addr_writel, bm); 156 register_ioport_read(addr + 4, 4, 4, bmdma_addr_readl, bm); 157 addr += 8; 158 } 159 } 160 161 /* XXX: call it also when the MRDMODE is changed from the PCI config 162 registers */ 163 static void cmd646_update_irq(PCIIDEState *d) 164 { 165 int pci_level; 166 pci_level = ((d->dev.config[MRDMODE] & MRDMODE_INTR_CH0) && 167 !(d->dev.config[MRDMODE] & MRDMODE_BLK_CH0)) || 168 ((d->dev.config[MRDMODE] & MRDMODE_INTR_CH1) && 169 !(d->dev.config[MRDMODE] & MRDMODE_BLK_CH1)); 170 qemu_set_irq(d->dev.irq[0], pci_level); 171 } 172 173 /* the PCI irq level is the logical OR of the two channels */ 174 static void cmd646_set_irq(void *opaque, int channel, int level) 175 { 176 PCIIDEState *d = opaque; 177 int irq_mask; 178 179 irq_mask = MRDMODE_INTR_CH0 << channel; 180 if (level) 181 d->dev.config[MRDMODE] |= irq_mask; 182 else 183 d->dev.config[MRDMODE] &= ~irq_mask; 184 cmd646_update_irq(d); 185 } 186 187 static void cmd646_reset(void *opaque) 188 { 189 PCIIDEState *d = opaque; 190 unsigned int i; 191 192 for (i = 0; i < 2; i++) 193 ide_dma_cancel(&d->bmdma[i]); 194 } 195 196 /* CMD646 PCI IDE controller */ 197 static int pci_cmd646_ide_initfn(PCIDevice *dev) 198 { 199 PCIIDEState *d = DO_UPCAST(PCIIDEState, dev, dev); 200 uint8_t *pci_conf = d->dev.config; 201 qemu_irq *irq; 202 203 pci_config_set_vendor_id(pci_conf, PCI_VENDOR_ID_CMD); 204 pci_config_set_device_id(pci_conf, PCI_DEVICE_ID_CMD_646); 205 206 pci_conf[0x08] = 0x07; // IDE controller revision 207 pci_conf[0x09] = 0x8f; 208 209 pci_config_set_class(pci_conf, PCI_CLASS_STORAGE_IDE); 210 pci_conf[PCI_HEADER_TYPE] = PCI_HEADER_TYPE_NORMAL; // header_type 211 212 pci_conf[0x51] = 0x04; // enable IDE0 213 if (d->secondary) { 214 /* XXX: if not enabled, really disable the seconday IDE controller */ 215 pci_conf[0x51] |= 0x08; /* enable IDE1 */ 216 } 217 218 pci_register_bar(dev, 0, 0x8, PCI_ADDRESS_SPACE_IO, ide_map); 219 pci_register_bar(dev, 1, 0x4, PCI_ADDRESS_SPACE_IO, ide_map); 220 pci_register_bar(dev, 2, 0x8, PCI_ADDRESS_SPACE_IO, ide_map); 221 pci_register_bar(dev, 3, 0x4, PCI_ADDRESS_SPACE_IO, ide_map); 222 pci_register_bar(dev, 4, 0x10, PCI_ADDRESS_SPACE_IO, bmdma_map); 223 224 pci_conf[0x3d] = 0x01; // interrupt on pin 1 225 226 irq = qemu_allocate_irqs(cmd646_set_irq, d, 2); 227 ide_bus_new(&d->bus[0], &d->dev.qdev); 228 ide_bus_new(&d->bus[1], &d->dev.qdev); 229 ide_init2(&d->bus[0], NULL, NULL, irq[0]); 230 ide_init2(&d->bus[1], NULL, NULL, irq[1]); 231 232 register_savevm("ide", 0, 3, pci_ide_save, pci_ide_load, d); 233 qemu_register_reset(cmd646_reset, d); 234 cmd646_reset(d); 235 return 0; 236 } 237 238 void pci_cmd646_ide_init(PCIBus *bus, DriveInfo **hd_table, 239 int secondary_ide_enabled) 240 { 241 PCIDevice *dev; 242 243 dev = pci_create(bus, -1, "CMD646 IDE"); 244 qdev_prop_set_uint32(&dev->qdev, "secondary", secondary_ide_enabled); 245 qdev_init_nofail(&dev->qdev); 246 247 pci_ide_create_devs(dev, hd_table); 248 } 249 250 static PCIDeviceInfo cmd646_ide_info[] = { 251 { 252 .qdev.name = "CMD646 IDE", 253 .qdev.size = sizeof(PCIIDEState), 254 .init = pci_cmd646_ide_initfn, 255 .qdev.props = (Property[]) { 256 DEFINE_PROP_UINT32("secondary", PCIIDEState, secondary, 0), 257 DEFINE_PROP_END_OF_LIST(), 258 }, 259 },{ 260 /* end of list */ 261 } 262 }; 263 264 static void cmd646_ide_register(void) 265 { 266 pci_qdev_register_many(cmd646_ide_info); 267 } 268 device_init(cmd646_ide_register); 269