1 /* 2 * QEMU IDE Emulation: PCI cmd646 support. 3 * 4 * Copyright (c) 2003 Fabrice Bellard 5 * Copyright (c) 2006 Openedhand Ltd. 6 * 7 * Permission is hereby granted, free of charge, to any person obtaining a copy 8 * of this software and associated documentation files (the "Software"), to deal 9 * in the Software without restriction, including without limitation the rights 10 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 11 * copies of the Software, and to permit persons to whom the Software is 12 * furnished to do so, subject to the following conditions: 13 * 14 * The above copyright notice and this permission notice shall be included in 15 * all copies or substantial portions of the Software. 16 * 17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 19 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 20 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 21 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 22 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN 23 * THE SOFTWARE. 24 */ 25 #include <hw/hw.h> 26 #include <hw/i386/pc.h> 27 #include <hw/pci/pci.h> 28 #include <hw/isa/isa.h> 29 #include "block/block.h" 30 #include "sysemu/sysemu.h" 31 #include "sysemu/dma.h" 32 33 #include <hw/ide/pci.h> 34 35 /* CMD646 specific */ 36 #define CFR 0x50 37 #define CFR_INTR_CH0 0x04 38 #define CNTRL 0x51 39 #define CNTRL_EN_CH0 0x04 40 #define CNTRL_EN_CH1 0x08 41 #define ARTTIM23 0x57 42 #define ARTTIM23_INTR_CH1 0x10 43 #define MRDMODE 0x71 44 #define MRDMODE_INTR_CH0 0x04 45 #define MRDMODE_INTR_CH1 0x08 46 #define MRDMODE_BLK_CH0 0x10 47 #define MRDMODE_BLK_CH1 0x20 48 #define UDIDETCR0 0x73 49 #define UDIDETCR1 0x7B 50 51 static void cmd646_update_irq(PCIDevice *pd); 52 53 static uint64_t cmd646_cmd_read(void *opaque, hwaddr addr, 54 unsigned size) 55 { 56 CMD646BAR *cmd646bar = opaque; 57 58 if (addr != 2 || size != 1) { 59 return ((uint64_t)1 << (size * 8)) - 1; 60 } 61 return ide_status_read(cmd646bar->bus, addr + 2); 62 } 63 64 static void cmd646_cmd_write(void *opaque, hwaddr addr, 65 uint64_t data, unsigned size) 66 { 67 CMD646BAR *cmd646bar = opaque; 68 69 if (addr != 2 || size != 1) { 70 return; 71 } 72 ide_cmd_write(cmd646bar->bus, addr + 2, data); 73 } 74 75 static const MemoryRegionOps cmd646_cmd_ops = { 76 .read = cmd646_cmd_read, 77 .write = cmd646_cmd_write, 78 .endianness = DEVICE_LITTLE_ENDIAN, 79 }; 80 81 static uint64_t cmd646_data_read(void *opaque, hwaddr addr, 82 unsigned size) 83 { 84 CMD646BAR *cmd646bar = opaque; 85 86 if (size == 1) { 87 return ide_ioport_read(cmd646bar->bus, addr); 88 } else if (addr == 0) { 89 if (size == 2) { 90 return ide_data_readw(cmd646bar->bus, addr); 91 } else { 92 return ide_data_readl(cmd646bar->bus, addr); 93 } 94 } 95 return ((uint64_t)1 << (size * 8)) - 1; 96 } 97 98 static void cmd646_data_write(void *opaque, hwaddr addr, 99 uint64_t data, unsigned size) 100 { 101 CMD646BAR *cmd646bar = opaque; 102 103 if (size == 1) { 104 ide_ioport_write(cmd646bar->bus, addr, data); 105 } else if (addr == 0) { 106 if (size == 2) { 107 ide_data_writew(cmd646bar->bus, addr, data); 108 } else { 109 ide_data_writel(cmd646bar->bus, addr, data); 110 } 111 } 112 } 113 114 static const MemoryRegionOps cmd646_data_ops = { 115 .read = cmd646_data_read, 116 .write = cmd646_data_write, 117 .endianness = DEVICE_LITTLE_ENDIAN, 118 }; 119 120 static void setup_cmd646_bar(PCIIDEState *d, int bus_num) 121 { 122 IDEBus *bus = &d->bus[bus_num]; 123 CMD646BAR *bar = &d->cmd646_bar[bus_num]; 124 125 bar->bus = bus; 126 bar->pci_dev = d; 127 memory_region_init_io(&bar->cmd, OBJECT(d), &cmd646_cmd_ops, bar, 128 "cmd646-cmd", 4); 129 memory_region_init_io(&bar->data, OBJECT(d), &cmd646_data_ops, bar, 130 "cmd646-data", 8); 131 } 132 133 static void cmd646_update_dma_interrupts(PCIDevice *pd) 134 { 135 /* Sync DMA interrupt status from UDMA interrupt status */ 136 if (pd->config[MRDMODE] & MRDMODE_INTR_CH0) { 137 pd->config[CFR] |= CFR_INTR_CH0; 138 } else { 139 pd->config[CFR] &= ~CFR_INTR_CH0; 140 } 141 142 if (pd->config[MRDMODE] & MRDMODE_INTR_CH1) { 143 pd->config[ARTTIM23] |= ARTTIM23_INTR_CH1; 144 } else { 145 pd->config[ARTTIM23] &= ~ARTTIM23_INTR_CH1; 146 } 147 } 148 149 static uint64_t bmdma_read(void *opaque, hwaddr addr, 150 unsigned size) 151 { 152 BMDMAState *bm = opaque; 153 PCIDevice *pci_dev = PCI_DEVICE(bm->pci_dev); 154 uint32_t val; 155 156 if (size != 1) { 157 return ((uint64_t)1 << (size * 8)) - 1; 158 } 159 160 switch(addr & 3) { 161 case 0: 162 val = bm->cmd; 163 break; 164 case 1: 165 val = pci_dev->config[MRDMODE]; 166 break; 167 case 2: 168 val = bm->status; 169 break; 170 case 3: 171 if (bm == &bm->pci_dev->bmdma[0]) { 172 val = pci_dev->config[UDIDETCR0]; 173 } else { 174 val = pci_dev->config[UDIDETCR1]; 175 } 176 break; 177 default: 178 val = 0xff; 179 break; 180 } 181 #ifdef DEBUG_IDE 182 printf("bmdma: readb " TARGET_FMT_plx " : 0x%02x\n", addr, val); 183 #endif 184 return val; 185 } 186 187 static void bmdma_write(void *opaque, hwaddr addr, 188 uint64_t val, unsigned size) 189 { 190 BMDMAState *bm = opaque; 191 PCIDevice *pci_dev = PCI_DEVICE(bm->pci_dev); 192 193 if (size != 1) { 194 return; 195 } 196 197 #ifdef DEBUG_IDE 198 printf("bmdma: writeb " TARGET_FMT_plx " : 0x%" PRIx64 "\n", addr, val); 199 #endif 200 switch(addr & 3) { 201 case 0: 202 bmdma_cmd_writeb(bm, val); 203 break; 204 case 1: 205 pci_dev->config[MRDMODE] = 206 (pci_dev->config[MRDMODE] & ~0x30) | (val & 0x30); 207 cmd646_update_dma_interrupts(pci_dev); 208 cmd646_update_irq(pci_dev); 209 break; 210 case 2: 211 bm->status = (val & 0x60) | (bm->status & 1) | (bm->status & ~val & 0x06); 212 break; 213 case 3: 214 if (bm == &bm->pci_dev->bmdma[0]) { 215 pci_dev->config[UDIDETCR0] = val; 216 } else { 217 pci_dev->config[UDIDETCR1] = val; 218 } 219 break; 220 } 221 } 222 223 static const MemoryRegionOps cmd646_bmdma_ops = { 224 .read = bmdma_read, 225 .write = bmdma_write, 226 }; 227 228 static void bmdma_setup_bar(PCIIDEState *d) 229 { 230 BMDMAState *bm; 231 int i; 232 233 memory_region_init(&d->bmdma_bar, OBJECT(d), "cmd646-bmdma", 16); 234 for(i = 0;i < 2; i++) { 235 bm = &d->bmdma[i]; 236 memory_region_init_io(&bm->extra_io, OBJECT(d), &cmd646_bmdma_ops, bm, 237 "cmd646-bmdma-bus", 4); 238 memory_region_add_subregion(&d->bmdma_bar, i * 8, &bm->extra_io); 239 memory_region_init_io(&bm->addr_ioport, OBJECT(d), 240 &bmdma_addr_ioport_ops, bm, 241 "cmd646-bmdma-ioport", 4); 242 memory_region_add_subregion(&d->bmdma_bar, i * 8 + 4, &bm->addr_ioport); 243 } 244 } 245 246 static void cmd646_update_irq(PCIDevice *pd) 247 { 248 int pci_level; 249 250 pci_level = ((pd->config[MRDMODE] & MRDMODE_INTR_CH0) && 251 !(pd->config[MRDMODE] & MRDMODE_BLK_CH0)) || 252 ((pd->config[MRDMODE] & MRDMODE_INTR_CH1) && 253 !(pd->config[MRDMODE] & MRDMODE_BLK_CH1)); 254 pci_set_irq(pd, pci_level); 255 } 256 257 /* the PCI irq level is the logical OR of the two channels */ 258 static void cmd646_set_irq(void *opaque, int channel, int level) 259 { 260 PCIIDEState *d = opaque; 261 PCIDevice *pd = PCI_DEVICE(d); 262 int irq_mask; 263 264 irq_mask = MRDMODE_INTR_CH0 << channel; 265 if (level) { 266 pd->config[MRDMODE] |= irq_mask; 267 } else { 268 pd->config[MRDMODE] &= ~irq_mask; 269 } 270 cmd646_update_dma_interrupts(pd); 271 cmd646_update_irq(pd); 272 } 273 274 static void cmd646_reset(void *opaque) 275 { 276 PCIIDEState *d = opaque; 277 unsigned int i; 278 279 for (i = 0; i < 2; i++) { 280 ide_bus_reset(&d->bus[i]); 281 } 282 } 283 284 static uint32_t cmd646_pci_config_read(PCIDevice *d, 285 uint32_t address, int len) 286 { 287 return pci_default_read_config(d, address, len); 288 } 289 290 static void cmd646_pci_config_write(PCIDevice *d, uint32_t addr, uint32_t val, 291 int l) 292 { 293 uint32_t i; 294 295 pci_default_write_config(d, addr, val, l); 296 297 for (i = addr; i < addr + l; i++) { 298 switch (i) { 299 case MRDMODE: 300 cmd646_update_dma_interrupts(d); 301 break; 302 } 303 } 304 305 cmd646_update_irq(d); 306 } 307 308 /* CMD646 PCI IDE controller */ 309 static int pci_cmd646_ide_initfn(PCIDevice *dev) 310 { 311 PCIIDEState *d = PCI_IDE(dev); 312 uint8_t *pci_conf = dev->config; 313 qemu_irq *irq; 314 int i; 315 316 pci_conf[PCI_CLASS_PROG] = 0x8f; 317 318 pci_conf[CNTRL] = CNTRL_EN_CH0; // enable IDE0 319 if (d->secondary) { 320 /* XXX: if not enabled, really disable the seconday IDE controller */ 321 pci_conf[CNTRL] |= CNTRL_EN_CH1; /* enable IDE1 */ 322 } 323 324 /* Set write-to-clear interrupt bits */ 325 dev->wmask[MRDMODE] = 0x0; 326 dev->w1cmask[MRDMODE] = MRDMODE_INTR_CH0 | MRDMODE_INTR_CH1; 327 328 setup_cmd646_bar(d, 0); 329 setup_cmd646_bar(d, 1); 330 pci_register_bar(dev, 0, PCI_BASE_ADDRESS_SPACE_IO, &d->cmd646_bar[0].data); 331 pci_register_bar(dev, 1, PCI_BASE_ADDRESS_SPACE_IO, &d->cmd646_bar[0].cmd); 332 pci_register_bar(dev, 2, PCI_BASE_ADDRESS_SPACE_IO, &d->cmd646_bar[1].data); 333 pci_register_bar(dev, 3, PCI_BASE_ADDRESS_SPACE_IO, &d->cmd646_bar[1].cmd); 334 bmdma_setup_bar(d); 335 pci_register_bar(dev, 4, PCI_BASE_ADDRESS_SPACE_IO, &d->bmdma_bar); 336 337 /* TODO: RST# value should be 0 */ 338 pci_conf[PCI_INTERRUPT_PIN] = 0x01; // interrupt on pin 1 339 340 irq = qemu_allocate_irqs(cmd646_set_irq, d, 2); 341 for (i = 0; i < 2; i++) { 342 ide_bus_new(&d->bus[i], sizeof(d->bus[i]), DEVICE(dev), i, 2); 343 ide_init2(&d->bus[i], irq[i]); 344 345 bmdma_init(&d->bus[i], &d->bmdma[i], d); 346 d->bmdma[i].bus = &d->bus[i]; 347 qemu_add_vm_change_state_handler(d->bus[i].dma->ops->restart_cb, 348 &d->bmdma[i].dma); 349 } 350 351 vmstate_register(DEVICE(dev), 0, &vmstate_ide_pci, d); 352 qemu_register_reset(cmd646_reset, d); 353 return 0; 354 } 355 356 static void pci_cmd646_ide_exitfn(PCIDevice *dev) 357 { 358 PCIIDEState *d = PCI_IDE(dev); 359 unsigned i; 360 361 for (i = 0; i < 2; ++i) { 362 memory_region_del_subregion(&d->bmdma_bar, &d->bmdma[i].extra_io); 363 memory_region_destroy(&d->bmdma[i].extra_io); 364 memory_region_del_subregion(&d->bmdma_bar, &d->bmdma[i].addr_ioport); 365 memory_region_destroy(&d->bmdma[i].addr_ioport); 366 memory_region_destroy(&d->cmd646_bar[i].cmd); 367 memory_region_destroy(&d->cmd646_bar[i].data); 368 } 369 memory_region_destroy(&d->bmdma_bar); 370 } 371 372 void pci_cmd646_ide_init(PCIBus *bus, DriveInfo **hd_table, 373 int secondary_ide_enabled) 374 { 375 PCIDevice *dev; 376 377 dev = pci_create(bus, -1, "cmd646-ide"); 378 qdev_prop_set_uint32(&dev->qdev, "secondary", secondary_ide_enabled); 379 qdev_init_nofail(&dev->qdev); 380 381 pci_ide_create_devs(dev, hd_table); 382 } 383 384 static Property cmd646_ide_properties[] = { 385 DEFINE_PROP_UINT32("secondary", PCIIDEState, secondary, 0), 386 DEFINE_PROP_END_OF_LIST(), 387 }; 388 389 static void cmd646_ide_class_init(ObjectClass *klass, void *data) 390 { 391 DeviceClass *dc = DEVICE_CLASS(klass); 392 PCIDeviceClass *k = PCI_DEVICE_CLASS(klass); 393 394 k->init = pci_cmd646_ide_initfn; 395 k->exit = pci_cmd646_ide_exitfn; 396 k->vendor_id = PCI_VENDOR_ID_CMD; 397 k->device_id = PCI_DEVICE_ID_CMD_646; 398 k->revision = 0x07; 399 k->class_id = PCI_CLASS_STORAGE_IDE; 400 k->config_read = cmd646_pci_config_read; 401 k->config_write = cmd646_pci_config_write; 402 dc->props = cmd646_ide_properties; 403 } 404 405 static const TypeInfo cmd646_ide_info = { 406 .name = "cmd646-ide", 407 .parent = TYPE_PCI_IDE, 408 .class_init = cmd646_ide_class_init, 409 }; 410 411 static void cmd646_ide_register_types(void) 412 { 413 type_register_static(&cmd646_ide_info); 414 } 415 416 type_init(cmd646_ide_register_types) 417