1 /* 2 * QEMU IDE Emulation: PCI cmd646 support. 3 * 4 * Copyright (c) 2003 Fabrice Bellard 5 * Copyright (c) 2006 Openedhand Ltd. 6 * 7 * Permission is hereby granted, free of charge, to any person obtaining a copy 8 * of this software and associated documentation files (the "Software"), to deal 9 * in the Software without restriction, including without limitation the rights 10 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 11 * copies of the Software, and to permit persons to whom the Software is 12 * furnished to do so, subject to the following conditions: 13 * 14 * The above copyright notice and this permission notice shall be included in 15 * all copies or substantial portions of the Software. 16 * 17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 19 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 20 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 21 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 22 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN 23 * THE SOFTWARE. 24 */ 25 #include <hw/hw.h> 26 #include <hw/pc.h> 27 #include <hw/pci.h> 28 #include <hw/isa.h> 29 #include "block.h" 30 #include "sysemu.h" 31 #include "dma.h" 32 33 #include <hw/ide/pci.h> 34 35 /* CMD646 specific */ 36 #define MRDMODE 0x71 37 #define MRDMODE_INTR_CH0 0x04 38 #define MRDMODE_INTR_CH1 0x08 39 #define MRDMODE_BLK_CH0 0x10 40 #define MRDMODE_BLK_CH1 0x20 41 #define UDIDETCR0 0x73 42 #define UDIDETCR1 0x7B 43 44 static void cmd646_update_irq(PCIIDEState *d); 45 46 static uint64_t cmd646_cmd_read(void *opaque, target_phys_addr_t addr, 47 unsigned size) 48 { 49 CMD646BAR *cmd646bar = opaque; 50 51 if (addr != 2 || size != 1) { 52 return ((uint64_t)1 << (size * 8)) - 1; 53 } 54 return ide_status_read(cmd646bar->bus, addr + 2); 55 } 56 57 static void cmd646_cmd_write(void *opaque, target_phys_addr_t addr, 58 uint64_t data, unsigned size) 59 { 60 CMD646BAR *cmd646bar = opaque; 61 62 if (addr != 2 || size != 1) { 63 return; 64 } 65 ide_cmd_write(cmd646bar->bus, addr + 2, data); 66 } 67 68 static const MemoryRegionOps cmd646_cmd_ops = { 69 .read = cmd646_cmd_read, 70 .write = cmd646_cmd_write, 71 .endianness = DEVICE_LITTLE_ENDIAN, 72 }; 73 74 static uint64_t cmd646_data_read(void *opaque, target_phys_addr_t addr, 75 unsigned size) 76 { 77 CMD646BAR *cmd646bar = opaque; 78 79 if (size == 1) { 80 return ide_ioport_read(cmd646bar->bus, addr); 81 } else if (addr == 0) { 82 if (size == 2) { 83 return ide_data_readw(cmd646bar->bus, addr); 84 } else { 85 return ide_data_readl(cmd646bar->bus, addr); 86 } 87 } 88 return ((uint64_t)1 << (size * 8)) - 1; 89 } 90 91 static void cmd646_data_write(void *opaque, target_phys_addr_t addr, 92 uint64_t data, unsigned size) 93 { 94 CMD646BAR *cmd646bar = opaque; 95 96 if (size == 1) { 97 ide_ioport_write(cmd646bar->bus, addr, data); 98 } else if (addr == 0) { 99 if (size == 2) { 100 ide_data_writew(cmd646bar->bus, addr, data); 101 } else { 102 ide_data_writel(cmd646bar->bus, addr, data); 103 } 104 } 105 } 106 107 static const MemoryRegionOps cmd646_data_ops = { 108 .read = cmd646_data_read, 109 .write = cmd646_data_write, 110 .endianness = DEVICE_LITTLE_ENDIAN, 111 }; 112 113 static void setup_cmd646_bar(PCIIDEState *d, int bus_num) 114 { 115 IDEBus *bus = &d->bus[bus_num]; 116 CMD646BAR *bar = &d->cmd646_bar[bus_num]; 117 118 bar->bus = bus; 119 bar->pci_dev = d; 120 memory_region_init_io(&bar->cmd, &cmd646_cmd_ops, bar, "cmd646-cmd", 4); 121 memory_region_init_io(&bar->data, &cmd646_data_ops, bar, "cmd646-data", 8); 122 } 123 124 static uint64_t bmdma_read(void *opaque, target_phys_addr_t addr, 125 unsigned size) 126 { 127 BMDMAState *bm = opaque; 128 PCIIDEState *pci_dev = bm->pci_dev; 129 uint32_t val; 130 131 if (size != 1) { 132 return ((uint64_t)1 << (size * 8)) - 1; 133 } 134 135 switch(addr & 3) { 136 case 0: 137 val = bm->cmd; 138 break; 139 case 1: 140 val = pci_dev->dev.config[MRDMODE]; 141 break; 142 case 2: 143 val = bm->status; 144 break; 145 case 3: 146 if (bm == &pci_dev->bmdma[0]) { 147 val = pci_dev->dev.config[UDIDETCR0]; 148 } else { 149 val = pci_dev->dev.config[UDIDETCR1]; 150 } 151 break; 152 default: 153 val = 0xff; 154 break; 155 } 156 #ifdef DEBUG_IDE 157 printf("bmdma: readb 0x%02" TARGET_PRIxPHYS " : 0x%02x\n", addr, val); 158 #endif 159 return val; 160 } 161 162 static void bmdma_write(void *opaque, target_phys_addr_t addr, 163 uint64_t val, unsigned size) 164 { 165 BMDMAState *bm = opaque; 166 PCIIDEState *pci_dev = bm->pci_dev; 167 168 if (size != 1) { 169 return; 170 } 171 172 #ifdef DEBUG_IDE 173 printf("bmdma: writeb 0x%02" TARGET_PRIxPHYS " : 0x%02" PRIx64 "\n", 174 addr, val); 175 #endif 176 switch(addr & 3) { 177 case 0: 178 bmdma_cmd_writeb(bm, val); 179 break; 180 case 1: 181 pci_dev->dev.config[MRDMODE] = 182 (pci_dev->dev.config[MRDMODE] & ~0x30) | (val & 0x30); 183 cmd646_update_irq(pci_dev); 184 break; 185 case 2: 186 bm->status = (val & 0x60) | (bm->status & 1) | (bm->status & ~val & 0x06); 187 break; 188 case 3: 189 if (bm == &pci_dev->bmdma[0]) 190 pci_dev->dev.config[UDIDETCR0] = val; 191 else 192 pci_dev->dev.config[UDIDETCR1] = val; 193 break; 194 } 195 } 196 197 static const MemoryRegionOps cmd646_bmdma_ops = { 198 .read = bmdma_read, 199 .write = bmdma_write, 200 }; 201 202 static void bmdma_setup_bar(PCIIDEState *d) 203 { 204 BMDMAState *bm; 205 int i; 206 207 memory_region_init(&d->bmdma_bar, "cmd646-bmdma", 16); 208 for(i = 0;i < 2; i++) { 209 bm = &d->bmdma[i]; 210 memory_region_init_io(&bm->extra_io, &cmd646_bmdma_ops, bm, 211 "cmd646-bmdma-bus", 4); 212 memory_region_add_subregion(&d->bmdma_bar, i * 8, &bm->extra_io); 213 memory_region_init_io(&bm->addr_ioport, &bmdma_addr_ioport_ops, bm, 214 "cmd646-bmdma-ioport", 4); 215 memory_region_add_subregion(&d->bmdma_bar, i * 8 + 4, &bm->addr_ioport); 216 } 217 } 218 219 /* XXX: call it also when the MRDMODE is changed from the PCI config 220 registers */ 221 static void cmd646_update_irq(PCIIDEState *d) 222 { 223 int pci_level; 224 pci_level = ((d->dev.config[MRDMODE] & MRDMODE_INTR_CH0) && 225 !(d->dev.config[MRDMODE] & MRDMODE_BLK_CH0)) || 226 ((d->dev.config[MRDMODE] & MRDMODE_INTR_CH1) && 227 !(d->dev.config[MRDMODE] & MRDMODE_BLK_CH1)); 228 qemu_set_irq(d->dev.irq[0], pci_level); 229 } 230 231 /* the PCI irq level is the logical OR of the two channels */ 232 static void cmd646_set_irq(void *opaque, int channel, int level) 233 { 234 PCIIDEState *d = opaque; 235 int irq_mask; 236 237 irq_mask = MRDMODE_INTR_CH0 << channel; 238 if (level) 239 d->dev.config[MRDMODE] |= irq_mask; 240 else 241 d->dev.config[MRDMODE] &= ~irq_mask; 242 cmd646_update_irq(d); 243 } 244 245 static void cmd646_reset(void *opaque) 246 { 247 PCIIDEState *d = opaque; 248 unsigned int i; 249 250 for (i = 0; i < 2; i++) { 251 ide_bus_reset(&d->bus[i]); 252 } 253 } 254 255 /* CMD646 PCI IDE controller */ 256 static int pci_cmd646_ide_initfn(PCIDevice *dev) 257 { 258 PCIIDEState *d = DO_UPCAST(PCIIDEState, dev, dev); 259 uint8_t *pci_conf = d->dev.config; 260 qemu_irq *irq; 261 int i; 262 263 pci_conf[PCI_CLASS_PROG] = 0x8f; 264 265 pci_conf[0x51] = 0x04; // enable IDE0 266 if (d->secondary) { 267 /* XXX: if not enabled, really disable the seconday IDE controller */ 268 pci_conf[0x51] |= 0x08; /* enable IDE1 */ 269 } 270 271 setup_cmd646_bar(d, 0); 272 setup_cmd646_bar(d, 1); 273 pci_register_bar(dev, 0, PCI_BASE_ADDRESS_SPACE_IO, &d->cmd646_bar[0].data); 274 pci_register_bar(dev, 1, PCI_BASE_ADDRESS_SPACE_IO, &d->cmd646_bar[0].cmd); 275 pci_register_bar(dev, 2, PCI_BASE_ADDRESS_SPACE_IO, &d->cmd646_bar[1].data); 276 pci_register_bar(dev, 3, PCI_BASE_ADDRESS_SPACE_IO, &d->cmd646_bar[1].cmd); 277 bmdma_setup_bar(d); 278 pci_register_bar(dev, 4, PCI_BASE_ADDRESS_SPACE_IO, &d->bmdma_bar); 279 280 /* TODO: RST# value should be 0 */ 281 pci_conf[PCI_INTERRUPT_PIN] = 0x01; // interrupt on pin 1 282 283 irq = qemu_allocate_irqs(cmd646_set_irq, d, 2); 284 for (i = 0; i < 2; i++) { 285 ide_bus_new(&d->bus[i], &d->dev.qdev, i); 286 ide_init2(&d->bus[i], irq[i]); 287 288 bmdma_init(&d->bus[i], &d->bmdma[i], d); 289 d->bmdma[i].bus = &d->bus[i]; 290 qemu_add_vm_change_state_handler(d->bus[i].dma->ops->restart_cb, 291 &d->bmdma[i].dma); 292 } 293 294 vmstate_register(&dev->qdev, 0, &vmstate_ide_pci, d); 295 qemu_register_reset(cmd646_reset, d); 296 return 0; 297 } 298 299 static void pci_cmd646_ide_exitfn(PCIDevice *dev) 300 { 301 PCIIDEState *d = DO_UPCAST(PCIIDEState, dev, dev); 302 unsigned i; 303 304 for (i = 0; i < 2; ++i) { 305 memory_region_del_subregion(&d->bmdma_bar, &d->bmdma[i].extra_io); 306 memory_region_destroy(&d->bmdma[i].extra_io); 307 memory_region_del_subregion(&d->bmdma_bar, &d->bmdma[i].addr_ioport); 308 memory_region_destroy(&d->bmdma[i].addr_ioport); 309 memory_region_destroy(&d->cmd646_bar[i].cmd); 310 memory_region_destroy(&d->cmd646_bar[i].data); 311 } 312 memory_region_destroy(&d->bmdma_bar); 313 } 314 315 void pci_cmd646_ide_init(PCIBus *bus, DriveInfo **hd_table, 316 int secondary_ide_enabled) 317 { 318 PCIDevice *dev; 319 320 dev = pci_create(bus, -1, "cmd646-ide"); 321 qdev_prop_set_uint32(&dev->qdev, "secondary", secondary_ide_enabled); 322 qdev_init_nofail(&dev->qdev); 323 324 pci_ide_create_devs(dev, hd_table); 325 } 326 327 static Property cmd646_ide_properties[] = { 328 DEFINE_PROP_UINT32("secondary", PCIIDEState, secondary, 0), 329 DEFINE_PROP_END_OF_LIST(), 330 }; 331 332 static void cmd646_ide_class_init(ObjectClass *klass, void *data) 333 { 334 DeviceClass *dc = DEVICE_CLASS(klass); 335 PCIDeviceClass *k = PCI_DEVICE_CLASS(klass); 336 337 k->init = pci_cmd646_ide_initfn; 338 k->exit = pci_cmd646_ide_exitfn; 339 k->vendor_id = PCI_VENDOR_ID_CMD; 340 k->device_id = PCI_DEVICE_ID_CMD_646; 341 k->revision = 0x07; 342 k->class_id = PCI_CLASS_STORAGE_IDE; 343 dc->props = cmd646_ide_properties; 344 } 345 346 static TypeInfo cmd646_ide_info = { 347 .name = "cmd646-ide", 348 .parent = TYPE_PCI_DEVICE, 349 .instance_size = sizeof(PCIIDEState), 350 .class_init = cmd646_ide_class_init, 351 }; 352 353 static void cmd646_ide_register_types(void) 354 { 355 type_register_static(&cmd646_ide_info); 356 } 357 358 type_init(cmd646_ide_register_types) 359