1 /* 2 * QEMU AHCI Emulation 3 * 4 * Copyright (c) 2010 qiaochong@loongson.cn 5 * Copyright (c) 2010 Roland Elek <elek.roland@gmail.com> 6 * Copyright (c) 2010 Sebastian Herbszt <herbszt@gmx.de> 7 * Copyright (c) 2010 Alexander Graf <agraf@suse.de> 8 * 9 * This library is free software; you can redistribute it and/or 10 * modify it under the terms of the GNU Lesser General Public 11 * License as published by the Free Software Foundation; either 12 * version 2.1 of the License, or (at your option) any later version. 13 * 14 * This library is distributed in the hope that it will be useful, 15 * but WITHOUT ANY WARRANTY; without even the implied warranty of 16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 17 * Lesser General Public License for more details. 18 * 19 * You should have received a copy of the GNU Lesser General Public 20 * License along with this library; if not, see <http://www.gnu.org/licenses/>. 21 * 22 */ 23 24 #include "qemu/osdep.h" 25 #include "hw/irq.h" 26 #include "migration/vmstate.h" 27 28 #include "qemu/error-report.h" 29 #include "qemu/log.h" 30 #include "qemu/main-loop.h" 31 #include "system/block-backend.h" 32 #include "system/dma.h" 33 #include "ahci-internal.h" 34 #include "ide-internal.h" 35 36 #include "trace.h" 37 38 static void check_cmd(AHCIState *s, int port); 39 static void handle_cmd(AHCIState *s, int port, uint8_t slot); 40 static void ahci_reset_port(AHCIState *s, int port); 41 static bool ahci_write_fis_d2h(AHCIDevice *ad, bool d2h_fis_i); 42 static void ahci_clear_cmd_issue(AHCIDevice *ad, uint8_t slot); 43 static void ahci_init_d2h(AHCIDevice *ad); 44 static int ahci_dma_prepare_buf(const IDEDMA *dma, int32_t limit); 45 static bool ahci_map_clb_address(AHCIDevice *ad); 46 static bool ahci_map_fis_address(AHCIDevice *ad); 47 static void ahci_unmap_clb_address(AHCIDevice *ad); 48 static void ahci_unmap_fis_address(AHCIDevice *ad); 49 50 static const char *AHCIHostReg_lookup[AHCI_HOST_REG__COUNT] = { 51 [AHCI_HOST_REG_CAP] = "CAP", 52 [AHCI_HOST_REG_CTL] = "GHC", 53 [AHCI_HOST_REG_IRQ_STAT] = "IS", 54 [AHCI_HOST_REG_PORTS_IMPL] = "PI", 55 [AHCI_HOST_REG_VERSION] = "VS", 56 [AHCI_HOST_REG_CCC_CTL] = "CCC_CTL", 57 [AHCI_HOST_REG_CCC_PORTS] = "CCC_PORTS", 58 [AHCI_HOST_REG_EM_LOC] = "EM_LOC", 59 [AHCI_HOST_REG_EM_CTL] = "EM_CTL", 60 [AHCI_HOST_REG_CAP2] = "CAP2", 61 [AHCI_HOST_REG_BOHC] = "BOHC", 62 }; 63 64 static const char *AHCIPortReg_lookup[AHCI_PORT_REG__COUNT] = { 65 [AHCI_PORT_REG_LST_ADDR] = "PxCLB", 66 [AHCI_PORT_REG_LST_ADDR_HI] = "PxCLBU", 67 [AHCI_PORT_REG_FIS_ADDR] = "PxFB", 68 [AHCI_PORT_REG_FIS_ADDR_HI] = "PxFBU", 69 [AHCI_PORT_REG_IRQ_STAT] = "PxIS", 70 [AHCI_PORT_REG_IRQ_MASK] = "PXIE", 71 [AHCI_PORT_REG_CMD] = "PxCMD", 72 [7] = "Reserved", 73 [AHCI_PORT_REG_TFDATA] = "PxTFD", 74 [AHCI_PORT_REG_SIG] = "PxSIG", 75 [AHCI_PORT_REG_SCR_STAT] = "PxSSTS", 76 [AHCI_PORT_REG_SCR_CTL] = "PxSCTL", 77 [AHCI_PORT_REG_SCR_ERR] = "PxSERR", 78 [AHCI_PORT_REG_SCR_ACT] = "PxSACT", 79 [AHCI_PORT_REG_CMD_ISSUE] = "PxCI", 80 [AHCI_PORT_REG_SCR_NOTIF] = "PxSNTF", 81 [AHCI_PORT_REG_FIS_CTL] = "PxFBS", 82 [AHCI_PORT_REG_DEV_SLEEP] = "PxDEVSLP", 83 [18 ... 27] = "Reserved", 84 [AHCI_PORT_REG_VENDOR_1 ... 85 AHCI_PORT_REG_VENDOR_4] = "PxVS", 86 }; 87 88 static const char *AHCIPortIRQ_lookup[AHCI_PORT_IRQ__COUNT] = { 89 [AHCI_PORT_IRQ_BIT_DHRS] = "DHRS", 90 [AHCI_PORT_IRQ_BIT_PSS] = "PSS", 91 [AHCI_PORT_IRQ_BIT_DSS] = "DSS", 92 [AHCI_PORT_IRQ_BIT_SDBS] = "SDBS", 93 [AHCI_PORT_IRQ_BIT_UFS] = "UFS", 94 [AHCI_PORT_IRQ_BIT_DPS] = "DPS", 95 [AHCI_PORT_IRQ_BIT_PCS] = "PCS", 96 [AHCI_PORT_IRQ_BIT_DMPS] = "DMPS", 97 [8 ... 21] = "RESERVED", 98 [AHCI_PORT_IRQ_BIT_PRCS] = "PRCS", 99 [AHCI_PORT_IRQ_BIT_IPMS] = "IPMS", 100 [AHCI_PORT_IRQ_BIT_OFS] = "OFS", 101 [25] = "RESERVED", 102 [AHCI_PORT_IRQ_BIT_INFS] = "INFS", 103 [AHCI_PORT_IRQ_BIT_IFS] = "IFS", 104 [AHCI_PORT_IRQ_BIT_HBDS] = "HBDS", 105 [AHCI_PORT_IRQ_BIT_HBFS] = "HBFS", 106 [AHCI_PORT_IRQ_BIT_TFES] = "TFES", 107 [AHCI_PORT_IRQ_BIT_CPDS] = "CPDS" 108 }; 109 110 static uint32_t ahci_port_read(AHCIState *s, int port, int offset) 111 { 112 uint32_t val; 113 AHCIPortRegs *pr = &s->dev[port].port_regs; 114 enum AHCIPortReg regnum = offset / sizeof(uint32_t); 115 assert(regnum < (AHCI_PORT_ADDR_OFFSET_LEN / sizeof(uint32_t))); 116 117 switch (regnum) { 118 case AHCI_PORT_REG_LST_ADDR: 119 val = pr->lst_addr; 120 break; 121 case AHCI_PORT_REG_LST_ADDR_HI: 122 val = pr->lst_addr_hi; 123 break; 124 case AHCI_PORT_REG_FIS_ADDR: 125 val = pr->fis_addr; 126 break; 127 case AHCI_PORT_REG_FIS_ADDR_HI: 128 val = pr->fis_addr_hi; 129 break; 130 case AHCI_PORT_REG_IRQ_STAT: 131 val = pr->irq_stat; 132 break; 133 case AHCI_PORT_REG_IRQ_MASK: 134 val = pr->irq_mask; 135 break; 136 case AHCI_PORT_REG_CMD: 137 val = pr->cmd; 138 break; 139 case AHCI_PORT_REG_TFDATA: 140 val = pr->tfdata; 141 break; 142 case AHCI_PORT_REG_SIG: 143 val = pr->sig; 144 break; 145 case AHCI_PORT_REG_SCR_STAT: 146 if (s->dev[port].port.ifs[0].blk) { 147 val = SATA_SCR_SSTATUS_DET_DEV_PRESENT_PHY_UP | 148 SATA_SCR_SSTATUS_SPD_GEN1 | SATA_SCR_SSTATUS_IPM_ACTIVE; 149 } else { 150 val = SATA_SCR_SSTATUS_DET_NODEV; 151 } 152 break; 153 case AHCI_PORT_REG_SCR_CTL: 154 val = pr->scr_ctl; 155 break; 156 case AHCI_PORT_REG_SCR_ERR: 157 val = pr->scr_err; 158 break; 159 case AHCI_PORT_REG_SCR_ACT: 160 val = pr->scr_act; 161 break; 162 case AHCI_PORT_REG_CMD_ISSUE: 163 val = pr->cmd_issue; 164 break; 165 default: 166 trace_ahci_port_read_default(s, port, AHCIPortReg_lookup[regnum], 167 offset); 168 val = 0; 169 } 170 171 trace_ahci_port_read(s, port, AHCIPortReg_lookup[regnum], offset, val); 172 return val; 173 } 174 175 static void ahci_check_irq(AHCIState *s) 176 { 177 int i; 178 uint32_t old_irq = s->control_regs.irqstatus; 179 180 s->control_regs.irqstatus = 0; 181 for (i = 0; i < s->ports; i++) { 182 AHCIPortRegs *pr = &s->dev[i].port_regs; 183 if (pr->irq_stat & pr->irq_mask) { 184 s->control_regs.irqstatus |= (1 << i); 185 } 186 } 187 trace_ahci_check_irq(s, old_irq, s->control_regs.irqstatus); 188 if (s->control_regs.irqstatus && 189 (s->control_regs.ghc & HOST_CTL_IRQ_EN)) { 190 trace_ahci_irq_raise(s); 191 qemu_irq_raise(s->irq); 192 } else { 193 trace_ahci_irq_lower(s); 194 qemu_irq_lower(s->irq); 195 } 196 } 197 198 static void ahci_trigger_irq(AHCIState *s, AHCIDevice *d, 199 enum AHCIPortIRQ irqbit) 200 { 201 g_assert((unsigned)irqbit < 32); 202 uint32_t irq = 1U << irqbit; 203 uint32_t irqstat = d->port_regs.irq_stat | irq; 204 205 trace_ahci_trigger_irq(s, d->port_no, 206 AHCIPortIRQ_lookup[irqbit], irq, 207 d->port_regs.irq_stat, irqstat, 208 irqstat & d->port_regs.irq_mask); 209 210 d->port_regs.irq_stat = irqstat; 211 ahci_check_irq(s); 212 } 213 214 static void map_page(AddressSpace *as, uint8_t **ptr, uint64_t addr, 215 uint32_t wanted) 216 { 217 hwaddr len = wanted; 218 219 if (*ptr) { 220 dma_memory_unmap(as, *ptr, len, DMA_DIRECTION_FROM_DEVICE, len); 221 } 222 223 *ptr = dma_memory_map(as, addr, &len, DMA_DIRECTION_FROM_DEVICE, 224 MEMTXATTRS_UNSPECIFIED); 225 if (len < wanted && *ptr) { 226 dma_memory_unmap(as, *ptr, len, DMA_DIRECTION_FROM_DEVICE, len); 227 *ptr = NULL; 228 } 229 } 230 231 /** 232 * Check the cmd register to see if we should start or stop 233 * the DMA or FIS RX engines. 234 * 235 * @ad: Device to dis/engage. 236 * 237 * @return 0 on success, -1 on error. 238 */ 239 static int ahci_cond_start_engines(AHCIDevice *ad) 240 { 241 AHCIPortRegs *pr = &ad->port_regs; 242 bool cmd_start = pr->cmd & PORT_CMD_START; 243 bool cmd_on = pr->cmd & PORT_CMD_LIST_ON; 244 bool fis_start = pr->cmd & PORT_CMD_FIS_RX; 245 bool fis_on = pr->cmd & PORT_CMD_FIS_ON; 246 247 if (cmd_start && !cmd_on) { 248 if (!ahci_map_clb_address(ad)) { 249 pr->cmd &= ~PORT_CMD_START; 250 error_report("AHCI: Failed to start DMA engine: " 251 "bad command list buffer address"); 252 return -1; 253 } 254 } else if (!cmd_start && cmd_on) { 255 ahci_unmap_clb_address(ad); 256 } 257 258 if (fis_start && !fis_on) { 259 if (!ahci_map_fis_address(ad)) { 260 pr->cmd &= ~PORT_CMD_FIS_RX; 261 error_report("AHCI: Failed to start FIS receive engine: " 262 "bad FIS receive buffer address"); 263 return -1; 264 } 265 } else if (!fis_start && fis_on) { 266 ahci_unmap_fis_address(ad); 267 } 268 269 return 0; 270 } 271 272 static void ahci_port_write(AHCIState *s, int port, int offset, uint32_t val) 273 { 274 AHCIPortRegs *pr = &s->dev[port].port_regs; 275 enum AHCIPortReg regnum = offset / sizeof(uint32_t); 276 assert(regnum < (AHCI_PORT_ADDR_OFFSET_LEN / sizeof(uint32_t))); 277 trace_ahci_port_write(s, port, AHCIPortReg_lookup[regnum], offset, val); 278 279 switch (regnum) { 280 case AHCI_PORT_REG_LST_ADDR: 281 pr->lst_addr = val; 282 break; 283 case AHCI_PORT_REG_LST_ADDR_HI: 284 pr->lst_addr_hi = val; 285 break; 286 case AHCI_PORT_REG_FIS_ADDR: 287 pr->fis_addr = val; 288 break; 289 case AHCI_PORT_REG_FIS_ADDR_HI: 290 pr->fis_addr_hi = val; 291 break; 292 case AHCI_PORT_REG_IRQ_STAT: 293 pr->irq_stat &= ~val; 294 ahci_check_irq(s); 295 break; 296 case AHCI_PORT_REG_IRQ_MASK: 297 pr->irq_mask = val & 0xfdc000ff; 298 ahci_check_irq(s); 299 break; 300 case AHCI_PORT_REG_CMD: 301 if ((pr->cmd & PORT_CMD_START) && !(val & PORT_CMD_START)) { 302 pr->scr_act = 0; 303 pr->cmd_issue = 0; 304 } 305 306 /* Block any Read-only fields from being set; 307 * including LIST_ON and FIS_ON. 308 * The spec requires to set ICC bits to zero after the ICC change 309 * is done. We don't support ICC state changes, therefore always 310 * force the ICC bits to zero. 311 */ 312 pr->cmd = (pr->cmd & PORT_CMD_RO_MASK) | 313 (val & ~(PORT_CMD_RO_MASK | PORT_CMD_ICC_MASK)); 314 315 /* Check FIS RX and CLB engines */ 316 ahci_cond_start_engines(&s->dev[port]); 317 318 /* XXX usually the FIS would be pending on the bus here and 319 issuing deferred until the OS enables FIS receival. 320 Instead, we only submit it once - which works in most 321 cases, but is a hack. */ 322 if ((pr->cmd & PORT_CMD_FIS_ON) && 323 !s->dev[port].init_d2h_sent) { 324 ahci_init_d2h(&s->dev[port]); 325 } 326 327 check_cmd(s, port); 328 break; 329 case AHCI_PORT_REG_TFDATA: 330 case AHCI_PORT_REG_SIG: 331 case AHCI_PORT_REG_SCR_STAT: 332 /* Read Only */ 333 break; 334 case AHCI_PORT_REG_SCR_CTL: 335 if (((pr->scr_ctl & AHCI_SCR_SCTL_DET) == 1) && 336 ((val & AHCI_SCR_SCTL_DET) == 0)) { 337 ahci_reset_port(s, port); 338 } 339 pr->scr_ctl = val; 340 break; 341 case AHCI_PORT_REG_SCR_ERR: 342 pr->scr_err &= ~val; 343 break; 344 case AHCI_PORT_REG_SCR_ACT: 345 /* RW1 */ 346 pr->scr_act |= val; 347 break; 348 case AHCI_PORT_REG_CMD_ISSUE: 349 pr->cmd_issue |= val; 350 check_cmd(s, port); 351 break; 352 default: 353 trace_ahci_port_write_unimpl(s, port, AHCIPortReg_lookup[regnum], 354 offset, val); 355 qemu_log_mask(LOG_UNIMP, "Attempted write to unimplemented register: " 356 "AHCI port %d register %s, offset 0x%x: 0x%"PRIx32, 357 port, AHCIPortReg_lookup[regnum], offset, val); 358 break; 359 } 360 } 361 362 static uint64_t ahci_mem_read_32(void *opaque, hwaddr addr) 363 { 364 AHCIState *s = opaque; 365 uint32_t val = 0; 366 367 if (addr < AHCI_GENERIC_HOST_CONTROL_REGS_MAX_ADDR) { 368 enum AHCIHostReg regnum = addr / 4; 369 assert(regnum < AHCI_HOST_REG__COUNT); 370 371 switch (regnum) { 372 case AHCI_HOST_REG_CAP: 373 val = s->control_regs.cap; 374 break; 375 case AHCI_HOST_REG_CTL: 376 val = s->control_regs.ghc; 377 break; 378 case AHCI_HOST_REG_IRQ_STAT: 379 val = s->control_regs.irqstatus; 380 break; 381 case AHCI_HOST_REG_PORTS_IMPL: 382 val = s->control_regs.impl; 383 break; 384 case AHCI_HOST_REG_VERSION: 385 val = s->control_regs.version; 386 break; 387 default: 388 trace_ahci_mem_read_32_host_default(s, AHCIHostReg_lookup[regnum], 389 addr); 390 } 391 trace_ahci_mem_read_32_host(s, AHCIHostReg_lookup[regnum], addr, val); 392 } else if ((addr >= AHCI_PORT_REGS_START_ADDR) && 393 (addr < (AHCI_PORT_REGS_START_ADDR + 394 (s->ports * AHCI_PORT_ADDR_OFFSET_LEN)))) { 395 val = ahci_port_read(s, (addr - AHCI_PORT_REGS_START_ADDR) >> 7, 396 addr & AHCI_PORT_ADDR_OFFSET_MASK); 397 } else { 398 trace_ahci_mem_read_32_default(s, addr, val); 399 } 400 401 trace_ahci_mem_read_32(s, addr, val); 402 return val; 403 } 404 405 406 /** 407 * AHCI 1.3 section 3 ("HBA Memory Registers") 408 * Support unaligned 8/16/32 bit reads, and 64 bit aligned reads. 409 * Caller is responsible for masking unwanted higher order bytes. 410 */ 411 static uint64_t ahci_mem_read(void *opaque, hwaddr addr, unsigned size) 412 { 413 hwaddr aligned = addr & ~0x3; 414 int ofst = addr - aligned; 415 uint64_t lo = ahci_mem_read_32(opaque, aligned); 416 uint64_t hi; 417 uint64_t val; 418 419 /* if < 8 byte read does not cross 4 byte boundary */ 420 if (ofst + size <= 4) { 421 val = lo >> (ofst * 8); 422 } else { 423 g_assert(size > 1); 424 425 /* If the 64bit read is unaligned, we will produce undefined 426 * results. AHCI does not support unaligned 64bit reads. */ 427 hi = ahci_mem_read_32(opaque, aligned + 4); 428 val = (hi << 32 | lo) >> (ofst * 8); 429 } 430 431 trace_ahci_mem_read(opaque, size, addr, val); 432 return val; 433 } 434 435 436 static void ahci_mem_write(void *opaque, hwaddr addr, 437 uint64_t val, unsigned size) 438 { 439 AHCIState *s = opaque; 440 441 trace_ahci_mem_write(s, size, addr, val); 442 443 /* Only aligned reads are allowed on AHCI */ 444 if (addr & 3) { 445 qemu_log_mask(LOG_GUEST_ERROR, 446 "ahci: Mis-aligned write to addr 0x%03" HWADDR_PRIX "\n", 447 addr); 448 return; 449 } 450 451 if (addr < AHCI_GENERIC_HOST_CONTROL_REGS_MAX_ADDR) { 452 enum AHCIHostReg regnum = addr / 4; 453 assert(regnum < AHCI_HOST_REG__COUNT); 454 455 switch (regnum) { 456 case AHCI_HOST_REG_CAP: /* R/WO, RO */ 457 /* FIXME handle R/WO */ 458 break; 459 case AHCI_HOST_REG_CTL: /* R/W */ 460 if (val & HOST_CTL_RESET) { 461 ahci_reset(s); 462 } else { 463 s->control_regs.ghc = (val & 0x3) | HOST_CTL_AHCI_EN; 464 ahci_check_irq(s); 465 } 466 break; 467 case AHCI_HOST_REG_IRQ_STAT: /* R/WC, RO */ 468 s->control_regs.irqstatus &= ~val; 469 ahci_check_irq(s); 470 break; 471 case AHCI_HOST_REG_PORTS_IMPL: /* R/WO, RO */ 472 /* FIXME handle R/WO */ 473 break; 474 case AHCI_HOST_REG_VERSION: /* RO */ 475 /* FIXME report write? */ 476 break; 477 default: 478 qemu_log_mask(LOG_UNIMP, 479 "Attempted write to unimplemented register: " 480 "AHCI host register %s, " 481 "offset 0x%"PRIx64": 0x%"PRIx64, 482 AHCIHostReg_lookup[regnum], addr, val); 483 trace_ahci_mem_write_host_unimpl(s, size, 484 AHCIHostReg_lookup[regnum], addr); 485 } 486 trace_ahci_mem_write_host(s, size, AHCIHostReg_lookup[regnum], 487 addr, val); 488 } else if ((addr >= AHCI_PORT_REGS_START_ADDR) && 489 (addr < (AHCI_PORT_REGS_START_ADDR + 490 (s->ports * AHCI_PORT_ADDR_OFFSET_LEN)))) { 491 ahci_port_write(s, (addr - AHCI_PORT_REGS_START_ADDR) >> 7, 492 addr & AHCI_PORT_ADDR_OFFSET_MASK, val); 493 } else { 494 qemu_log_mask(LOG_UNIMP, "Attempted write to unimplemented register: " 495 "AHCI global register at offset 0x%"PRIx64": 0x%"PRIx64, 496 addr, val); 497 trace_ahci_mem_write_unimpl(s, size, addr, val); 498 } 499 } 500 501 static const MemoryRegionOps ahci_mem_ops = { 502 .read = ahci_mem_read, 503 .write = ahci_mem_write, 504 .endianness = DEVICE_LITTLE_ENDIAN, 505 }; 506 507 static uint64_t ahci_idp_read(void *opaque, hwaddr addr, 508 unsigned size) 509 { 510 AHCIState *s = opaque; 511 512 if (addr == s->idp_offset) { 513 /* index register */ 514 return s->idp_index; 515 } else if (addr == s->idp_offset + 4) { 516 /* data register - do memory read at location selected by index */ 517 return ahci_mem_read(opaque, s->idp_index, size); 518 } else { 519 return 0; 520 } 521 } 522 523 static void ahci_idp_write(void *opaque, hwaddr addr, 524 uint64_t val, unsigned size) 525 { 526 AHCIState *s = opaque; 527 528 if (addr == s->idp_offset) { 529 /* index register - mask off reserved bits */ 530 s->idp_index = (uint32_t)val & ((AHCI_MEM_BAR_SIZE - 1) & ~3); 531 } else if (addr == s->idp_offset + 4) { 532 /* data register - do memory write at location selected by index */ 533 ahci_mem_write(opaque, s->idp_index, val, size); 534 } 535 } 536 537 static const MemoryRegionOps ahci_idp_ops = { 538 .read = ahci_idp_read, 539 .write = ahci_idp_write, 540 .endianness = DEVICE_LITTLE_ENDIAN, 541 }; 542 543 544 static void ahci_reg_init(AHCIState *s) 545 { 546 int i; 547 548 s->control_regs.cap = (s->ports - 1) | 549 (AHCI_NUM_COMMAND_SLOTS << 8) | 550 (AHCI_SUPPORTED_SPEED_GEN1 << AHCI_SUPPORTED_SPEED) | 551 HOST_CAP_NCQ | HOST_CAP_AHCI | HOST_CAP_64; 552 553 s->control_regs.impl = (1 << s->ports) - 1; 554 555 s->control_regs.version = AHCI_VERSION_1_0; 556 557 for (i = 0; i < s->ports; i++) { 558 s->dev[i].port_state = STATE_RUN; 559 } 560 } 561 562 static void check_cmd(AHCIState *s, int port) 563 { 564 AHCIPortRegs *pr = &s->dev[port].port_regs; 565 uint8_t slot; 566 567 if ((pr->cmd & PORT_CMD_START) && pr->cmd_issue) { 568 for (slot = 0; (slot < 32) && pr->cmd_issue; slot++) { 569 if (pr->cmd_issue & (1U << slot)) { 570 handle_cmd(s, port, slot); 571 } 572 } 573 } 574 } 575 576 static void ahci_check_cmd_bh(void *opaque) 577 { 578 AHCIDevice *ad = opaque; 579 580 qemu_bh_delete(ad->check_bh); 581 ad->check_bh = NULL; 582 583 check_cmd(ad->hba, ad->port_no); 584 } 585 586 static void ahci_init_d2h(AHCIDevice *ad) 587 { 588 IDEState *ide_state = &ad->port.ifs[0]; 589 AHCIPortRegs *pr = &ad->port_regs; 590 591 if (ad->init_d2h_sent) { 592 return; 593 } 594 595 /* 596 * For simplicity, do not call ahci_clear_cmd_issue() for this 597 * ahci_write_fis_d2h(). (The reset value for PxCI is 0.) 598 */ 599 if (ahci_write_fis_d2h(ad, true)) { 600 ad->init_d2h_sent = true; 601 /* We're emulating receiving the first Reg D2H FIS from the device; 602 * Update the SIG register, but otherwise proceed as normal. */ 603 pr->sig = ((uint32_t)ide_state->hcyl << 24) | 604 (ide_state->lcyl << 16) | 605 (ide_state->sector << 8) | 606 (ide_state->nsector & 0xFF); 607 } 608 } 609 610 static void ahci_set_signature(AHCIDevice *ad, uint32_t sig) 611 { 612 IDEState *s = &ad->port.ifs[0]; 613 s->hcyl = sig >> 24 & 0xFF; 614 s->lcyl = sig >> 16 & 0xFF; 615 s->sector = sig >> 8 & 0xFF; 616 s->nsector = sig & 0xFF; 617 618 trace_ahci_set_signature(ad->hba, ad->port_no, s->nsector, s->sector, 619 s->lcyl, s->hcyl, sig); 620 } 621 622 static void ahci_reset_port(AHCIState *s, int port) 623 { 624 AHCIDevice *d = &s->dev[port]; 625 AHCIPortRegs *pr = &d->port_regs; 626 IDEState *ide_state = &d->port.ifs[0]; 627 int i; 628 629 trace_ahci_reset_port(s, port); 630 631 ide_bus_reset(&d->port); 632 ide_state->ncq_queues = AHCI_MAX_CMDS; 633 634 pr->scr_stat = 0; 635 pr->scr_err = 0; 636 pr->scr_act = 0; 637 pr->tfdata = 0x7F; 638 pr->sig = 0xFFFFFFFF; 639 pr->cmd_issue = 0; 640 d->busy_slot = -1; 641 d->init_d2h_sent = false; 642 643 ide_state = &s->dev[port].port.ifs[0]; 644 if (!ide_state->blk) { 645 return; 646 } 647 648 /* reset ncq queue */ 649 for (i = 0; i < AHCI_MAX_CMDS; i++) { 650 NCQTransferState *ncq_tfs = &s->dev[port].ncq_tfs[i]; 651 ncq_tfs->halt = false; 652 if (!ncq_tfs->used) { 653 continue; 654 } 655 656 if (ncq_tfs->aiocb) { 657 blk_aio_cancel(ncq_tfs->aiocb); 658 ncq_tfs->aiocb = NULL; 659 } 660 661 /* Maybe we just finished the request thanks to blk_aio_cancel() */ 662 if (!ncq_tfs->used) { 663 continue; 664 } 665 666 qemu_sglist_destroy(&ncq_tfs->sglist); 667 ncq_tfs->used = 0; 668 } 669 670 s->dev[port].port_state = STATE_RUN; 671 if (ide_state->drive_kind == IDE_CD) { 672 ahci_set_signature(d, SATA_SIGNATURE_CDROM); 673 ide_state->status = SEEK_STAT | WRERR_STAT | READY_STAT; 674 } else { 675 ahci_set_signature(d, SATA_SIGNATURE_DISK); 676 ide_state->status = SEEK_STAT | WRERR_STAT; 677 } 678 679 ide_state->error = 1; 680 ahci_init_d2h(d); 681 } 682 683 /* Buffer pretty output based on a raw FIS structure. */ 684 static char *ahci_pretty_buffer_fis(const uint8_t *fis, int cmd_len) 685 { 686 int i; 687 GString *s = g_string_new("FIS:"); 688 689 for (i = 0; i < cmd_len; i++) { 690 if ((i & 0xf) == 0) { 691 g_string_append_printf(s, "\n0x%02x: ", i); 692 } 693 g_string_append_printf(s, "%02x ", fis[i]); 694 } 695 g_string_append_c(s, '\n'); 696 697 return g_string_free(s, FALSE); 698 } 699 700 static bool ahci_map_fis_address(AHCIDevice *ad) 701 { 702 AHCIPortRegs *pr = &ad->port_regs; 703 map_page(ad->hba->as, &ad->res_fis, 704 ((uint64_t)pr->fis_addr_hi << 32) | pr->fis_addr, 256); 705 if (ad->res_fis != NULL) { 706 pr->cmd |= PORT_CMD_FIS_ON; 707 return true; 708 } 709 710 pr->cmd &= ~PORT_CMD_FIS_ON; 711 return false; 712 } 713 714 static void ahci_unmap_fis_address(AHCIDevice *ad) 715 { 716 if (ad->res_fis == NULL) { 717 trace_ahci_unmap_fis_address_null(ad->hba, ad->port_no); 718 return; 719 } 720 ad->port_regs.cmd &= ~PORT_CMD_FIS_ON; 721 dma_memory_unmap(ad->hba->as, ad->res_fis, 256, 722 DMA_DIRECTION_FROM_DEVICE, 256); 723 ad->res_fis = NULL; 724 } 725 726 static bool ahci_map_clb_address(AHCIDevice *ad) 727 { 728 AHCIPortRegs *pr = &ad->port_regs; 729 ad->cur_cmd = NULL; 730 map_page(ad->hba->as, &ad->lst, 731 ((uint64_t)pr->lst_addr_hi << 32) | pr->lst_addr, 1024); 732 if (ad->lst != NULL) { 733 pr->cmd |= PORT_CMD_LIST_ON; 734 return true; 735 } 736 737 pr->cmd &= ~PORT_CMD_LIST_ON; 738 return false; 739 } 740 741 static void ahci_unmap_clb_address(AHCIDevice *ad) 742 { 743 if (ad->lst == NULL) { 744 trace_ahci_unmap_clb_address_null(ad->hba, ad->port_no); 745 return; 746 } 747 ad->port_regs.cmd &= ~PORT_CMD_LIST_ON; 748 dma_memory_unmap(ad->hba->as, ad->lst, 1024, 749 DMA_DIRECTION_FROM_DEVICE, 1024); 750 ad->lst = NULL; 751 } 752 753 static void ahci_write_fis_sdb(AHCIState *s, NCQTransferState *ncq_tfs) 754 { 755 AHCIDevice *ad = ncq_tfs->drive; 756 AHCIPortRegs *pr = &ad->port_regs; 757 IDEState *ide_state; 758 SDBFIS *sdb_fis; 759 760 if (!ad->res_fis || 761 !(pr->cmd & PORT_CMD_FIS_RX)) { 762 return; 763 } 764 765 sdb_fis = (SDBFIS *)&ad->res_fis[RES_FIS_SDBFIS]; 766 ide_state = &ad->port.ifs[0]; 767 768 sdb_fis->type = SATA_FIS_TYPE_SDB; 769 /* Interrupt pending & Notification bit */ 770 sdb_fis->flags = 0x40; /* Interrupt bit, always 1 for NCQ */ 771 sdb_fis->status = ide_state->status & 0x77; 772 sdb_fis->error = ide_state->error; 773 /* update SAct field in SDB_FIS */ 774 sdb_fis->payload = cpu_to_le32(ad->finished); 775 776 /* Update shadow registers (except BSY 0x80 and DRQ 0x08) */ 777 pr->tfdata = (ad->port.ifs[0].error << 8) | 778 (ad->port.ifs[0].status & 0x77) | 779 (pr->tfdata & 0x88); 780 pr->scr_act &= ~ad->finished; 781 ad->finished = 0; 782 783 /* 784 * TFES IRQ is always raised if ERR_STAT is set, regardless of I bit. 785 * If ERR_STAT is not set, trigger SDBS IRQ if interrupt bit is set 786 * (which currently, it always is). 787 */ 788 if (sdb_fis->status & ERR_STAT) { 789 ahci_trigger_irq(s, ad, AHCI_PORT_IRQ_BIT_TFES); 790 } else if (sdb_fis->flags & 0x40) { 791 ahci_trigger_irq(s, ad, AHCI_PORT_IRQ_BIT_SDBS); 792 } 793 } 794 795 static void ahci_write_fis_pio(AHCIDevice *ad, uint16_t len, bool pio_fis_i) 796 { 797 AHCIPortRegs *pr = &ad->port_regs; 798 uint8_t *pio_fis; 799 IDEState *s = &ad->port.ifs[0]; 800 801 if (!ad->res_fis || !(pr->cmd & PORT_CMD_FIS_RX)) { 802 return; 803 } 804 805 pio_fis = &ad->res_fis[RES_FIS_PSFIS]; 806 807 pio_fis[0] = SATA_FIS_TYPE_PIO_SETUP; 808 pio_fis[1] = (pio_fis_i ? (1 << 6) : 0); 809 pio_fis[2] = s->status; 810 pio_fis[3] = s->error; 811 812 pio_fis[4] = s->sector; 813 pio_fis[5] = s->lcyl; 814 pio_fis[6] = s->hcyl; 815 pio_fis[7] = s->select; 816 pio_fis[8] = s->hob_sector; 817 pio_fis[9] = s->hob_lcyl; 818 pio_fis[10] = s->hob_hcyl; 819 pio_fis[11] = 0; 820 pio_fis[12] = s->nsector & 0xFF; 821 pio_fis[13] = (s->nsector >> 8) & 0xFF; 822 pio_fis[14] = 0; 823 pio_fis[15] = s->status; 824 pio_fis[16] = len & 255; 825 pio_fis[17] = len >> 8; 826 pio_fis[18] = 0; 827 pio_fis[19] = 0; 828 829 /* Update shadow registers: */ 830 pr->tfdata = (ad->port.ifs[0].error << 8) | 831 ad->port.ifs[0].status; 832 833 if (pio_fis[2] & ERR_STAT) { 834 ahci_trigger_irq(ad->hba, ad, AHCI_PORT_IRQ_BIT_TFES); 835 } 836 } 837 838 static bool ahci_write_fis_d2h(AHCIDevice *ad, bool d2h_fis_i) 839 { 840 AHCIPortRegs *pr = &ad->port_regs; 841 uint8_t *d2h_fis; 842 int i; 843 IDEState *s = &ad->port.ifs[0]; 844 845 if (!ad->res_fis || !(pr->cmd & PORT_CMD_FIS_RX)) { 846 return false; 847 } 848 849 d2h_fis = &ad->res_fis[RES_FIS_RFIS]; 850 851 d2h_fis[0] = SATA_FIS_TYPE_REGISTER_D2H; 852 d2h_fis[1] = d2h_fis_i ? (1 << 6) : 0; /* interrupt bit */ 853 d2h_fis[2] = s->status; 854 d2h_fis[3] = s->error; 855 856 d2h_fis[4] = s->sector; 857 d2h_fis[5] = s->lcyl; 858 d2h_fis[6] = s->hcyl; 859 d2h_fis[7] = s->select; 860 d2h_fis[8] = s->hob_sector; 861 d2h_fis[9] = s->hob_lcyl; 862 d2h_fis[10] = s->hob_hcyl; 863 d2h_fis[11] = 0; 864 d2h_fis[12] = s->nsector & 0xFF; 865 d2h_fis[13] = (s->nsector >> 8) & 0xFF; 866 for (i = 14; i < 20; i++) { 867 d2h_fis[i] = 0; 868 } 869 870 /* Update shadow registers: */ 871 pr->tfdata = (ad->port.ifs[0].error << 8) | 872 ad->port.ifs[0].status; 873 874 /* TFES IRQ is always raised if ERR_STAT is set, regardless of I bit. */ 875 if (d2h_fis[2] & ERR_STAT) { 876 ahci_trigger_irq(ad->hba, ad, AHCI_PORT_IRQ_BIT_TFES); 877 } else if (d2h_fis_i) { 878 ahci_trigger_irq(ad->hba, ad, AHCI_PORT_IRQ_BIT_DHRS); 879 } 880 881 return true; 882 } 883 884 static int prdt_tbl_entry_size(const AHCI_SG *tbl) 885 { 886 /* flags_size is zero-based */ 887 return (le32_to_cpu(tbl->flags_size) & AHCI_PRDT_SIZE_MASK) + 1; 888 } 889 890 /** 891 * Fetch entries in a guest-provided PRDT and convert it into a QEMU SGlist. 892 * @ad: The AHCIDevice for whom we are building the SGList. 893 * @sglist: The SGList target to add PRD entries to. 894 * @cmd: The AHCI Command Header that describes where the PRDT is. 895 * @limit: The remaining size of the S/ATA transaction, in bytes. 896 * @offset: The number of bytes already transferred, in bytes. 897 * 898 * The AHCI PRDT can describe up to 256GiB. S/ATA only support transactions of 899 * up to 32MiB as of ATA8-ACS3 rev 1b, assuming a 512 byte sector size. We stop 900 * building the sglist from the PRDT as soon as we hit @limit bytes, 901 * which is <= INT32_MAX/2GiB. 902 */ 903 static int ahci_populate_sglist(AHCIDevice *ad, QEMUSGList *sglist, 904 AHCICmdHdr *cmd, int64_t limit, uint64_t offset) 905 { 906 uint16_t opts = le16_to_cpu(cmd->opts); 907 uint16_t prdtl = le16_to_cpu(cmd->prdtl); 908 uint64_t cfis_addr = le64_to_cpu(cmd->tbl_addr); 909 uint64_t prdt_addr = cfis_addr + 0x80; 910 dma_addr_t prdt_len = (prdtl * sizeof(AHCI_SG)); 911 dma_addr_t real_prdt_len = prdt_len; 912 uint8_t *prdt; 913 int i; 914 int r = 0; 915 uint64_t sum = 0; 916 int off_idx = -1; 917 int64_t off_pos = -1; 918 IDEBus *bus = &ad->port; 919 BusState *qbus = BUS(bus); 920 921 trace_ahci_populate_sglist(ad->hba, ad->port_no); 922 923 if (!prdtl) { 924 trace_ahci_populate_sglist_no_prdtl(ad->hba, ad->port_no, opts); 925 return -1; 926 } 927 928 /* map PRDT */ 929 if (!(prdt = dma_memory_map(ad->hba->as, prdt_addr, &prdt_len, 930 DMA_DIRECTION_TO_DEVICE, 931 MEMTXATTRS_UNSPECIFIED))){ 932 trace_ahci_populate_sglist_no_map(ad->hba, ad->port_no); 933 return -1; 934 } 935 936 if (prdt_len < real_prdt_len) { 937 trace_ahci_populate_sglist_short_map(ad->hba, ad->port_no); 938 r = -1; 939 goto out; 940 } 941 942 /* Get entries in the PRDT, init a qemu sglist accordingly */ 943 if (prdtl > 0) { 944 AHCI_SG *tbl = (AHCI_SG *)prdt; 945 int tbl_entry_size = 0; 946 947 sum = 0; 948 for (i = 0; i < prdtl; i++) { 949 tbl_entry_size = prdt_tbl_entry_size(&tbl[i]); 950 if (offset < (sum + tbl_entry_size)) { 951 off_idx = i; 952 off_pos = offset - sum; 953 break; 954 } 955 sum += tbl_entry_size; 956 } 957 if ((off_idx == -1) || (off_pos < 0) || (off_pos > tbl_entry_size)) { 958 trace_ahci_populate_sglist_bad_offset(ad->hba, ad->port_no, 959 off_idx, off_pos); 960 r = -1; 961 goto out; 962 } 963 964 qemu_sglist_init(sglist, qbus->parent, (prdtl - off_idx), 965 ad->hba->as); 966 qemu_sglist_add(sglist, le64_to_cpu(tbl[off_idx].addr) + off_pos, 967 MIN(prdt_tbl_entry_size(&tbl[off_idx]) - off_pos, 968 limit)); 969 970 for (i = off_idx + 1; i < prdtl && sglist->size < limit; i++) { 971 qemu_sglist_add(sglist, le64_to_cpu(tbl[i].addr), 972 MIN(prdt_tbl_entry_size(&tbl[i]), 973 limit - sglist->size)); 974 } 975 } 976 977 out: 978 dma_memory_unmap(ad->hba->as, prdt, prdt_len, 979 DMA_DIRECTION_TO_DEVICE, prdt_len); 980 return r; 981 } 982 983 static void ncq_err(NCQTransferState *ncq_tfs) 984 { 985 IDEState *ide_state = &ncq_tfs->drive->port.ifs[0]; 986 987 ide_state->error = ABRT_ERR; 988 ide_state->status = READY_STAT | ERR_STAT; 989 qemu_sglist_destroy(&ncq_tfs->sglist); 990 ncq_tfs->used = 0; 991 } 992 993 static void ncq_finish(NCQTransferState *ncq_tfs) 994 { 995 /* If we didn't error out, set our finished bit. Errored commands 996 * do not get a bit set for the SDB FIS ACT register, nor do they 997 * clear the outstanding bit in scr_act (PxSACT). */ 998 if (ncq_tfs->used) { 999 ncq_tfs->drive->finished |= (1 << ncq_tfs->tag); 1000 } 1001 1002 ahci_write_fis_sdb(ncq_tfs->drive->hba, ncq_tfs); 1003 1004 trace_ncq_finish(ncq_tfs->drive->hba, ncq_tfs->drive->port_no, 1005 ncq_tfs->tag); 1006 1007 block_acct_done(blk_get_stats(ncq_tfs->drive->port.ifs[0].blk), 1008 &ncq_tfs->acct); 1009 qemu_sglist_destroy(&ncq_tfs->sglist); 1010 ncq_tfs->used = 0; 1011 } 1012 1013 static void ncq_cb(void *opaque, int ret) 1014 { 1015 NCQTransferState *ncq_tfs = (NCQTransferState *)opaque; 1016 IDEState *ide_state = &ncq_tfs->drive->port.ifs[0]; 1017 1018 ncq_tfs->aiocb = NULL; 1019 1020 if (ret < 0) { 1021 bool is_read = ncq_tfs->cmd == READ_FPDMA_QUEUED; 1022 BlockErrorAction action = blk_get_error_action(ide_state->blk, 1023 is_read, -ret); 1024 if (action == BLOCK_ERROR_ACTION_STOP) { 1025 ncq_tfs->halt = true; 1026 ide_state->bus->error_status = IDE_RETRY_HBA; 1027 } else if (action == BLOCK_ERROR_ACTION_REPORT) { 1028 ncq_err(ncq_tfs); 1029 } 1030 blk_error_action(ide_state->blk, action, is_read, -ret); 1031 } else { 1032 ide_state->status = READY_STAT | SEEK_STAT; 1033 } 1034 1035 if (!ncq_tfs->halt) { 1036 ncq_finish(ncq_tfs); 1037 } 1038 } 1039 1040 static int is_ncq(uint8_t ata_cmd) 1041 { 1042 /* Based on SATA 3.2 section 13.6.3.2 */ 1043 switch (ata_cmd) { 1044 case READ_FPDMA_QUEUED: 1045 case WRITE_FPDMA_QUEUED: 1046 case NCQ_NON_DATA: 1047 case RECEIVE_FPDMA_QUEUED: 1048 case SEND_FPDMA_QUEUED: 1049 return 1; 1050 default: 1051 return 0; 1052 } 1053 } 1054 1055 static void execute_ncq_command(NCQTransferState *ncq_tfs) 1056 { 1057 AHCIDevice *ad = ncq_tfs->drive; 1058 IDEState *ide_state = &ad->port.ifs[0]; 1059 int port = ad->port_no; 1060 1061 g_assert(is_ncq(ncq_tfs->cmd)); 1062 ncq_tfs->halt = false; 1063 1064 switch (ncq_tfs->cmd) { 1065 case READ_FPDMA_QUEUED: 1066 trace_execute_ncq_command_read(ad->hba, port, ncq_tfs->tag, 1067 ncq_tfs->sector_count, ncq_tfs->lba); 1068 dma_acct_start(ide_state->blk, &ncq_tfs->acct, 1069 &ncq_tfs->sglist, BLOCK_ACCT_READ); 1070 ncq_tfs->aiocb = dma_blk_read(ide_state->blk, &ncq_tfs->sglist, 1071 ncq_tfs->lba << BDRV_SECTOR_BITS, 1072 BDRV_SECTOR_SIZE, 1073 ncq_cb, ncq_tfs); 1074 break; 1075 case WRITE_FPDMA_QUEUED: 1076 trace_execute_ncq_command_write(ad->hba, port, ncq_tfs->tag, 1077 ncq_tfs->sector_count, ncq_tfs->lba); 1078 dma_acct_start(ide_state->blk, &ncq_tfs->acct, 1079 &ncq_tfs->sglist, BLOCK_ACCT_WRITE); 1080 ncq_tfs->aiocb = dma_blk_write(ide_state->blk, &ncq_tfs->sglist, 1081 ncq_tfs->lba << BDRV_SECTOR_BITS, 1082 BDRV_SECTOR_SIZE, 1083 ncq_cb, ncq_tfs); 1084 break; 1085 default: 1086 trace_execute_ncq_command_unsup(ad->hba, port, 1087 ncq_tfs->tag, ncq_tfs->cmd); 1088 ncq_err(ncq_tfs); 1089 } 1090 } 1091 1092 1093 static void process_ncq_command(AHCIState *s, int port, const uint8_t *cmd_fis, 1094 uint8_t slot) 1095 { 1096 AHCIDevice *ad = &s->dev[port]; 1097 const NCQFrame *ncq_fis = (NCQFrame *)cmd_fis; 1098 uint8_t tag = ncq_fis->tag >> 3; 1099 NCQTransferState *ncq_tfs = &ad->ncq_tfs[tag]; 1100 size_t size; 1101 1102 g_assert(is_ncq(ncq_fis->command)); 1103 if (ncq_tfs->used) { 1104 /* error - already in use */ 1105 qemu_log_mask(LOG_GUEST_ERROR, "%s: tag %d already used\n", 1106 __func__, tag); 1107 return; 1108 } 1109 1110 /* 1111 * A NCQ command clears the bit in PxCI after the command has been QUEUED 1112 * successfully (ERROR not set, BUSY and DRQ cleared). 1113 * 1114 * For NCQ commands, PxCI will always be cleared here. 1115 * 1116 * (Once the NCQ command is COMPLETED, the device will send a SDB FIS with 1117 * the interrupt bit set, which will clear PxSACT and raise an interrupt.) 1118 */ 1119 ahci_clear_cmd_issue(ad, slot); 1120 1121 /* 1122 * In reality, for NCQ commands, PxCI is cleared after receiving a D2H FIS 1123 * without the interrupt bit set, but since ahci_write_fis_d2h() can raise 1124 * an IRQ on error, we need to call them in reverse order. 1125 */ 1126 ahci_write_fis_d2h(ad, false); 1127 1128 ncq_tfs->used = 1; 1129 ncq_tfs->drive = ad; 1130 ncq_tfs->slot = slot; 1131 ncq_tfs->cmdh = &((AHCICmdHdr *)ad->lst)[slot]; 1132 ncq_tfs->cmd = ncq_fis->command; 1133 ncq_tfs->lba = ((uint64_t)ncq_fis->lba5 << 40) | 1134 ((uint64_t)ncq_fis->lba4 << 32) | 1135 ((uint64_t)ncq_fis->lba3 << 24) | 1136 ((uint64_t)ncq_fis->lba2 << 16) | 1137 ((uint64_t)ncq_fis->lba1 << 8) | 1138 (uint64_t)ncq_fis->lba0; 1139 ncq_tfs->tag = tag; 1140 1141 /* Sanity-check the NCQ packet */ 1142 if (tag != slot) { 1143 trace_process_ncq_command_mismatch(s, port, tag, slot); 1144 } 1145 1146 if (ncq_fis->aux0 || ncq_fis->aux1 || ncq_fis->aux2 || ncq_fis->aux3) { 1147 trace_process_ncq_command_aux(s, port, tag); 1148 } 1149 if (ncq_fis->prio || ncq_fis->icc) { 1150 trace_process_ncq_command_prioicc(s, port, tag); 1151 } 1152 if (ncq_fis->fua & NCQ_FIS_FUA_MASK) { 1153 trace_process_ncq_command_fua(s, port, tag); 1154 } 1155 if (ncq_fis->tag & NCQ_FIS_RARC_MASK) { 1156 trace_process_ncq_command_rarc(s, port, tag); 1157 } 1158 1159 ncq_tfs->sector_count = ((ncq_fis->sector_count_high << 8) | 1160 ncq_fis->sector_count_low); 1161 if (!ncq_tfs->sector_count) { 1162 ncq_tfs->sector_count = 0x10000; 1163 } 1164 size = ncq_tfs->sector_count * BDRV_SECTOR_SIZE; 1165 ahci_populate_sglist(ad, &ncq_tfs->sglist, ncq_tfs->cmdh, size, 0); 1166 1167 if (ncq_tfs->sglist.size < size) { 1168 error_report("ahci: PRDT length for NCQ command (0x" DMA_ADDR_FMT ") " 1169 "is smaller than the requested size (0x%zx)", 1170 ncq_tfs->sglist.size, size); 1171 ncq_err(ncq_tfs); 1172 ahci_trigger_irq(ad->hba, ad, AHCI_PORT_IRQ_BIT_OFS); 1173 return; 1174 } else if (ncq_tfs->sglist.size != size) { 1175 trace_process_ncq_command_large(s, port, tag, 1176 ncq_tfs->sglist.size, size); 1177 } 1178 1179 trace_process_ncq_command(s, port, tag, 1180 ncq_fis->command, 1181 ncq_tfs->lba, 1182 ncq_tfs->lba + ncq_tfs->sector_count - 1); 1183 execute_ncq_command(ncq_tfs); 1184 } 1185 1186 static AHCICmdHdr *get_cmd_header(AHCIState *s, uint8_t port, uint8_t slot) 1187 { 1188 if (port >= s->ports || slot >= AHCI_MAX_CMDS) { 1189 return NULL; 1190 } 1191 1192 return s->dev[port].lst ? &((AHCICmdHdr *)s->dev[port].lst)[slot] : NULL; 1193 } 1194 1195 static void handle_reg_h2d_fis(AHCIState *s, int port, 1196 uint8_t slot, const uint8_t *cmd_fis) 1197 { 1198 IDEState *ide_state = &s->dev[port].port.ifs[0]; 1199 AHCICmdHdr *cmd = get_cmd_header(s, port, slot); 1200 AHCIDevice *ad = &s->dev[port]; 1201 uint16_t opts = le16_to_cpu(cmd->opts); 1202 1203 if (cmd_fis[1] & 0x0F) { 1204 trace_handle_reg_h2d_fis_pmp(s, port, cmd_fis[1], 1205 cmd_fis[2], cmd_fis[3]); 1206 return; 1207 } 1208 1209 if (cmd_fis[1] & 0x70) { 1210 trace_handle_reg_h2d_fis_res(s, port, cmd_fis[1], 1211 cmd_fis[2], cmd_fis[3]); 1212 return; 1213 } 1214 1215 if (!(cmd_fis[1] & SATA_FIS_REG_H2D_UPDATE_COMMAND_REGISTER)) { 1216 switch (s->dev[port].port_state) { 1217 case STATE_RUN: 1218 if (cmd_fis[15] & ATA_SRST) { 1219 s->dev[port].port_state = STATE_RESET; 1220 /* 1221 * When setting SRST in the first H2D FIS in the reset sequence, 1222 * the device does not send a D2H FIS. Host software thus has to 1223 * set the "Clear Busy upon R_OK" bit such that PxCI (and BUSY) 1224 * gets cleared. See AHCI 1.3.1, section 10.4.1 Software Reset. 1225 */ 1226 if (opts & AHCI_CMD_CLR_BUSY) { 1227 ahci_clear_cmd_issue(ad, slot); 1228 } 1229 } 1230 break; 1231 case STATE_RESET: 1232 if (!(cmd_fis[15] & ATA_SRST)) { 1233 /* 1234 * When clearing SRST in the second H2D FIS in the reset 1235 * sequence, the device will execute diagnostics. When this is 1236 * done, the device will send a D2H FIS with the good status. 1237 * See SATA 3.5a Gold, section 11.4 Software reset protocol. 1238 * 1239 * This D2H FIS is the first D2H FIS received from the device, 1240 * and is received regardless if the reset was performed by a 1241 * COMRESET or by setting and clearing the SRST bit. Therefore, 1242 * the logic for this is found in ahci_init_d2h() and not here. 1243 */ 1244 ahci_reset_port(s, port); 1245 } 1246 break; 1247 } 1248 return; 1249 } 1250 1251 /* Check for NCQ command */ 1252 if (is_ncq(cmd_fis[2])) { 1253 process_ncq_command(s, port, cmd_fis, slot); 1254 return; 1255 } 1256 1257 /* Decompose the FIS: 1258 * AHCI does not interpret FIS packets, it only forwards them. 1259 * SATA 1.0 describes how to decode LBA28 and CHS FIS packets. 1260 * Later specifications, e.g, SATA 3.2, describe LBA48 FIS packets. 1261 * 1262 * ATA4 describes sector number for LBA28/CHS commands. 1263 * ATA6 describes sector number for LBA48 commands. 1264 * ATA8 deprecates CHS fully, describing only LBA28/48. 1265 * 1266 * We dutifully convert the FIS into IDE registers, and allow the 1267 * core layer to interpret them as needed. */ 1268 ide_state->feature = cmd_fis[3]; 1269 ide_state->sector = cmd_fis[4]; /* LBA 7:0 */ 1270 ide_state->lcyl = cmd_fis[5]; /* LBA 15:8 */ 1271 ide_state->hcyl = cmd_fis[6]; /* LBA 23:16 */ 1272 ide_state->select = cmd_fis[7]; /* LBA 27:24 (LBA28) */ 1273 ide_state->hob_sector = cmd_fis[8]; /* LBA 31:24 */ 1274 ide_state->hob_lcyl = cmd_fis[9]; /* LBA 39:32 */ 1275 ide_state->hob_hcyl = cmd_fis[10]; /* LBA 47:40 */ 1276 ide_state->hob_feature = cmd_fis[11]; 1277 ide_state->nsector = (int64_t)((cmd_fis[13] << 8) | cmd_fis[12]); 1278 /* 14, 16, 17, 18, 19: Reserved (SATA 1.0) */ 1279 /* 15: Only valid when UPDATE_COMMAND not set. */ 1280 1281 /* Copy the ACMD field (ATAPI packet, if any) from the AHCI command 1282 * table to ide_state->io_buffer */ 1283 if (opts & AHCI_CMD_ATAPI) { 1284 memcpy(ide_state->io_buffer, &cmd_fis[AHCI_COMMAND_TABLE_ACMD], 0x10); 1285 if (trace_event_get_state_backends(TRACE_HANDLE_REG_H2D_FIS_DUMP)) { 1286 char *pretty_fis = ahci_pretty_buffer_fis(ide_state->io_buffer, 0x10); 1287 trace_handle_reg_h2d_fis_dump(s, port, pretty_fis); 1288 g_free(pretty_fis); 1289 } 1290 } 1291 1292 ide_state->error = 0; 1293 s->dev[port].done_first_drq = false; 1294 /* Reset transferred byte counter */ 1295 cmd->status = 0; 1296 1297 /* 1298 * A non-NCQ command clears the bit in PxCI after the command has COMPLETED 1299 * successfully (ERROR not set, BUSY and DRQ cleared). 1300 * 1301 * For non-NCQ commands, PxCI will always be cleared by ahci_cmd_done(). 1302 */ 1303 ad->busy_slot = slot; 1304 1305 /* We're ready to process the command in FIS byte 2. */ 1306 ide_bus_exec_cmd(&s->dev[port].port, cmd_fis[2]); 1307 } 1308 1309 static void handle_cmd(AHCIState *s, int port, uint8_t slot) 1310 { 1311 IDEState *ide_state; 1312 uint64_t tbl_addr; 1313 AHCICmdHdr *cmd; 1314 uint8_t *cmd_fis; 1315 dma_addr_t cmd_len; 1316 1317 if (s->dev[port].port.ifs[0].status & (BUSY_STAT|DRQ_STAT)) { 1318 /* Engine currently busy, try again later */ 1319 trace_handle_cmd_busy(s, port); 1320 return; 1321 } 1322 1323 if (!s->dev[port].lst) { 1324 trace_handle_cmd_nolist(s, port); 1325 return; 1326 } 1327 cmd = get_cmd_header(s, port, slot); 1328 /* remember current slot handle for later */ 1329 s->dev[port].cur_cmd = cmd; 1330 1331 /* The device we are working for */ 1332 ide_state = &s->dev[port].port.ifs[0]; 1333 if (!ide_state->blk) { 1334 trace_handle_cmd_badport(s, port); 1335 return; 1336 } 1337 1338 tbl_addr = le64_to_cpu(cmd->tbl_addr); 1339 cmd_len = 0x80; 1340 cmd_fis = dma_memory_map(s->as, tbl_addr, &cmd_len, 1341 DMA_DIRECTION_TO_DEVICE, MEMTXATTRS_UNSPECIFIED); 1342 if (!cmd_fis) { 1343 trace_handle_cmd_badfis(s, port); 1344 return; 1345 } else if (cmd_len != 0x80) { 1346 ahci_trigger_irq(s, &s->dev[port], AHCI_PORT_IRQ_BIT_HBFS); 1347 trace_handle_cmd_badmap(s, port, cmd_len); 1348 goto out; 1349 } 1350 if (trace_event_get_state_backends(TRACE_HANDLE_CMD_FIS_DUMP)) { 1351 char *pretty_fis = ahci_pretty_buffer_fis(cmd_fis, 0x80); 1352 trace_handle_cmd_fis_dump(s, port, pretty_fis); 1353 g_free(pretty_fis); 1354 } 1355 switch (cmd_fis[0]) { 1356 case SATA_FIS_TYPE_REGISTER_H2D: 1357 handle_reg_h2d_fis(s, port, slot, cmd_fis); 1358 break; 1359 default: 1360 trace_handle_cmd_unhandled_fis(s, port, 1361 cmd_fis[0], cmd_fis[1], cmd_fis[2]); 1362 break; 1363 } 1364 1365 out: 1366 dma_memory_unmap(s->as, cmd_fis, cmd_len, DMA_DIRECTION_TO_DEVICE, 1367 cmd_len); 1368 } 1369 1370 /* Transfer PIO data between RAM and device */ 1371 static void ahci_pio_transfer(const IDEDMA *dma) 1372 { 1373 AHCIDevice *ad = DO_UPCAST(AHCIDevice, dma, dma); 1374 IDEState *s = &ad->port.ifs[0]; 1375 uint32_t size = (uint32_t)(s->data_end - s->data_ptr); 1376 /* write == ram -> device */ 1377 uint16_t opts = le16_to_cpu(ad->cur_cmd->opts); 1378 int is_write = opts & AHCI_CMD_WRITE; 1379 int is_atapi = opts & AHCI_CMD_ATAPI; 1380 int has_sglist = 0; 1381 bool pio_fis_i; 1382 1383 /* The PIO Setup FIS is received prior to transfer, but the interrupt 1384 * is only triggered after data is received. 1385 * 1386 * The device only sets the 'I' bit in the PIO Setup FIS for device->host 1387 * requests (see "DPIOI1" in the SATA spec), or for host->device DRQs after 1388 * the first (see "DPIOO1"). The latter is consistent with the spec's 1389 * description of the PACKET protocol, where the command part of ATAPI requests 1390 * ("DPKT0") has the 'I' bit clear, while the data part of PIO ATAPI requests 1391 * ("DPKT4a" and "DPKT7") has the 'I' bit set for both directions for all DRQs. 1392 */ 1393 pio_fis_i = ad->done_first_drq || (!is_atapi && !is_write); 1394 ahci_write_fis_pio(ad, size, pio_fis_i); 1395 1396 if (is_atapi && !ad->done_first_drq) { 1397 /* already prepopulated iobuffer */ 1398 goto out; 1399 } 1400 1401 if (ahci_dma_prepare_buf(dma, size)) { 1402 has_sglist = 1; 1403 } 1404 1405 trace_ahci_pio_transfer(ad->hba, ad->port_no, is_write ? "writ" : "read", 1406 size, is_atapi ? "atapi" : "ata", 1407 has_sglist ? "" : "o"); 1408 1409 if (has_sglist && size) { 1410 const MemTxAttrs attrs = MEMTXATTRS_UNSPECIFIED; 1411 1412 if (is_write) { 1413 dma_buf_write(s->data_ptr, size, NULL, &s->sg, attrs); 1414 } else { 1415 dma_buf_read(s->data_ptr, size, NULL, &s->sg, attrs); 1416 } 1417 } 1418 1419 /* Update number of transferred bytes, destroy sglist */ 1420 dma_buf_commit(s, size); 1421 1422 out: 1423 /* declare that we processed everything */ 1424 s->data_ptr = s->data_end; 1425 1426 ad->done_first_drq = true; 1427 if (pio_fis_i) { 1428 ahci_trigger_irq(ad->hba, ad, AHCI_PORT_IRQ_BIT_PSS); 1429 } 1430 } 1431 1432 static void ahci_start_dma(const IDEDMA *dma, IDEState *s, 1433 BlockCompletionFunc *dma_cb) 1434 { 1435 AHCIDevice *ad = DO_UPCAST(AHCIDevice, dma, dma); 1436 trace_ahci_start_dma(ad->hba, ad->port_no); 1437 s->io_buffer_offset = 0; 1438 dma_cb(s, 0); 1439 } 1440 1441 static void ahci_restart_dma(const IDEDMA *dma) 1442 { 1443 /* Nothing to do, ahci_start_dma already resets s->io_buffer_offset. */ 1444 } 1445 1446 /** 1447 * IDE/PIO restarts are handled by the core layer, but NCQ commands 1448 * need an extra kick from the AHCI HBA. 1449 */ 1450 static void ahci_restart(const IDEDMA *dma) 1451 { 1452 AHCIDevice *ad = DO_UPCAST(AHCIDevice, dma, dma); 1453 int i; 1454 1455 for (i = 0; i < AHCI_MAX_CMDS; i++) { 1456 NCQTransferState *ncq_tfs = &ad->ncq_tfs[i]; 1457 if (ncq_tfs->halt) { 1458 execute_ncq_command(ncq_tfs); 1459 } 1460 } 1461 } 1462 1463 /** 1464 * Called in DMA and PIO R/W chains to read the PRDT. 1465 * Not shared with NCQ pathways. 1466 */ 1467 static int32_t ahci_dma_prepare_buf(const IDEDMA *dma, int32_t limit) 1468 { 1469 AHCIDevice *ad = DO_UPCAST(AHCIDevice, dma, dma); 1470 IDEState *s = &ad->port.ifs[0]; 1471 1472 if (ahci_populate_sglist(ad, &s->sg, ad->cur_cmd, 1473 limit, s->io_buffer_offset) == -1) { 1474 trace_ahci_dma_prepare_buf_fail(ad->hba, ad->port_no); 1475 return -1; 1476 } 1477 s->io_buffer_size = s->sg.size; 1478 1479 trace_ahci_dma_prepare_buf(ad->hba, ad->port_no, limit, s->io_buffer_size); 1480 return s->io_buffer_size; 1481 } 1482 1483 /** 1484 * Updates the command header with a bytes-read value. 1485 * Called via dma_buf_commit, for both DMA and PIO paths. 1486 * sglist destruction is handled within dma_buf_commit. 1487 */ 1488 static void ahci_commit_buf(const IDEDMA *dma, uint32_t tx_bytes) 1489 { 1490 AHCIDevice *ad = DO_UPCAST(AHCIDevice, dma, dma); 1491 1492 tx_bytes += le32_to_cpu(ad->cur_cmd->status); 1493 ad->cur_cmd->status = cpu_to_le32(tx_bytes); 1494 } 1495 1496 static int ahci_dma_rw_buf(const IDEDMA *dma, bool is_write) 1497 { 1498 AHCIDevice *ad = DO_UPCAST(AHCIDevice, dma, dma); 1499 IDEState *s = &ad->port.ifs[0]; 1500 uint8_t *p = s->io_buffer + s->io_buffer_index; 1501 int l = s->io_buffer_size - s->io_buffer_index; 1502 1503 if (ahci_populate_sglist(ad, &s->sg, ad->cur_cmd, l, s->io_buffer_offset)) { 1504 return 0; 1505 } 1506 1507 if (is_write) { 1508 dma_buf_read(p, l, NULL, &s->sg, MEMTXATTRS_UNSPECIFIED); 1509 } else { 1510 dma_buf_write(p, l, NULL, &s->sg, MEMTXATTRS_UNSPECIFIED); 1511 } 1512 1513 /* free sglist, update byte count */ 1514 dma_buf_commit(s, l); 1515 s->io_buffer_index += l; 1516 1517 trace_ahci_dma_rw_buf(ad->hba, ad->port_no, l); 1518 return 1; 1519 } 1520 1521 static void ahci_clear_cmd_issue(AHCIDevice *ad, uint8_t slot) 1522 { 1523 IDEState *ide_state = &ad->port.ifs[0]; 1524 1525 if (!(ide_state->status & ERR_STAT) && 1526 !(ide_state->status & (BUSY_STAT | DRQ_STAT))) { 1527 ad->port_regs.cmd_issue &= ~(1 << slot); 1528 } 1529 } 1530 1531 /* Non-NCQ command is done - This function is never called for NCQ commands. */ 1532 static void ahci_cmd_done(const IDEDMA *dma) 1533 { 1534 AHCIDevice *ad = DO_UPCAST(AHCIDevice, dma, dma); 1535 IDEState *ide_state = &ad->port.ifs[0]; 1536 1537 trace_ahci_cmd_done(ad->hba, ad->port_no); 1538 1539 /* no longer busy */ 1540 if (ad->busy_slot != -1) { 1541 ahci_clear_cmd_issue(ad, ad->busy_slot); 1542 ad->busy_slot = -1; 1543 } 1544 1545 /* 1546 * In reality, for non-NCQ commands, PxCI is cleared after receiving a D2H 1547 * FIS with the interrupt bit set, but since ahci_write_fis_d2h() will raise 1548 * an IRQ, we need to call them in reverse order. 1549 */ 1550 ahci_write_fis_d2h(ad, true); 1551 1552 if (!(ide_state->status & ERR_STAT) && 1553 ad->port_regs.cmd_issue && !ad->check_bh) { 1554 ad->check_bh = qemu_bh_new_guarded(ahci_check_cmd_bh, ad, 1555 &ad->mem_reentrancy_guard); 1556 qemu_bh_schedule(ad->check_bh); 1557 } 1558 } 1559 1560 static void ahci_irq_set(void *opaque, int n, int level) 1561 { 1562 qemu_log_mask(LOG_UNIMP, "ahci: IRQ#%d level:%d\n", n, level); 1563 } 1564 1565 static const IDEDMAOps ahci_dma_ops = { 1566 .start_dma = ahci_start_dma, 1567 .restart = ahci_restart, 1568 .restart_dma = ahci_restart_dma, 1569 .pio_transfer = ahci_pio_transfer, 1570 .prepare_buf = ahci_dma_prepare_buf, 1571 .commit_buf = ahci_commit_buf, 1572 .rw_buf = ahci_dma_rw_buf, 1573 .cmd_done = ahci_cmd_done, 1574 }; 1575 1576 void ahci_init(AHCIState *s, DeviceState *qdev) 1577 { 1578 /* XXX BAR size should be 1k, but that breaks, so bump it to 4k for now */ 1579 memory_region_init_io(&s->mem, OBJECT(qdev), &ahci_mem_ops, s, 1580 "ahci", AHCI_MEM_BAR_SIZE); 1581 memory_region_init_io(&s->idp, OBJECT(qdev), &ahci_idp_ops, s, 1582 "ahci-idp", 32); 1583 } 1584 1585 void ahci_realize(AHCIState *s, DeviceState *qdev, AddressSpace *as) 1586 { 1587 qemu_irq *irqs; 1588 int i; 1589 1590 s->as = as; 1591 assert(s->ports > 0); 1592 s->dev = g_new0(AHCIDevice, s->ports); 1593 ahci_reg_init(s); 1594 irqs = qemu_allocate_irqs(ahci_irq_set, s, s->ports); 1595 for (i = 0; i < s->ports; i++) { 1596 AHCIDevice *ad = &s->dev[i]; 1597 1598 ide_bus_init(&ad->port, sizeof(ad->port), qdev, i, 1); 1599 ide_bus_init_output_irq(&ad->port, irqs[i]); 1600 1601 ad->hba = s; 1602 ad->port_no = i; 1603 ad->port.dma = &ad->dma; 1604 ad->port.dma->ops = &ahci_dma_ops; 1605 ide_bus_register_restart_cb(&ad->port); 1606 } 1607 g_free(irqs); 1608 } 1609 1610 void ahci_uninit(AHCIState *s) 1611 { 1612 int i, j; 1613 1614 for (i = 0; i < s->ports; i++) { 1615 AHCIDevice *ad = &s->dev[i]; 1616 1617 for (j = 0; j < 2; j++) { 1618 ide_exit(&ad->port.ifs[j]); 1619 } 1620 object_unparent(OBJECT(&ad->port)); 1621 } 1622 1623 g_free(s->dev); 1624 } 1625 1626 void ahci_reset(AHCIState *s) 1627 { 1628 AHCIPortRegs *pr; 1629 int i; 1630 1631 trace_ahci_reset(s); 1632 1633 s->control_regs.irqstatus = 0; 1634 /* AHCI Enable (AE) 1635 * The implementation of this bit is dependent upon the value of the 1636 * CAP.SAM bit. If CAP.SAM is '0', then GHC.AE shall be read-write and 1637 * shall have a reset value of '0'. If CAP.SAM is '1', then AE shall be 1638 * read-only and shall have a reset value of '1'. 1639 * 1640 * We set HOST_CAP_AHCI so we must enable AHCI at reset. 1641 */ 1642 s->control_regs.ghc = HOST_CTL_AHCI_EN; 1643 1644 for (i = 0; i < s->ports; i++) { 1645 pr = &s->dev[i].port_regs; 1646 pr->irq_stat = 0; 1647 pr->irq_mask = 0; 1648 pr->scr_ctl = 0; 1649 pr->cmd = PORT_CMD_SPIN_UP | PORT_CMD_POWER_ON; 1650 ahci_reset_port(s, i); 1651 } 1652 } 1653 1654 static const VMStateDescription vmstate_ncq_tfs = { 1655 .name = "ncq state", 1656 .version_id = 1, 1657 .fields = (const VMStateField[]) { 1658 VMSTATE_UINT32(sector_count, NCQTransferState), 1659 VMSTATE_UINT64(lba, NCQTransferState), 1660 VMSTATE_UINT8(tag, NCQTransferState), 1661 VMSTATE_UINT8(cmd, NCQTransferState), 1662 VMSTATE_UINT8(slot, NCQTransferState), 1663 VMSTATE_BOOL(used, NCQTransferState), 1664 VMSTATE_BOOL(halt, NCQTransferState), 1665 VMSTATE_END_OF_LIST() 1666 }, 1667 }; 1668 1669 static const VMStateDescription vmstate_ahci_device = { 1670 .name = "ahci port", 1671 .version_id = 1, 1672 .fields = (const VMStateField[]) { 1673 VMSTATE_IDE_BUS(port, AHCIDevice), 1674 VMSTATE_IDE_DRIVE(port.ifs[0], AHCIDevice), 1675 VMSTATE_UINT32(port_state, AHCIDevice), 1676 VMSTATE_UINT32(finished, AHCIDevice), 1677 VMSTATE_UINT32(port_regs.lst_addr, AHCIDevice), 1678 VMSTATE_UINT32(port_regs.lst_addr_hi, AHCIDevice), 1679 VMSTATE_UINT32(port_regs.fis_addr, AHCIDevice), 1680 VMSTATE_UINT32(port_regs.fis_addr_hi, AHCIDevice), 1681 VMSTATE_UINT32(port_regs.irq_stat, AHCIDevice), 1682 VMSTATE_UINT32(port_regs.irq_mask, AHCIDevice), 1683 VMSTATE_UINT32(port_regs.cmd, AHCIDevice), 1684 VMSTATE_UINT32(port_regs.tfdata, AHCIDevice), 1685 VMSTATE_UINT32(port_regs.sig, AHCIDevice), 1686 VMSTATE_UINT32(port_regs.scr_stat, AHCIDevice), 1687 VMSTATE_UINT32(port_regs.scr_ctl, AHCIDevice), 1688 VMSTATE_UINT32(port_regs.scr_err, AHCIDevice), 1689 VMSTATE_UINT32(port_regs.scr_act, AHCIDevice), 1690 VMSTATE_UINT32(port_regs.cmd_issue, AHCIDevice), 1691 VMSTATE_BOOL(done_first_drq, AHCIDevice), 1692 VMSTATE_INT32(busy_slot, AHCIDevice), 1693 VMSTATE_BOOL(init_d2h_sent, AHCIDevice), 1694 VMSTATE_STRUCT_ARRAY(ncq_tfs, AHCIDevice, AHCI_MAX_CMDS, 1695 1, vmstate_ncq_tfs, NCQTransferState), 1696 VMSTATE_END_OF_LIST() 1697 }, 1698 }; 1699 1700 static int ahci_state_post_load(void *opaque, int version_id) 1701 { 1702 int i, j; 1703 struct AHCIDevice *ad; 1704 NCQTransferState *ncq_tfs; 1705 AHCIPortRegs *pr; 1706 AHCIState *s = opaque; 1707 1708 for (i = 0; i < s->ports; i++) { 1709 ad = &s->dev[i]; 1710 pr = &ad->port_regs; 1711 1712 if (!(pr->cmd & PORT_CMD_START) && (pr->cmd & PORT_CMD_LIST_ON)) { 1713 error_report("AHCI: DMA engine should be off, but status bit " 1714 "indicates it is still running."); 1715 return -1; 1716 } 1717 if (!(pr->cmd & PORT_CMD_FIS_RX) && (pr->cmd & PORT_CMD_FIS_ON)) { 1718 error_report("AHCI: FIS RX engine should be off, but status bit " 1719 "indicates it is still running."); 1720 return -1; 1721 } 1722 1723 /* After a migrate, the DMA/FIS engines are "off" and 1724 * need to be conditionally restarted */ 1725 pr->cmd &= ~(PORT_CMD_LIST_ON | PORT_CMD_FIS_ON); 1726 if (ahci_cond_start_engines(ad) != 0) { 1727 return -1; 1728 } 1729 1730 for (j = 0; j < AHCI_MAX_CMDS; j++) { 1731 ncq_tfs = &ad->ncq_tfs[j]; 1732 ncq_tfs->drive = ad; 1733 1734 if (ncq_tfs->used != ncq_tfs->halt) { 1735 return -1; 1736 } 1737 if (!ncq_tfs->halt) { 1738 continue; 1739 } 1740 if (!is_ncq(ncq_tfs->cmd)) { 1741 return -1; 1742 } 1743 if (ncq_tfs->slot != ncq_tfs->tag) { 1744 return -1; 1745 } 1746 /* If ncq_tfs->halt is justly set, the engine should be engaged, 1747 * and the command list buffer should be mapped. */ 1748 ncq_tfs->cmdh = get_cmd_header(s, i, ncq_tfs->slot); 1749 if (!ncq_tfs->cmdh) { 1750 return -1; 1751 } 1752 ahci_populate_sglist(ncq_tfs->drive, &ncq_tfs->sglist, 1753 ncq_tfs->cmdh, 1754 ncq_tfs->sector_count * BDRV_SECTOR_SIZE, 1755 0); 1756 if (ncq_tfs->sector_count != ncq_tfs->sglist.size >> 9) { 1757 return -1; 1758 } 1759 } 1760 1761 1762 /* 1763 * If an error is present, ad->busy_slot will be valid and not -1. 1764 * In this case, an operation is waiting to resume and will re-check 1765 * for additional AHCI commands to execute upon completion. 1766 * 1767 * In the case where no error was present, busy_slot will be -1, 1768 * and we should check to see if there are additional commands waiting. 1769 */ 1770 if (ad->busy_slot == -1) { 1771 check_cmd(s, i); 1772 } else { 1773 /* We are in the middle of a command, and may need to access 1774 * the command header in guest memory again. */ 1775 if (ad->busy_slot < 0 || ad->busy_slot >= AHCI_MAX_CMDS) { 1776 return -1; 1777 } 1778 ad->cur_cmd = get_cmd_header(s, i, ad->busy_slot); 1779 } 1780 } 1781 1782 return 0; 1783 } 1784 1785 const VMStateDescription vmstate_ahci = { 1786 .name = "ahci", 1787 .version_id = 1, 1788 .post_load = ahci_state_post_load, 1789 .fields = (const VMStateField[]) { 1790 VMSTATE_STRUCT_VARRAY_POINTER_UINT32(dev, AHCIState, ports, 1791 vmstate_ahci_device, AHCIDevice), 1792 VMSTATE_UINT32(control_regs.cap, AHCIState), 1793 VMSTATE_UINT32(control_regs.ghc, AHCIState), 1794 VMSTATE_UINT32(control_regs.irqstatus, AHCIState), 1795 VMSTATE_UINT32(control_regs.impl, AHCIState), 1796 VMSTATE_UINT32(control_regs.version, AHCIState), 1797 VMSTATE_UINT32(idp_index, AHCIState), 1798 VMSTATE_UINT32_EQUAL(ports, AHCIState, NULL), 1799 VMSTATE_END_OF_LIST() 1800 }, 1801 }; 1802 1803 void ahci_ide_create_devs(AHCIState *ahci, DriveInfo **hd) 1804 { 1805 int i; 1806 1807 for (i = 0; i < ahci->ports; i++) { 1808 if (hd[i] == NULL) { 1809 continue; 1810 } 1811 ide_bus_create_drive(&ahci->dev[i].port, 0, hd[i]); 1812 } 1813 } 1814