1 /* 2 * QEMU AHCI Emulation 3 * 4 * Copyright (c) 2010 qiaochong@loongson.cn 5 * Copyright (c) 2010 Roland Elek <elek.roland@gmail.com> 6 * Copyright (c) 2010 Sebastian Herbszt <herbszt@gmx.de> 7 * Copyright (c) 2010 Alexander Graf <agraf@suse.de> 8 * 9 * This library is free software; you can redistribute it and/or 10 * modify it under the terms of the GNU Lesser General Public 11 * License as published by the Free Software Foundation; either 12 * version 2 of the License, or (at your option) any later version. 13 * 14 * This library is distributed in the hope that it will be useful, 15 * but WITHOUT ANY WARRANTY; without even the implied warranty of 16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 17 * Lesser General Public License for more details. 18 * 19 * You should have received a copy of the GNU Lesser General Public 20 * License along with this library; if not, see <http://www.gnu.org/licenses/>. 21 * 22 */ 23 24 #ifndef HW_IDE_AHCI_INTERNAL_H 25 #define HW_IDE_AHCI_INTERNAL_H 26 27 #include "hw/ide/ahci.h" 28 #include "hw/sysbus.h" 29 30 #define AHCI_MEM_BAR_SIZE 0x1000 31 #define AHCI_MAX_PORTS 32 32 #define AHCI_MAX_SG 168 /* hardware max is 64K */ 33 #define AHCI_DMA_BOUNDARY 0xffffffff 34 #define AHCI_USE_CLUSTERING 0 35 #define AHCI_MAX_CMDS 32 36 #define AHCI_CMD_SZ 32 37 #define AHCI_CMD_SLOT_SZ (AHCI_MAX_CMDS * AHCI_CMD_SZ) 38 #define AHCI_RX_FIS_SZ 256 39 #define AHCI_CMD_TBL_CDB 0x40 40 #define AHCI_CMD_TBL_HDR_SZ 0x80 41 #define AHCI_CMD_TBL_SZ (AHCI_CMD_TBL_HDR_SZ + (AHCI_MAX_SG * 16)) 42 #define AHCI_CMD_TBL_AR_SZ (AHCI_CMD_TBL_SZ * AHCI_MAX_CMDS) 43 #define AHCI_PORT_PRIV_DMA_SZ (AHCI_CMD_SLOT_SZ + AHCI_CMD_TBL_AR_SZ + \ 44 AHCI_RX_FIS_SZ) 45 46 #define AHCI_IRQ_ON_SG (1U << 31) 47 #define AHCI_CMD_ATAPI (1 << 5) 48 #define AHCI_CMD_WRITE (1 << 6) 49 #define AHCI_CMD_PREFETCH (1 << 7) 50 #define AHCI_CMD_RESET (1 << 8) 51 #define AHCI_CMD_CLR_BUSY (1 << 10) 52 53 #define RX_FIS_D2H_REG 0x40 /* offset of D2H Register FIS data */ 54 #define RX_FIS_SDB 0x58 /* offset of SDB FIS data */ 55 #define RX_FIS_UNK 0x60 /* offset of Unknown FIS data */ 56 57 /* global controller registers */ 58 #define HOST_CAP 0x00 /* host capabilities */ 59 #define HOST_CTL 0x04 /* global host control */ 60 #define HOST_IRQ_STAT 0x08 /* interrupt status */ 61 #define HOST_PORTS_IMPL 0x0c /* bitmap of implemented ports */ 62 #define HOST_VERSION 0x10 /* AHCI spec. version compliancy */ 63 64 enum AHCIHostReg { 65 AHCI_HOST_REG_CAP = 0, /* CAP: host capabilities */ 66 AHCI_HOST_REG_CTL = 1, /* GHC: global host control */ 67 AHCI_HOST_REG_IRQ_STAT = 2, /* IS: interrupt status */ 68 AHCI_HOST_REG_PORTS_IMPL = 3, /* PI: bitmap of implemented ports */ 69 AHCI_HOST_REG_VERSION = 4, /* VS: AHCI spec. version compliancy */ 70 AHCI_HOST_REG_CCC_CTL = 5, /* CCC_CTL: CCC Control */ 71 AHCI_HOST_REG_CCC_PORTS = 6, /* CCC_PORTS: CCC Ports */ 72 AHCI_HOST_REG_EM_LOC = 7, /* EM_LOC: Enclosure Mgmt Location */ 73 AHCI_HOST_REG_EM_CTL = 8, /* EM_CTL: Enclosure Mgmt Control */ 74 AHCI_HOST_REG_CAP2 = 9, /* CAP2: host capabilities, extended */ 75 AHCI_HOST_REG_BOHC = 10, /* BOHC: firmare/os handoff ctrl & status */ 76 AHCI_HOST_REG__COUNT = 11 77 }; 78 79 /* HOST_CTL bits */ 80 #define HOST_CTL_RESET (1 << 0) /* reset controller; self-clear */ 81 #define HOST_CTL_IRQ_EN (1 << 1) /* global IRQ enable */ 82 #define HOST_CTL_AHCI_EN (1U << 31) /* AHCI enabled */ 83 84 /* HOST_CAP bits */ 85 #define HOST_CAP_SSC (1 << 14) /* Slumber capable */ 86 #define HOST_CAP_AHCI (1 << 18) /* AHCI only */ 87 #define HOST_CAP_CLO (1 << 24) /* Command List Override support */ 88 #define HOST_CAP_SSS (1 << 27) /* Staggered Spin-up */ 89 #define HOST_CAP_NCQ (1 << 30) /* Native Command Queueing */ 90 #define HOST_CAP_64 (1U << 31) /* PCI DAC (64-bit DMA) support */ 91 92 /* registers for each SATA port */ 93 enum AHCIPortReg { 94 AHCI_PORT_REG_LST_ADDR = 0, /* PxCLB: command list DMA addr */ 95 AHCI_PORT_REG_LST_ADDR_HI = 1, /* PxCLBU: command list DMA addr hi */ 96 AHCI_PORT_REG_FIS_ADDR = 2, /* PxFB: FIS rx buf addr */ 97 AHCI_PORT_REG_FIS_ADDR_HI = 3, /* PxFBU: FIX rx buf addr hi */ 98 AHCI_PORT_REG_IRQ_STAT = 4, /* PxIS: interrupt status */ 99 AHCI_PORT_REG_IRQ_MASK = 5, /* PxIE: interrupt enable/disable mask */ 100 AHCI_PORT_REG_CMD = 6, /* PxCMD: port command */ 101 /* RESERVED */ 102 AHCI_PORT_REG_TFDATA = 8, /* PxTFD: taskfile data */ 103 AHCI_PORT_REG_SIG = 9, /* PxSIG: device TF signature */ 104 AHCI_PORT_REG_SCR_STAT = 10, /* PxSSTS: SATA phy register: SStatus */ 105 AHCI_PORT_REG_SCR_CTL = 11, /* PxSCTL: SATA phy register: SControl */ 106 AHCI_PORT_REG_SCR_ERR = 12, /* PxSERR: SATA phy register: SError */ 107 AHCI_PORT_REG_SCR_ACT = 13, /* PxSACT: SATA phy register: SActive */ 108 AHCI_PORT_REG_CMD_ISSUE = 14, /* PxCI: command issue */ 109 AHCI_PORT_REG_SCR_NOTIF = 15, /* PxSNTF: SATA phy register: SNotification */ 110 AHCI_PORT_REG_FIS_CTL = 16, /* PxFBS: Port multiplier switching ctl */ 111 AHCI_PORT_REG_DEV_SLEEP = 17, /* PxDEVSLP: device sleep control */ 112 /* RESERVED */ 113 AHCI_PORT_REG_VENDOR_1 = 28, /* PxVS: Vendor Specific */ 114 AHCI_PORT_REG_VENDOR_2 = 29, 115 AHCI_PORT_REG_VENDOR_3 = 30, 116 AHCI_PORT_REG_VENDOR_4 = 31, 117 AHCI_PORT_REG__COUNT = 32 118 }; 119 120 /* Port interrupt bit descriptors */ 121 enum AHCIPortIRQ { 122 AHCI_PORT_IRQ_BIT_DHRS = 0, 123 AHCI_PORT_IRQ_BIT_PSS = 1, 124 AHCI_PORT_IRQ_BIT_DSS = 2, 125 AHCI_PORT_IRQ_BIT_SDBS = 3, 126 AHCI_PORT_IRQ_BIT_UFS = 4, 127 AHCI_PORT_IRQ_BIT_DPS = 5, 128 AHCI_PORT_IRQ_BIT_PCS = 6, 129 AHCI_PORT_IRQ_BIT_DMPS = 7, 130 /* RESERVED */ 131 AHCI_PORT_IRQ_BIT_PRCS = 22, 132 AHCI_PORT_IRQ_BIT_IPMS = 23, 133 AHCI_PORT_IRQ_BIT_OFS = 24, 134 /* RESERVED */ 135 AHCI_PORT_IRQ_BIT_INFS = 26, 136 AHCI_PORT_IRQ_BIT_IFS = 27, 137 AHCI_PORT_IRQ_BIT_HBDS = 28, 138 AHCI_PORT_IRQ_BIT_HBFS = 29, 139 AHCI_PORT_IRQ_BIT_TFES = 30, 140 AHCI_PORT_IRQ_BIT_CPDS = 31, 141 AHCI_PORT_IRQ__COUNT = 32 142 }; 143 144 145 /* PORT_IRQ_{STAT,MASK} bits */ 146 #define PORT_IRQ_COLD_PRES (1U << 31) /* cold presence detect */ 147 #define PORT_IRQ_TF_ERR (1 << 30) /* task file error */ 148 #define PORT_IRQ_HBUS_ERR (1 << 29) /* host bus fatal error */ 149 #define PORT_IRQ_HBUS_DATA_ERR (1 << 28) /* host bus data error */ 150 #define PORT_IRQ_IF_ERR (1 << 27) /* interface fatal error */ 151 #define PORT_IRQ_IF_NONFATAL (1 << 26) /* interface non-fatal error */ 152 /* reserved */ 153 #define PORT_IRQ_OVERFLOW (1 << 24) /* xfer exhausted available S/G */ 154 #define PORT_IRQ_BAD_PMP (1 << 23) /* incorrect port multiplier */ 155 #define PORT_IRQ_PHYRDY (1 << 22) /* PhyRdy changed */ 156 /* reserved */ 157 #define PORT_IRQ_DEV_ILCK (1 << 7) /* device interlock */ 158 #define PORT_IRQ_CONNECT (1 << 6) /* port connect change status */ 159 #define PORT_IRQ_SG_DONE (1 << 5) /* descriptor processed */ 160 #define PORT_IRQ_UNK_FIS (1 << 4) /* unknown FIS rx'd */ 161 #define PORT_IRQ_SDB_FIS (1 << 3) /* Set Device Bits FIS rx'd */ 162 #define PORT_IRQ_DMAS_FIS (1 << 2) /* DMA Setup FIS rx'd */ 163 #define PORT_IRQ_PIOS_FIS (1 << 1) /* PIO Setup FIS rx'd */ 164 #define PORT_IRQ_D2H_REG_FIS (1 << 0) /* D2H Register FIS rx'd */ 165 166 #define PORT_IRQ_FREEZE (PORT_IRQ_HBUS_ERR | PORT_IRQ_IF_ERR | \ 167 PORT_IRQ_CONNECT | PORT_IRQ_PHYRDY | \ 168 PORT_IRQ_UNK_FIS) 169 #define PORT_IRQ_ERROR (PORT_IRQ_FREEZE | PORT_IRQ_TF_ERR | \ 170 PORT_IRQ_HBUS_DATA_ERR) 171 #define DEF_PORT_IRQ (PORT_IRQ_ERROR | PORT_IRQ_SG_DONE | \ 172 PORT_IRQ_SDB_FIS | PORT_IRQ_DMAS_FIS | \ 173 PORT_IRQ_PIOS_FIS | PORT_IRQ_D2H_REG_FIS) 174 175 /* PORT_CMD bits */ 176 #define PORT_CMD_ATAPI (1 << 24) /* Device is ATAPI */ 177 #define PORT_CMD_LIST_ON (1 << 15) /* cmd list DMA engine running */ 178 #define PORT_CMD_FIS_ON (1 << 14) /* FIS DMA engine running */ 179 #define PORT_CMD_FIS_RX (1 << 4) /* Enable FIS receive DMA engine */ 180 #define PORT_CMD_CLO (1 << 3) /* Command list override */ 181 #define PORT_CMD_POWER_ON (1 << 2) /* Power up device */ 182 #define PORT_CMD_SPIN_UP (1 << 1) /* Spin up device */ 183 #define PORT_CMD_START (1 << 0) /* Enable port DMA engine */ 184 185 #define PORT_CMD_ICC_MASK (0xfU << 28) /* i/f ICC state mask */ 186 #define PORT_CMD_ICC_ACTIVE (0x1 << 28) /* Put i/f in active state */ 187 #define PORT_CMD_ICC_PARTIAL (0x2 << 28) /* Put i/f in partial state */ 188 #define PORT_CMD_ICC_SLUMBER (0x6 << 28) /* Put i/f in slumber state */ 189 190 #define PORT_CMD_RO_MASK 0x007dffe0 /* Which CMD bits are read only? */ 191 192 /* ap->flags bits */ 193 #define AHCI_FLAG_NO_NCQ (1 << 24) 194 #define AHCI_FLAG_IGN_IRQ_IF_ERR (1 << 25) /* ignore IRQ_IF_ERR */ 195 #define AHCI_FLAG_HONOR_PI (1 << 26) /* honor PORTS_IMPL */ 196 #define AHCI_FLAG_IGN_SERR_INTERNAL (1 << 27) /* ignore SERR_INTERNAL */ 197 #define AHCI_FLAG_32BIT_ONLY (1 << 28) /* force 32bit */ 198 199 #define ATA_SRST (1 << 2) /* software reset */ 200 201 #define STATE_RUN 0 202 #define STATE_RESET 1 203 204 #define SATA_SCR_SSTATUS_DET_NODEV 0x0 205 #define SATA_SCR_SSTATUS_DET_DEV_PRESENT_PHY_UP 0x3 206 207 #define SATA_SCR_SSTATUS_SPD_NODEV 0x00 208 #define SATA_SCR_SSTATUS_SPD_GEN1 0x10 209 210 #define SATA_SCR_SSTATUS_IPM_NODEV 0x000 211 #define SATA_SCR_SSTATUS_IPM_ACTIVE 0X100 212 213 #define AHCI_SCR_SCTL_DET 0xf 214 215 #define SATA_FIS_TYPE_REGISTER_H2D 0x27 216 #define SATA_FIS_REG_H2D_UPDATE_COMMAND_REGISTER 0x80 217 #define SATA_FIS_TYPE_REGISTER_D2H 0x34 218 #define SATA_FIS_TYPE_PIO_SETUP 0x5f 219 #define SATA_FIS_TYPE_SDB 0xA1 220 221 #define AHCI_CMD_HDR_CMD_FIS_LEN 0x1f 222 #define AHCI_CMD_HDR_PRDT_LEN 16 223 224 #define SATA_SIGNATURE_CDROM 0xeb140101 225 #define SATA_SIGNATURE_DISK 0x00000101 226 227 #define AHCI_GENERIC_HOST_CONTROL_REGS_MAX_ADDR 0x20 228 /* Shouldn't this be 0x2c? */ 229 230 #define AHCI_PORT_REGS_START_ADDR 0x100 231 #define AHCI_PORT_ADDR_OFFSET_MASK 0x7f 232 #define AHCI_PORT_ADDR_OFFSET_LEN 0x80 233 234 #define AHCI_NUM_COMMAND_SLOTS 31 235 #define AHCI_SUPPORTED_SPEED 20 236 #define AHCI_SUPPORTED_SPEED_GEN1 1 237 #define AHCI_VERSION_1_0 0x10000 238 239 #define AHCI_PROGMODE_MAJOR_REV_1 1 240 241 #define AHCI_COMMAND_TABLE_ACMD 0x40 242 243 #define AHCI_PRDT_SIZE_MASK 0x3fffff 244 245 #define IDE_FEATURE_DMA 1 246 247 #define READ_FPDMA_QUEUED 0x60 248 #define WRITE_FPDMA_QUEUED 0x61 249 #define NCQ_NON_DATA 0x63 250 #define RECEIVE_FPDMA_QUEUED 0x65 251 #define SEND_FPDMA_QUEUED 0x64 252 253 #define NCQ_FIS_FUA_MASK 0x80 254 #define NCQ_FIS_RARC_MASK 0x01 255 256 #define RES_FIS_DSFIS 0x00 257 #define RES_FIS_PSFIS 0x20 258 #define RES_FIS_RFIS 0x40 259 #define RES_FIS_SDBFIS 0x58 260 #define RES_FIS_UFIS 0x60 261 262 #define SATA_CAP_SIZE 0x8 263 #define SATA_CAP_REV 0x2 264 #define SATA_CAP_BAR 0x4 265 266 typedef struct AHCIPortRegs { 267 uint32_t lst_addr; 268 uint32_t lst_addr_hi; 269 uint32_t fis_addr; 270 uint32_t fis_addr_hi; 271 uint32_t irq_stat; 272 uint32_t irq_mask; 273 uint32_t cmd; 274 uint32_t unused0; 275 uint32_t tfdata; 276 uint32_t sig; 277 uint32_t scr_stat; 278 uint32_t scr_ctl; 279 uint32_t scr_err; 280 uint32_t scr_act; 281 uint32_t cmd_issue; 282 uint32_t reserved; 283 } AHCIPortRegs; 284 285 typedef struct AHCICmdHdr { 286 uint16_t opts; 287 uint16_t prdtl; 288 uint32_t status; 289 uint64_t tbl_addr; 290 uint32_t reserved[4]; 291 } QEMU_PACKED AHCICmdHdr; 292 293 typedef struct AHCI_SG { 294 uint64_t addr; 295 uint32_t reserved; 296 uint32_t flags_size; 297 } QEMU_PACKED AHCI_SG; 298 299 typedef struct NCQTransferState { 300 AHCIDevice *drive; 301 BlockAIOCB *aiocb; 302 AHCICmdHdr *cmdh; 303 QEMUSGList sglist; 304 BlockAcctCookie acct; 305 uint32_t sector_count; 306 uint64_t lba; 307 uint8_t tag; 308 uint8_t cmd; 309 uint8_t slot; 310 bool used; 311 bool halt; 312 } NCQTransferState; 313 314 struct AHCIDevice { 315 IDEDMA dma; 316 IDEBus port; 317 int port_no; 318 uint32_t port_state; 319 uint32_t finished; 320 AHCIPortRegs port_regs; 321 struct AHCIState *hba; 322 QEMUBH *check_bh; 323 uint8_t *lst; 324 uint8_t *res_fis; 325 bool done_atapi_packet; 326 int32_t busy_slot; 327 bool init_d2h_sent; 328 AHCICmdHdr *cur_cmd; 329 NCQTransferState ncq_tfs[AHCI_MAX_CMDS]; 330 }; 331 332 struct AHCIPCIState { 333 /*< private >*/ 334 PCIDevice parent_obj; 335 /*< public >*/ 336 337 AHCIState ahci; 338 }; 339 340 #define ICH_AHCI(obj) \ 341 OBJECT_CHECK(AHCIPCIState, (obj), TYPE_ICH9_AHCI) 342 343 extern const VMStateDescription vmstate_ahci; 344 345 #define VMSTATE_AHCI(_field, _state) { \ 346 .name = (stringify(_field)), \ 347 .size = sizeof(AHCIState), \ 348 .vmsd = &vmstate_ahci, \ 349 .flags = VMS_STRUCT, \ 350 .offset = vmstate_offset_value(_state, _field, AHCIState), \ 351 } 352 353 /** 354 * NCQFrame is the same as a Register H2D FIS (described in SATA 3.2), 355 * but some fields have been re-mapped and re-purposed, as seen in 356 * SATA 3.2 section 13.6.4.1 ("READ FPDMA QUEUED") 357 * 358 * cmd_fis[3], feature 7:0, becomes sector count 7:0. 359 * cmd_fis[7], device 7:0, uses bit 7 as the Force Unit Access bit. 360 * cmd_fis[11], feature 15:8, becomes sector count 15:8. 361 * cmd_fis[12], count 7:0, becomes the NCQ TAG (7:3) and RARC bit (0) 362 * cmd_fis[13], count 15:8, becomes the priority value (7:6) 363 * bytes 16-19 become an le32 "auxiliary" field. 364 */ 365 typedef struct NCQFrame { 366 uint8_t fis_type; 367 uint8_t c; 368 uint8_t command; 369 uint8_t sector_count_low; /* (feature 7:0) */ 370 uint8_t lba0; 371 uint8_t lba1; 372 uint8_t lba2; 373 uint8_t fua; /* (device 7:0) */ 374 uint8_t lba3; 375 uint8_t lba4; 376 uint8_t lba5; 377 uint8_t sector_count_high; /* (feature 15:8) */ 378 uint8_t tag; /* (count 0:7) */ 379 uint8_t prio; /* (count 15:8) */ 380 uint8_t icc; 381 uint8_t control; 382 uint8_t aux0; 383 uint8_t aux1; 384 uint8_t aux2; 385 uint8_t aux3; 386 } QEMU_PACKED NCQFrame; 387 388 typedef struct SDBFIS { 389 uint8_t type; 390 uint8_t flags; 391 uint8_t status; 392 uint8_t error; 393 uint32_t payload; 394 } QEMU_PACKED SDBFIS; 395 396 void ahci_realize(AHCIState *s, DeviceState *qdev, AddressSpace *as, int ports); 397 void ahci_init(AHCIState *s, DeviceState *qdev); 398 void ahci_uninit(AHCIState *s); 399 400 void ahci_reset(AHCIState *s); 401 402 #define SYSBUS_AHCI(obj) OBJECT_CHECK(SysbusAHCIState, (obj), TYPE_SYSBUS_AHCI) 403 404 #endif /* HW_IDE_AHCI_H */ 405