1 /* 2 * TPR optimization for 32-bit Windows guests (XP and Server 2003) 3 * 4 * Copyright (C) 2007-2008 Qumranet Technologies 5 * Copyright (C) 2012 Jan Kiszka, Siemens AG 6 * 7 * This work is licensed under the terms of the GNU GPL version 2, or 8 * (at your option) any later version. See the COPYING file in the 9 * top-level directory. 10 */ 11 12 #include "qemu/osdep.h" 13 #include "qemu/module.h" 14 #include "exec/target_page.h" 15 #include "system/system.h" 16 #include "system/cpus.h" 17 #include "system/hw_accel.h" 18 #include "system/kvm.h" 19 #include "system/runstate.h" 20 #include "system/address-spaces.h" 21 #include "hw/i386/apic_internal.h" 22 #include "hw/sysbus.h" 23 #include "hw/boards.h" 24 #include "migration/vmstate.h" 25 #include "qom/object.h" 26 27 #define VAPIC_IO_PORT 0x7e 28 29 #define VAPIC_CPU_SHIFT 7 30 31 #define ROM_BLOCK_SIZE 512 32 #define ROM_BLOCK_MASK (~(ROM_BLOCK_SIZE - 1)) 33 34 typedef enum VAPICMode { 35 VAPIC_INACTIVE = 0, 36 VAPIC_ACTIVE = 1, 37 VAPIC_STANDBY = 2, 38 } VAPICMode; 39 40 typedef struct VAPICHandlers { 41 uint32_t set_tpr; 42 uint32_t set_tpr_eax; 43 uint32_t get_tpr[8]; 44 uint32_t get_tpr_stack; 45 } QEMU_PACKED VAPICHandlers; 46 47 typedef struct GuestROMState { 48 char signature[8]; 49 uint32_t vaddr; 50 uint32_t fixup_start; 51 uint32_t fixup_end; 52 uint32_t vapic_vaddr; 53 uint32_t vapic_size; 54 uint32_t vcpu_shift; 55 uint32_t real_tpr_addr; 56 VAPICHandlers up; 57 VAPICHandlers mp; 58 } QEMU_PACKED GuestROMState; 59 60 struct VAPICROMState { 61 SysBusDevice busdev; 62 63 MemoryRegion io; 64 MemoryRegion rom; 65 uint32_t state; 66 uint32_t rom_state_paddr; 67 uint32_t rom_state_vaddr; 68 uint32_t vapic_paddr; 69 uint32_t real_tpr_addr; 70 GuestROMState rom_state; 71 size_t rom_size; 72 bool rom_mapped_writable; 73 VMChangeStateEntry *vmsentry; 74 }; 75 76 #define TYPE_VAPIC "kvmvapic" 77 OBJECT_DECLARE_SIMPLE_TYPE(VAPICROMState, VAPIC) 78 79 #define TPR_INSTR_ABS_MODRM 0x1 80 #define TPR_INSTR_MATCH_MODRM_REG 0x2 81 82 typedef struct TPRInstruction { 83 uint8_t opcode; 84 uint8_t modrm_reg; 85 unsigned int flags; 86 TPRAccess access; 87 size_t length; 88 off_t addr_offset; 89 } TPRInstruction; 90 91 /* must be sorted by length, shortest first */ 92 static const TPRInstruction tpr_instr[] = { 93 { /* mov abs to eax */ 94 .opcode = 0xa1, 95 .access = TPR_ACCESS_READ, 96 .length = 5, 97 .addr_offset = 1, 98 }, 99 { /* mov eax to abs */ 100 .opcode = 0xa3, 101 .access = TPR_ACCESS_WRITE, 102 .length = 5, 103 .addr_offset = 1, 104 }, 105 { /* mov r32 to r/m32 */ 106 .opcode = 0x89, 107 .flags = TPR_INSTR_ABS_MODRM, 108 .access = TPR_ACCESS_WRITE, 109 .length = 6, 110 .addr_offset = 2, 111 }, 112 { /* mov r/m32 to r32 */ 113 .opcode = 0x8b, 114 .flags = TPR_INSTR_ABS_MODRM, 115 .access = TPR_ACCESS_READ, 116 .length = 6, 117 .addr_offset = 2, 118 }, 119 { /* push r/m32 */ 120 .opcode = 0xff, 121 .modrm_reg = 6, 122 .flags = TPR_INSTR_ABS_MODRM | TPR_INSTR_MATCH_MODRM_REG, 123 .access = TPR_ACCESS_READ, 124 .length = 6, 125 .addr_offset = 2, 126 }, 127 { /* mov imm32, r/m32 (c7/0) */ 128 .opcode = 0xc7, 129 .modrm_reg = 0, 130 .flags = TPR_INSTR_ABS_MODRM | TPR_INSTR_MATCH_MODRM_REG, 131 .access = TPR_ACCESS_WRITE, 132 .length = 10, 133 .addr_offset = 2, 134 }, 135 }; 136 137 static void read_guest_rom_state(VAPICROMState *s) 138 { 139 cpu_physical_memory_read(s->rom_state_paddr, &s->rom_state, 140 sizeof(GuestROMState)); 141 } 142 143 static void write_guest_rom_state(VAPICROMState *s) 144 { 145 cpu_physical_memory_write(s->rom_state_paddr, &s->rom_state, 146 sizeof(GuestROMState)); 147 } 148 149 static void update_guest_rom_state(VAPICROMState *s) 150 { 151 read_guest_rom_state(s); 152 153 s->rom_state.real_tpr_addr = cpu_to_le32(s->real_tpr_addr); 154 s->rom_state.vcpu_shift = cpu_to_le32(VAPIC_CPU_SHIFT); 155 156 write_guest_rom_state(s); 157 } 158 159 static int find_real_tpr_addr(VAPICROMState *s, CPUX86State *env) 160 { 161 CPUState *cs = env_cpu(env); 162 hwaddr paddr; 163 target_ulong addr; 164 165 if (s->state == VAPIC_ACTIVE) { 166 return 0; 167 } 168 /* 169 * If there is no prior TPR access instruction we could analyze (which is 170 * the case after resume from hibernation), we need to scan the possible 171 * virtual address space for the APIC mapping. 172 */ 173 for (addr = 0xfffff000; addr >= 0x80000000; addr -= TARGET_PAGE_SIZE) { 174 paddr = cpu_get_phys_page_debug(cs, addr); 175 if (paddr != APIC_DEFAULT_ADDRESS) { 176 continue; 177 } 178 s->real_tpr_addr = addr + 0x80; 179 update_guest_rom_state(s); 180 return 0; 181 } 182 return -1; 183 } 184 185 static uint8_t modrm_reg(uint8_t modrm) 186 { 187 return (modrm >> 3) & 7; 188 } 189 190 static bool is_abs_modrm(uint8_t modrm) 191 { 192 return (modrm & 0xc7) == 0x05; 193 } 194 195 static bool opcode_matches(uint8_t *opcode, const TPRInstruction *instr) 196 { 197 return opcode[0] == instr->opcode && 198 (!(instr->flags & TPR_INSTR_ABS_MODRM) || is_abs_modrm(opcode[1])) && 199 (!(instr->flags & TPR_INSTR_MATCH_MODRM_REG) || 200 modrm_reg(opcode[1]) == instr->modrm_reg); 201 } 202 203 static int evaluate_tpr_instruction(VAPICROMState *s, X86CPU *cpu, 204 target_ulong *pip, TPRAccess access) 205 { 206 CPUState *cs = CPU(cpu); 207 const TPRInstruction *instr; 208 target_ulong ip = *pip; 209 uint8_t opcode[2]; 210 uint32_t real_tpr_addr; 211 int i; 212 213 if ((ip & 0xf0000000ULL) != 0x80000000ULL && 214 (ip & 0xf0000000ULL) != 0xe0000000ULL) { 215 return -1; 216 } 217 218 /* 219 * Early Windows 2003 SMP initialization contains a 220 * 221 * mov imm32, r/m32 222 * 223 * instruction that is patched by TPR optimization. The problem is that 224 * RSP, used by the patched instruction, is zero, so the guest gets a 225 * double fault and dies. 226 */ 227 if (cpu->env.regs[R_ESP] == 0) { 228 return -1; 229 } 230 231 if (kvm_enabled() && !kvm_irqchip_in_kernel()) { 232 /* 233 * KVM without kernel-based TPR access reporting will pass an IP that 234 * points after the accessing instruction. So we need to look backward 235 * to find the reason. 236 */ 237 for (i = 0; i < ARRAY_SIZE(tpr_instr); i++) { 238 instr = &tpr_instr[i]; 239 if (instr->access != access) { 240 continue; 241 } 242 if (cpu_memory_rw_debug(cs, ip - instr->length, opcode, 243 sizeof(opcode), 0) < 0) { 244 return -1; 245 } 246 if (opcode_matches(opcode, instr)) { 247 ip -= instr->length; 248 goto instruction_ok; 249 } 250 } 251 return -1; 252 } else { 253 if (cpu_memory_rw_debug(cs, ip, opcode, sizeof(opcode), 0) < 0) { 254 return -1; 255 } 256 for (i = 0; i < ARRAY_SIZE(tpr_instr); i++) { 257 instr = &tpr_instr[i]; 258 if (opcode_matches(opcode, instr)) { 259 goto instruction_ok; 260 } 261 } 262 return -1; 263 } 264 265 instruction_ok: 266 /* 267 * Grab the virtual TPR address from the instruction 268 * and update the cached values. 269 */ 270 if (cpu_memory_rw_debug(cs, ip + instr->addr_offset, 271 (void *)&real_tpr_addr, 272 sizeof(real_tpr_addr), 0) < 0) { 273 return -1; 274 } 275 real_tpr_addr = le32_to_cpu(real_tpr_addr); 276 if ((real_tpr_addr & 0xfff) != 0x80) { 277 return -1; 278 } 279 s->real_tpr_addr = real_tpr_addr; 280 update_guest_rom_state(s); 281 282 *pip = ip; 283 return 0; 284 } 285 286 static int update_rom_mapping(VAPICROMState *s, CPUX86State *env, target_ulong ip) 287 { 288 CPUState *cs = env_cpu(env); 289 hwaddr paddr; 290 uint32_t rom_state_vaddr; 291 uint32_t pos, patch, offset; 292 293 /* nothing to do if already activated */ 294 if (s->state == VAPIC_ACTIVE) { 295 return 0; 296 } 297 298 /* bail out if ROM init code was not executed (missing ROM?) */ 299 if (s->state == VAPIC_INACTIVE) { 300 return -1; 301 } 302 303 /* find out virtual address of the ROM */ 304 rom_state_vaddr = s->rom_state_paddr + (ip & 0xf0000000); 305 paddr = cpu_get_phys_page_debug(cs, rom_state_vaddr); 306 if (paddr == -1) { 307 return -1; 308 } 309 paddr += rom_state_vaddr & ~TARGET_PAGE_MASK; 310 if (paddr != s->rom_state_paddr) { 311 return -1; 312 } 313 read_guest_rom_state(s); 314 if (memcmp(s->rom_state.signature, "kvm aPiC", 8) != 0) { 315 return -1; 316 } 317 s->rom_state_vaddr = rom_state_vaddr; 318 319 /* fixup addresses in ROM if needed */ 320 if (rom_state_vaddr == le32_to_cpu(s->rom_state.vaddr)) { 321 return 0; 322 } 323 for (pos = le32_to_cpu(s->rom_state.fixup_start); 324 pos < le32_to_cpu(s->rom_state.fixup_end); 325 pos += 4) { 326 cpu_physical_memory_read(paddr + pos - s->rom_state.vaddr, 327 &offset, sizeof(offset)); 328 offset = le32_to_cpu(offset); 329 cpu_physical_memory_read(paddr + offset, &patch, sizeof(patch)); 330 patch = le32_to_cpu(patch); 331 patch += rom_state_vaddr - le32_to_cpu(s->rom_state.vaddr); 332 patch = cpu_to_le32(patch); 333 cpu_physical_memory_write(paddr + offset, &patch, sizeof(patch)); 334 } 335 read_guest_rom_state(s); 336 s->vapic_paddr = paddr + le32_to_cpu(s->rom_state.vapic_vaddr) - 337 le32_to_cpu(s->rom_state.vaddr); 338 339 return 0; 340 } 341 342 /* 343 * Tries to read the unique processor number from the Kernel Processor Control 344 * Region (KPCR) of 32-bit Windows XP and Server 2003. Returns -1 if the KPCR 345 * cannot be accessed or is considered invalid. This also ensures that we are 346 * not patching the wrong guest. 347 */ 348 static int get_kpcr_number(X86CPU *cpu) 349 { 350 CPUX86State *env = &cpu->env; 351 struct kpcr { 352 uint8_t fill1[0x1c]; 353 uint32_t self; 354 uint8_t fill2[0x31]; 355 uint8_t number; 356 } QEMU_PACKED kpcr; 357 358 if (cpu_memory_rw_debug(CPU(cpu), env->segs[R_FS].base, 359 (void *)&kpcr, sizeof(kpcr), 0) < 0 || 360 kpcr.self != env->segs[R_FS].base) { 361 return -1; 362 } 363 return kpcr.number; 364 } 365 366 static int vapic_enable(VAPICROMState *s, X86CPU *cpu) 367 { 368 int cpu_number = get_kpcr_number(cpu); 369 hwaddr vapic_paddr; 370 static const uint8_t enabled = 1; 371 372 if (cpu_number < 0) { 373 return -1; 374 } 375 vapic_paddr = s->vapic_paddr + 376 (((hwaddr)cpu_number) << VAPIC_CPU_SHIFT); 377 cpu_physical_memory_write(vapic_paddr + offsetof(VAPICState, enabled), 378 &enabled, sizeof(enabled)); 379 apic_enable_vapic(cpu->apic_state, vapic_paddr); 380 381 s->state = VAPIC_ACTIVE; 382 383 return 0; 384 } 385 386 static void patch_byte(X86CPU *cpu, target_ulong addr, uint8_t byte) 387 { 388 cpu_memory_rw_debug(CPU(cpu), addr, &byte, 1, 1); 389 } 390 391 static void patch_call(X86CPU *cpu, target_ulong ip, uint32_t target) 392 { 393 uint32_t offset; 394 395 offset = cpu_to_le32(target - ip - 5); 396 patch_byte(cpu, ip, 0xe8); /* call near */ 397 cpu_memory_rw_debug(CPU(cpu), ip + 1, (void *)&offset, sizeof(offset), 1); 398 } 399 400 typedef struct PatchInfo { 401 VAPICHandlers *handler; 402 target_ulong ip; 403 } PatchInfo; 404 405 static void do_patch_instruction(CPUState *cs, run_on_cpu_data data) 406 { 407 X86CPU *x86_cpu = X86_CPU(cs); 408 PatchInfo *info = (PatchInfo *) data.host_ptr; 409 VAPICHandlers *handlers = info->handler; 410 target_ulong ip = info->ip; 411 uint8_t opcode[2]; 412 uint32_t imm32 = 0; 413 414 cpu_memory_rw_debug(cs, ip, opcode, sizeof(opcode), 0); 415 416 switch (opcode[0]) { 417 case 0x89: /* mov r32 to r/m32 */ 418 patch_byte(x86_cpu, ip, 0x50 + modrm_reg(opcode[1])); /* push reg */ 419 patch_call(x86_cpu, ip + 1, handlers->set_tpr); 420 break; 421 case 0x8b: /* mov r/m32 to r32 */ 422 patch_byte(x86_cpu, ip, 0x90); 423 patch_call(x86_cpu, ip + 1, handlers->get_tpr[modrm_reg(opcode[1])]); 424 break; 425 case 0xa1: /* mov abs to eax */ 426 patch_call(x86_cpu, ip, handlers->get_tpr[0]); 427 break; 428 case 0xa3: /* mov eax to abs */ 429 patch_call(x86_cpu, ip, handlers->set_tpr_eax); 430 break; 431 case 0xc7: /* mov imm32, r/m32 (c7/0) */ 432 patch_byte(x86_cpu, ip, 0x68); /* push imm32 */ 433 cpu_memory_rw_debug(cs, ip + 6, (void *)&imm32, sizeof(imm32), 0); 434 cpu_memory_rw_debug(cs, ip + 1, (void *)&imm32, sizeof(imm32), 1); 435 patch_call(x86_cpu, ip + 5, handlers->set_tpr); 436 break; 437 case 0xff: /* push r/m32 */ 438 patch_byte(x86_cpu, ip, 0x50); /* push eax */ 439 patch_call(x86_cpu, ip + 1, handlers->get_tpr_stack); 440 break; 441 default: 442 abort(); 443 } 444 445 g_free(info); 446 } 447 448 static void patch_instruction(VAPICROMState *s, X86CPU *cpu, target_ulong ip) 449 { 450 MachineState *ms = MACHINE(qdev_get_machine()); 451 CPUState *cs = CPU(cpu); 452 VAPICHandlers *handlers; 453 PatchInfo *info; 454 455 if (ms->smp.cpus == 1) { 456 handlers = &s->rom_state.up; 457 } else { 458 handlers = &s->rom_state.mp; 459 } 460 461 info = g_new(PatchInfo, 1); 462 info->handler = handlers; 463 info->ip = ip; 464 465 async_safe_run_on_cpu(cs, do_patch_instruction, RUN_ON_CPU_HOST_PTR(info)); 466 } 467 468 void vapic_report_tpr_access(DeviceState *dev, CPUState *cs, target_ulong ip, 469 TPRAccess access) 470 { 471 VAPICROMState *s = VAPIC(dev); 472 X86CPU *cpu = X86_CPU(cs); 473 CPUX86State *env = &cpu->env; 474 475 cpu_synchronize_state(cs); 476 477 if (evaluate_tpr_instruction(s, cpu, &ip, access) < 0) { 478 if (s->state == VAPIC_ACTIVE) { 479 vapic_enable(s, cpu); 480 } 481 return; 482 } 483 if (update_rom_mapping(s, env, ip) < 0) { 484 return; 485 } 486 if (vapic_enable(s, cpu) < 0) { 487 return; 488 } 489 patch_instruction(s, cpu, ip); 490 } 491 492 typedef struct VAPICEnableTPRReporting { 493 DeviceState *apic; 494 bool enable; 495 } VAPICEnableTPRReporting; 496 497 static void vapic_do_enable_tpr_reporting(CPUState *cpu, run_on_cpu_data data) 498 { 499 VAPICEnableTPRReporting *info = data.host_ptr; 500 apic_enable_tpr_access_reporting(info->apic, info->enable); 501 } 502 503 static void vapic_enable_tpr_reporting(bool enable) 504 { 505 VAPICEnableTPRReporting info = { 506 .enable = enable, 507 }; 508 CPUState *cs; 509 X86CPU *cpu; 510 511 CPU_FOREACH(cs) { 512 cpu = X86_CPU(cs); 513 info.apic = cpu->apic_state; 514 run_on_cpu(cs, vapic_do_enable_tpr_reporting, RUN_ON_CPU_HOST_PTR(&info)); 515 } 516 } 517 518 static void vapic_reset(DeviceState *dev) 519 { 520 VAPICROMState *s = VAPIC(dev); 521 522 s->state = VAPIC_INACTIVE; 523 s->rom_state_paddr = 0; 524 vapic_enable_tpr_reporting(false); 525 } 526 527 /* 528 * Set the IRQ polling hypercalls to the supported variant: 529 * - vmcall if using KVM in-kernel irqchip 530 * - 32-bit VAPIC port write otherwise 531 */ 532 static int patch_hypercalls(VAPICROMState *s) 533 { 534 hwaddr rom_paddr = s->rom_state_paddr & ROM_BLOCK_MASK; 535 static const uint8_t vmcall_pattern[] = { /* vmcall */ 536 0xb8, 0x1, 0, 0, 0, 0xf, 0x1, 0xc1 537 }; 538 static const uint8_t outl_pattern[] = { /* nop; outl %eax,0x7e */ 539 0xb8, 0x1, 0, 0, 0, 0x90, 0xe7, 0x7e 540 }; 541 uint8_t alternates[2]; 542 const uint8_t *pattern; 543 const uint8_t *patch; 544 off_t pos; 545 uint8_t *rom; 546 547 rom = g_malloc(s->rom_size); 548 cpu_physical_memory_read(rom_paddr, rom, s->rom_size); 549 550 for (pos = 0; pos < s->rom_size - sizeof(vmcall_pattern); pos++) { 551 if (kvm_irqchip_in_kernel()) { 552 pattern = outl_pattern; 553 alternates[0] = outl_pattern[7]; 554 alternates[1] = outl_pattern[7]; 555 patch = &vmcall_pattern[5]; 556 } else { 557 pattern = vmcall_pattern; 558 alternates[0] = vmcall_pattern[7]; 559 alternates[1] = 0xd9; /* AMD's VMMCALL */ 560 patch = &outl_pattern[5]; 561 } 562 if (memcmp(rom + pos, pattern, 7) == 0 && 563 (rom[pos + 7] == alternates[0] || rom[pos + 7] == alternates[1])) { 564 cpu_physical_memory_write(rom_paddr + pos + 5, patch, 3); 565 /* 566 * Don't flush the tb here. Under ordinary conditions, the patched 567 * calls are miles away from the current IP. Under malicious 568 * conditions, the guest could trick us to crash. 569 */ 570 } 571 } 572 573 g_free(rom); 574 return 0; 575 } 576 577 /* 578 * For TCG mode or the time KVM honors read-only memory regions, we need to 579 * enable write access to the option ROM so that variables can be updated by 580 * the guest. 581 */ 582 static int vapic_map_rom_writable(VAPICROMState *s) 583 { 584 hwaddr rom_paddr = s->rom_state_paddr & ROM_BLOCK_MASK; 585 MemoryRegionSection section; 586 MemoryRegion *mr = get_system_memory(); 587 size_t rom_size; 588 uint8_t *ram; 589 590 if (s->rom_mapped_writable) { 591 memory_region_del_subregion(mr, &s->rom); 592 object_unparent(OBJECT(&s->rom)); 593 } 594 595 /* grab RAM memory region (region @rom_paddr may still be pc.rom) */ 596 section = memory_region_find(mr, 0, 1); 597 598 /* read ROM size from RAM region */ 599 if (rom_paddr + 2 >= memory_region_size(section.mr)) { 600 return -1; 601 } 602 ram = memory_region_get_ram_ptr(section.mr); 603 rom_size = ram[rom_paddr + 2] * ROM_BLOCK_SIZE; 604 if (rom_size == 0) { 605 return -1; 606 } 607 s->rom_size = rom_size; 608 609 /* We need to round to avoid creating subpages 610 * from which we cannot run code. */ 611 rom_size += rom_paddr & ~TARGET_PAGE_MASK; 612 rom_paddr &= TARGET_PAGE_MASK; 613 rom_size = TARGET_PAGE_ALIGN(rom_size); 614 615 memory_region_init_alias(&s->rom, OBJECT(s), "kvmvapic-rom", section.mr, 616 rom_paddr, rom_size); 617 memory_region_add_subregion_overlap(mr, rom_paddr, &s->rom, 1000); 618 s->rom_mapped_writable = true; 619 memory_region_unref(section.mr); 620 621 return 0; 622 } 623 624 static int vapic_prepare(VAPICROMState *s) 625 { 626 if (vapic_map_rom_writable(s) < 0) { 627 return -1; 628 } 629 630 if (patch_hypercalls(s) < 0) { 631 return -1; 632 } 633 634 vapic_enable_tpr_reporting(true); 635 636 return 0; 637 } 638 639 static void vapic_write(void *opaque, hwaddr addr, uint64_t data, 640 unsigned int size) 641 { 642 VAPICROMState *s = opaque; 643 X86CPU *cpu; 644 CPUX86State *env; 645 hwaddr rom_paddr; 646 647 if (!current_cpu) { 648 return; 649 } 650 651 cpu_synchronize_state(current_cpu); 652 cpu = X86_CPU(current_cpu); 653 env = &cpu->env; 654 655 /* 656 * The VAPIC supports two PIO-based hypercalls, both via port 0x7E. 657 * o 16-bit write access: 658 * Reports the option ROM initialization to the hypervisor. Written 659 * value is the offset of the state structure in the ROM. 660 * o 8-bit write access: 661 * Reactivates the VAPIC after a guest hibernation, i.e. after the 662 * option ROM content has been re-initialized by a guest power cycle. 663 * o 32-bit write access: 664 * Poll for pending IRQs, considering the current VAPIC state. 665 */ 666 switch (size) { 667 case 2: 668 if (s->state == VAPIC_INACTIVE) { 669 rom_paddr = (env->segs[R_CS].base + env->eip) & ROM_BLOCK_MASK; 670 s->rom_state_paddr = rom_paddr + data; 671 672 s->state = VAPIC_STANDBY; 673 } 674 if (vapic_prepare(s) < 0) { 675 s->state = VAPIC_INACTIVE; 676 s->rom_state_paddr = 0; 677 break; 678 } 679 break; 680 case 1: 681 if (kvm_enabled()) { 682 /* 683 * Disable triggering instruction in ROM by writing a NOP. 684 * 685 * We cannot do this in TCG mode as the reported IP is not 686 * accurate. 687 */ 688 pause_all_vcpus(); 689 patch_byte(cpu, env->eip - 2, 0x66); 690 patch_byte(cpu, env->eip - 1, 0x90); 691 resume_all_vcpus(); 692 } 693 694 if (s->state == VAPIC_ACTIVE) { 695 break; 696 } 697 if (update_rom_mapping(s, env, env->eip) < 0) { 698 break; 699 } 700 if (find_real_tpr_addr(s, env) < 0) { 701 break; 702 } 703 vapic_enable(s, cpu); 704 break; 705 default: 706 case 4: 707 if (!kvm_irqchip_in_kernel()) { 708 apic_poll_irq(cpu->apic_state); 709 } 710 break; 711 } 712 } 713 714 static uint64_t vapic_read(void *opaque, hwaddr addr, unsigned size) 715 { 716 return 0xffffffff; 717 } 718 719 static const MemoryRegionOps vapic_ops = { 720 .write = vapic_write, 721 .read = vapic_read, 722 .endianness = DEVICE_LITTLE_ENDIAN, 723 }; 724 725 static void vapic_realize(DeviceState *dev, Error **errp) 726 { 727 SysBusDevice *sbd = SYS_BUS_DEVICE(dev); 728 VAPICROMState *s = VAPIC(dev); 729 730 memory_region_init_io(&s->io, OBJECT(s), &vapic_ops, s, "kvmvapic", 2); 731 memory_region_add_subregion(get_system_io(), VAPIC_IO_PORT, &s->io); 732 sysbus_init_ioports(sbd, VAPIC_IO_PORT, 2); 733 734 option_rom[nb_option_roms].name = "kvmvapic.bin"; 735 option_rom[nb_option_roms].bootindex = -1; 736 nb_option_roms++; 737 } 738 739 static void do_vapic_enable(CPUState *cs, run_on_cpu_data data) 740 { 741 VAPICROMState *s = data.host_ptr; 742 X86CPU *cpu = X86_CPU(cs); 743 744 static const uint8_t enabled = 1; 745 cpu_physical_memory_write(s->vapic_paddr + offsetof(VAPICState, enabled), 746 &enabled, sizeof(enabled)); 747 apic_enable_vapic(cpu->apic_state, s->vapic_paddr); 748 s->state = VAPIC_ACTIVE; 749 } 750 751 static void vapic_vm_state_change(void *opaque, bool running, RunState state) 752 { 753 MachineState *ms = MACHINE(qdev_get_machine()); 754 VAPICROMState *s = opaque; 755 uint8_t *zero; 756 757 if (!running) { 758 return; 759 } 760 761 if (s->state == VAPIC_ACTIVE) { 762 if (ms->smp.cpus == 1) { 763 run_on_cpu(first_cpu, do_vapic_enable, RUN_ON_CPU_HOST_PTR(s)); 764 } else { 765 zero = g_malloc0(s->rom_state.vapic_size); 766 cpu_physical_memory_write(s->vapic_paddr, zero, 767 s->rom_state.vapic_size); 768 g_free(zero); 769 } 770 } 771 772 qemu_del_vm_change_state_handler(s->vmsentry); 773 s->vmsentry = NULL; 774 } 775 776 static int vapic_post_load(void *opaque, int version_id) 777 { 778 VAPICROMState *s = opaque; 779 780 /* 781 * The old implementation of qemu-kvm did not provide the state 782 * VAPIC_STANDBY. Reconstruct it. 783 */ 784 if (s->state == VAPIC_INACTIVE && s->rom_state_paddr != 0) { 785 s->state = VAPIC_STANDBY; 786 } 787 788 if (s->state != VAPIC_INACTIVE) { 789 if (vapic_prepare(s) < 0) { 790 return -1; 791 } 792 } 793 794 if (!s->vmsentry) { 795 s->vmsentry = 796 qemu_add_vm_change_state_handler(vapic_vm_state_change, s); 797 } 798 return 0; 799 } 800 801 static const VMStateDescription vmstate_handlers = { 802 .name = "kvmvapic-handlers", 803 .version_id = 1, 804 .minimum_version_id = 1, 805 .fields = (const VMStateField[]) { 806 VMSTATE_UINT32(set_tpr, VAPICHandlers), 807 VMSTATE_UINT32(set_tpr_eax, VAPICHandlers), 808 VMSTATE_UINT32_ARRAY(get_tpr, VAPICHandlers, 8), 809 VMSTATE_UINT32(get_tpr_stack, VAPICHandlers), 810 VMSTATE_END_OF_LIST() 811 } 812 }; 813 814 static const VMStateDescription vmstate_guest_rom = { 815 .name = "kvmvapic-guest-rom", 816 .version_id = 1, 817 .minimum_version_id = 1, 818 .fields = (const VMStateField[]) { 819 VMSTATE_UNUSED(8), /* signature */ 820 VMSTATE_UINT32(vaddr, GuestROMState), 821 VMSTATE_UINT32(fixup_start, GuestROMState), 822 VMSTATE_UINT32(fixup_end, GuestROMState), 823 VMSTATE_UINT32(vapic_vaddr, GuestROMState), 824 VMSTATE_UINT32(vapic_size, GuestROMState), 825 VMSTATE_UINT32(vcpu_shift, GuestROMState), 826 VMSTATE_UINT32(real_tpr_addr, GuestROMState), 827 VMSTATE_STRUCT(up, GuestROMState, 0, vmstate_handlers, VAPICHandlers), 828 VMSTATE_STRUCT(mp, GuestROMState, 0, vmstate_handlers, VAPICHandlers), 829 VMSTATE_END_OF_LIST() 830 } 831 }; 832 833 static const VMStateDescription vmstate_vapic = { 834 .name = "kvm-tpr-opt", /* compatible with qemu-kvm VAPIC */ 835 .version_id = 1, 836 .minimum_version_id = 1, 837 .post_load = vapic_post_load, 838 .fields = (const VMStateField[]) { 839 VMSTATE_STRUCT(rom_state, VAPICROMState, 0, vmstate_guest_rom, 840 GuestROMState), 841 VMSTATE_UINT32(state, VAPICROMState), 842 VMSTATE_UINT32(real_tpr_addr, VAPICROMState), 843 VMSTATE_UINT32(rom_state_vaddr, VAPICROMState), 844 VMSTATE_UINT32(vapic_paddr, VAPICROMState), 845 VMSTATE_UINT32(rom_state_paddr, VAPICROMState), 846 VMSTATE_END_OF_LIST() 847 } 848 }; 849 850 static void vapic_class_init(ObjectClass *klass, const void *data) 851 { 852 DeviceClass *dc = DEVICE_CLASS(klass); 853 854 device_class_set_legacy_reset(dc, vapic_reset); 855 dc->vmsd = &vmstate_vapic; 856 dc->realize = vapic_realize; 857 } 858 859 static const TypeInfo vapic_type = { 860 .name = TYPE_VAPIC, 861 .parent = TYPE_SYS_BUS_DEVICE, 862 .instance_size = sizeof(VAPICROMState), 863 .class_init = vapic_class_init, 864 }; 865 866 static void vapic_register(void) 867 { 868 type_register_static(&vapic_type); 869 } 870 871 type_init(vapic_register); 872