1 /* 2 * Q35 chipset based pc system emulator 3 * 4 * Copyright (c) 2003-2004 Fabrice Bellard 5 * Copyright (c) 2009, 2010 6 * Isaku Yamahata <yamahata at valinux co jp> 7 * VA Linux Systems Japan K.K. 8 * Copyright (C) 2012 Jason Baron <jbaron@redhat.com> 9 * 10 * This is based on pc.c, but heavily modified. 11 * 12 * Permission is hereby granted, free of charge, to any person obtaining a copy 13 * of this software and associated documentation files (the "Software"), to deal 14 * in the Software without restriction, including without limitation the rights 15 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 16 * copies of the Software, and to permit persons to whom the Software is 17 * furnished to do so, subject to the following conditions: 18 * 19 * The above copyright notice and this permission notice shall be included in 20 * all copies or substantial portions of the Software. 21 * 22 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 23 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 24 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 25 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 26 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 27 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN 28 * THE SOFTWARE. 29 */ 30 #include "hw/hw.h" 31 #include "hw/loader.h" 32 #include "sysemu/arch_init.h" 33 #include "hw/i2c/smbus.h" 34 #include "hw/boards.h" 35 #include "hw/timer/mc146818rtc.h" 36 #include "hw/xen/xen.h" 37 #include "sysemu/kvm.h" 38 #include "hw/kvm/clock.h" 39 #include "hw/pci-host/q35.h" 40 #include "exec/address-spaces.h" 41 #include "hw/i386/ich9.h" 42 #include "hw/i386/smbios.h" 43 #include "hw/ide/pci.h" 44 #include "hw/ide/ahci.h" 45 #include "hw/usb.h" 46 #include "hw/cpu/icc_bus.h" 47 #include "qemu/error-report.h" 48 49 /* ICH9 AHCI has 6 ports */ 50 #define MAX_SATA_PORTS 6 51 52 static bool has_acpi_build = true; 53 static bool smbios_defaults = true; 54 static bool smbios_legacy_mode; 55 /* Make sure that guest addresses aligned at 1Gbyte boundaries get mapped to 56 * host addresses aligned at 1Gbyte boundaries. This way we can use 1GByte 57 * pages in the host. 58 */ 59 static bool gigabyte_align = true; 60 static bool has_reserved_memory = true; 61 62 /* PC hardware initialisation */ 63 static void pc_q35_init(MachineState *machine) 64 { 65 PCMachineState *pc_machine = PC_MACHINE(machine); 66 ram_addr_t below_4g_mem_size, above_4g_mem_size; 67 Q35PCIHost *q35_host; 68 PCIHostState *phb; 69 PCIBus *host_bus; 70 PCIDevice *lpc; 71 BusState *idebus[MAX_SATA_PORTS]; 72 ISADevice *rtc_state; 73 ISADevice *floppy; 74 MemoryRegion *pci_memory; 75 MemoryRegion *rom_memory; 76 MemoryRegion *ram_memory; 77 GSIState *gsi_state; 78 ISABus *isa_bus; 79 int pci_enabled = 1; 80 qemu_irq *cpu_irq; 81 qemu_irq *gsi; 82 qemu_irq *i8259; 83 int i; 84 ICH9LPCState *ich9_lpc; 85 PCIDevice *ahci; 86 DeviceState *icc_bridge; 87 PcGuestInfo *guest_info; 88 ram_addr_t lowmem; 89 DriveInfo *hd[MAX_SATA_PORTS]; 90 91 /* Check whether RAM fits below 4G (leaving 1/2 GByte for IO memory 92 * and 256 Mbytes for PCI Express Enhanced Configuration Access Mapping 93 * also known as MMCFG). 94 * If it doesn't, we need to split it in chunks below and above 4G. 95 * In any case, try to make sure that guest addresses aligned at 96 * 1G boundaries get mapped to host addresses aligned at 1G boundaries. 97 * For old machine types, use whatever split we used historically to avoid 98 * breaking migration. 99 */ 100 if (machine->ram_size >= 0xb0000000) { 101 lowmem = gigabyte_align ? 0x80000000 : 0xb0000000; 102 } else { 103 lowmem = 0xb0000000; 104 } 105 106 /* Handle the machine opt max-ram-below-4g. It is basically doing 107 * min(qemu limit, user limit). 108 */ 109 if (lowmem > pc_machine->max_ram_below_4g) { 110 lowmem = pc_machine->max_ram_below_4g; 111 if (machine->ram_size - lowmem > lowmem && 112 lowmem & ((1ULL << 30) - 1)) { 113 error_report("Warning: Large machine and max_ram_below_4g(%"PRIu64 114 ") not a multiple of 1G; possible bad performance.", 115 pc_machine->max_ram_below_4g); 116 } 117 } 118 119 if (machine->ram_size >= lowmem) { 120 above_4g_mem_size = machine->ram_size - lowmem; 121 below_4g_mem_size = lowmem; 122 } else { 123 above_4g_mem_size = 0; 124 below_4g_mem_size = machine->ram_size; 125 } 126 127 if (xen_enabled() && xen_hvm_init(&below_4g_mem_size, &above_4g_mem_size, 128 &ram_memory) != 0) { 129 fprintf(stderr, "xen hardware virtual machine initialisation failed\n"); 130 exit(1); 131 } 132 133 icc_bridge = qdev_create(NULL, TYPE_ICC_BRIDGE); 134 object_property_add_child(qdev_get_machine(), "icc-bridge", 135 OBJECT(icc_bridge), NULL); 136 137 pc_cpus_init(machine->cpu_model, icc_bridge); 138 pc_acpi_init("q35-acpi-dsdt.aml"); 139 140 kvmclock_create(); 141 142 /* pci enabled */ 143 if (pci_enabled) { 144 pci_memory = g_new(MemoryRegion, 1); 145 memory_region_init(pci_memory, NULL, "pci", UINT64_MAX); 146 rom_memory = pci_memory; 147 } else { 148 pci_memory = NULL; 149 rom_memory = get_system_memory(); 150 } 151 152 guest_info = pc_guest_info_init(below_4g_mem_size, above_4g_mem_size); 153 guest_info->isapc_ram_fw = false; 154 guest_info->has_acpi_build = has_acpi_build; 155 guest_info->has_reserved_memory = has_reserved_memory; 156 157 /* Migration was not supported in 2.0 for Q35, so do not bother 158 * with this hack (see hw/i386/acpi-build.c). 159 */ 160 guest_info->legacy_acpi_table_size = 0; 161 162 if (smbios_defaults) { 163 MachineClass *mc = MACHINE_GET_CLASS(machine); 164 /* These values are guest ABI, do not change */ 165 smbios_set_defaults("QEMU", "Standard PC (Q35 + ICH9, 2009)", 166 mc->name, smbios_legacy_mode); 167 } 168 169 /* allocate ram and load rom/bios */ 170 if (!xen_enabled()) { 171 pc_memory_init(machine, get_system_memory(), 172 below_4g_mem_size, above_4g_mem_size, 173 rom_memory, &ram_memory, guest_info); 174 } 175 176 /* irq lines */ 177 gsi_state = g_malloc0(sizeof(*gsi_state)); 178 if (kvm_irqchip_in_kernel()) { 179 kvm_pc_setup_irq_routing(pci_enabled); 180 gsi = qemu_allocate_irqs(kvm_pc_gsi_handler, gsi_state, 181 GSI_NUM_PINS); 182 } else { 183 gsi = qemu_allocate_irqs(gsi_handler, gsi_state, GSI_NUM_PINS); 184 } 185 186 /* create pci host bus */ 187 q35_host = Q35_HOST_DEVICE(qdev_create(NULL, TYPE_Q35_HOST_DEVICE)); 188 189 object_property_add_child(qdev_get_machine(), "q35", OBJECT(q35_host), NULL); 190 q35_host->mch.ram_memory = ram_memory; 191 q35_host->mch.pci_address_space = pci_memory; 192 q35_host->mch.system_memory = get_system_memory(); 193 q35_host->mch.address_space_io = get_system_io(); 194 q35_host->mch.below_4g_mem_size = below_4g_mem_size; 195 q35_host->mch.above_4g_mem_size = above_4g_mem_size; 196 q35_host->mch.guest_info = guest_info; 197 /* pci */ 198 qdev_init_nofail(DEVICE(q35_host)); 199 phb = PCI_HOST_BRIDGE(q35_host); 200 host_bus = phb->bus; 201 /* create ISA bus */ 202 lpc = pci_create_simple_multifunction(host_bus, PCI_DEVFN(ICH9_LPC_DEV, 203 ICH9_LPC_FUNC), true, 204 TYPE_ICH9_LPC_DEVICE); 205 206 object_property_add_link(OBJECT(machine), PC_MACHINE_ACPI_DEVICE_PROP, 207 TYPE_HOTPLUG_HANDLER, 208 (Object **)&pc_machine->acpi_dev, 209 object_property_allow_set_link, 210 OBJ_PROP_LINK_UNREF_ON_RELEASE, &error_abort); 211 object_property_set_link(OBJECT(machine), OBJECT(lpc), 212 PC_MACHINE_ACPI_DEVICE_PROP, &error_abort); 213 214 ich9_lpc = ICH9_LPC_DEVICE(lpc); 215 ich9_lpc->pic = gsi; 216 ich9_lpc->ioapic = gsi_state->ioapic_irq; 217 pci_bus_irqs(host_bus, ich9_lpc_set_irq, ich9_lpc_map_irq, ich9_lpc, 218 ICH9_LPC_NB_PIRQS); 219 pci_bus_set_route_irq_fn(host_bus, ich9_route_intx_pin_to_irq); 220 isa_bus = ich9_lpc->isa_bus; 221 222 /*end early*/ 223 isa_bus_irqs(isa_bus, gsi); 224 225 if (kvm_irqchip_in_kernel()) { 226 i8259 = kvm_i8259_init(isa_bus); 227 } else if (xen_enabled()) { 228 i8259 = xen_interrupt_controller_init(); 229 } else { 230 cpu_irq = pc_allocate_cpu_irq(); 231 i8259 = i8259_init(isa_bus, cpu_irq[0]); 232 } 233 234 for (i = 0; i < ISA_NUM_IRQS; i++) { 235 gsi_state->i8259_irq[i] = i8259[i]; 236 } 237 if (pci_enabled) { 238 ioapic_init_gsi(gsi_state, "q35"); 239 } 240 qdev_init_nofail(icc_bridge); 241 242 pc_register_ferr_irq(gsi[13]); 243 244 /* init basic PC hardware */ 245 pc_basic_device_init(isa_bus, gsi, &rtc_state, &floppy, 246 !pc_machine->vmport, 0xff0104); 247 248 /* connect pm stuff to lpc */ 249 ich9_lpc_pm_init(lpc); 250 251 /* ahci and SATA device, for q35 1 ahci controller is built-in */ 252 ahci = pci_create_simple_multifunction(host_bus, 253 PCI_DEVFN(ICH9_SATA1_DEV, 254 ICH9_SATA1_FUNC), 255 true, "ich9-ahci"); 256 idebus[0] = qdev_get_child_bus(&ahci->qdev, "ide.0"); 257 idebus[1] = qdev_get_child_bus(&ahci->qdev, "ide.1"); 258 g_assert(MAX_SATA_PORTS == ICH_AHCI(ahci)->ahci.ports); 259 ide_drive_get(hd, ICH_AHCI(ahci)->ahci.ports); 260 ahci_ide_create_devs(ahci, hd); 261 262 if (usb_enabled(false)) { 263 /* Should we create 6 UHCI according to ich9 spec? */ 264 ehci_create_ich9_with_companions(host_bus, 0x1d); 265 } 266 267 /* TODO: Populate SPD eeprom data. */ 268 smbus_eeprom_init(ich9_smb_init(host_bus, 269 PCI_DEVFN(ICH9_SMB_DEV, ICH9_SMB_FUNC), 270 0xb100), 271 8, NULL, 0); 272 273 pc_cmos_init(below_4g_mem_size, above_4g_mem_size, machine->boot_order, 274 floppy, idebus[0], idebus[1], rtc_state); 275 276 /* the rest devices to which pci devfn is automatically assigned */ 277 pc_vga_init(isa_bus, host_bus); 278 pc_nic_init(isa_bus, host_bus); 279 if (pci_enabled) { 280 pc_pci_device_init(host_bus); 281 } 282 } 283 284 static void pc_compat_2_0(MachineState *machine) 285 { 286 smbios_legacy_mode = true; 287 has_reserved_memory = false; 288 pc_set_legacy_acpi_data_size(); 289 } 290 291 static void pc_compat_1_7(MachineState *machine) 292 { 293 pc_compat_2_0(machine); 294 smbios_defaults = false; 295 gigabyte_align = false; 296 option_rom_has_mr = true; 297 x86_cpu_compat_disable_kvm_features(FEAT_1_ECX, CPUID_EXT_X2APIC); 298 } 299 300 static void pc_compat_1_6(MachineState *machine) 301 { 302 pc_compat_1_7(machine); 303 rom_file_has_mr = false; 304 has_acpi_build = false; 305 } 306 307 static void pc_compat_1_5(MachineState *machine) 308 { 309 pc_compat_1_6(machine); 310 } 311 312 static void pc_compat_1_4(MachineState *machine) 313 { 314 pc_compat_1_5(machine); 315 x86_cpu_compat_set_features("n270", FEAT_1_ECX, 0, CPUID_EXT_MOVBE); 316 x86_cpu_compat_set_features("Westmere", FEAT_1_ECX, 0, CPUID_EXT_PCLMULQDQ); 317 } 318 319 static void pc_q35_init_2_0(MachineState *machine) 320 { 321 pc_compat_2_0(machine); 322 pc_q35_init(machine); 323 } 324 325 static void pc_q35_init_1_7(MachineState *machine) 326 { 327 pc_compat_1_7(machine); 328 pc_q35_init(machine); 329 } 330 331 static void pc_q35_init_1_6(MachineState *machine) 332 { 333 pc_compat_1_6(machine); 334 pc_q35_init(machine); 335 } 336 337 static void pc_q35_init_1_5(MachineState *machine) 338 { 339 pc_compat_1_5(machine); 340 pc_q35_init(machine); 341 } 342 343 static void pc_q35_init_1_4(MachineState *machine) 344 { 345 pc_compat_1_4(machine); 346 pc_q35_init(machine); 347 } 348 349 #define PC_Q35_MACHINE_OPTIONS \ 350 PC_DEFAULT_MACHINE_OPTIONS, \ 351 .desc = "Standard PC (Q35 + ICH9, 2009)", \ 352 .hot_add_cpu = pc_hot_add_cpu, \ 353 .units_per_default_bus = 1 354 355 #define PC_Q35_2_2_MACHINE_OPTIONS \ 356 PC_Q35_MACHINE_OPTIONS, \ 357 .default_machine_opts = "firmware=bios-256k.bin" 358 359 static QEMUMachine pc_q35_machine_v2_2 = { 360 PC_Q35_2_2_MACHINE_OPTIONS, 361 .name = "pc-q35-2.2", 362 .alias = "q35", 363 .init = pc_q35_init, 364 }; 365 366 #define PC_Q35_2_1_MACHINE_OPTIONS PC_Q35_2_2_MACHINE_OPTIONS 367 368 static QEMUMachine pc_q35_machine_v2_1 = { 369 PC_Q35_2_1_MACHINE_OPTIONS, 370 .name = "pc-q35-2.1", 371 .init = pc_q35_init, 372 .compat_props = (GlobalProperty[]) { 373 PC_COMPAT_2_1, 374 { /* end of list */ } 375 }, 376 }; 377 378 #define PC_Q35_2_0_MACHINE_OPTIONS PC_Q35_2_1_MACHINE_OPTIONS 379 380 static QEMUMachine pc_q35_machine_v2_0 = { 381 PC_Q35_2_0_MACHINE_OPTIONS, 382 .name = "pc-q35-2.0", 383 .init = pc_q35_init_2_0, 384 .compat_props = (GlobalProperty[]) { 385 PC_COMPAT_2_0, 386 { /* end of list */ } 387 }, 388 }; 389 390 #define PC_Q35_1_7_MACHINE_OPTIONS PC_Q35_MACHINE_OPTIONS 391 392 static QEMUMachine pc_q35_machine_v1_7 = { 393 PC_Q35_1_7_MACHINE_OPTIONS, 394 .name = "pc-q35-1.7", 395 .init = pc_q35_init_1_7, 396 .compat_props = (GlobalProperty[]) { 397 PC_COMPAT_1_7, 398 { /* end of list */ } 399 }, 400 }; 401 402 #define PC_Q35_1_6_MACHINE_OPTIONS PC_Q35_MACHINE_OPTIONS 403 404 static QEMUMachine pc_q35_machine_v1_6 = { 405 PC_Q35_1_6_MACHINE_OPTIONS, 406 .name = "pc-q35-1.6", 407 .init = pc_q35_init_1_6, 408 .compat_props = (GlobalProperty[]) { 409 PC_COMPAT_1_6, 410 { /* end of list */ } 411 }, 412 }; 413 414 static QEMUMachine pc_q35_machine_v1_5 = { 415 PC_Q35_1_6_MACHINE_OPTIONS, 416 .name = "pc-q35-1.5", 417 .init = pc_q35_init_1_5, 418 .compat_props = (GlobalProperty[]) { 419 PC_COMPAT_1_5, 420 { /* end of list */ } 421 }, 422 }; 423 424 #define PC_Q35_1_4_MACHINE_OPTIONS \ 425 PC_Q35_1_6_MACHINE_OPTIONS, \ 426 .hot_add_cpu = NULL 427 428 static QEMUMachine pc_q35_machine_v1_4 = { 429 PC_Q35_1_4_MACHINE_OPTIONS, 430 .name = "pc-q35-1.4", 431 .init = pc_q35_init_1_4, 432 .compat_props = (GlobalProperty[]) { 433 PC_COMPAT_1_4, 434 { /* end of list */ } 435 }, 436 }; 437 438 static void pc_q35_machine_init(void) 439 { 440 qemu_register_pc_machine(&pc_q35_machine_v2_2); 441 qemu_register_pc_machine(&pc_q35_machine_v2_1); 442 qemu_register_pc_machine(&pc_q35_machine_v2_0); 443 qemu_register_pc_machine(&pc_q35_machine_v1_7); 444 qemu_register_pc_machine(&pc_q35_machine_v1_6); 445 qemu_register_pc_machine(&pc_q35_machine_v1_5); 446 qemu_register_pc_machine(&pc_q35_machine_v1_4); 447 } 448 449 machine_init(pc_q35_machine_init); 450