1 /* 2 * Q35 chipset based pc system emulator 3 * 4 * Copyright (c) 2003-2004 Fabrice Bellard 5 * Copyright (c) 2009, 2010 6 * Isaku Yamahata <yamahata at valinux co jp> 7 * VA Linux Systems Japan K.K. 8 * Copyright (C) 2012 Jason Baron <jbaron@redhat.com> 9 * 10 * This is based on pc.c, but heavily modified. 11 * 12 * Permission is hereby granted, free of charge, to any person obtaining a copy 13 * of this software and associated documentation files (the "Software"), to deal 14 * in the Software without restriction, including without limitation the rights 15 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 16 * copies of the Software, and to permit persons to whom the Software is 17 * furnished to do so, subject to the following conditions: 18 * 19 * The above copyright notice and this permission notice shall be included in 20 * all copies or substantial portions of the Software. 21 * 22 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 23 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 24 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 25 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 26 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 27 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN 28 * THE SOFTWARE. 29 */ 30 31 #include "qemu/osdep.h" 32 #include "qemu/units.h" 33 #include "hw/acpi/acpi.h" 34 #include "hw/char/parallel-isa.h" 35 #include "hw/loader.h" 36 #include "hw/i2c/smbus_eeprom.h" 37 #include "hw/rtc/mc146818rtc.h" 38 #include "system/tcg.h" 39 #include "system/kvm.h" 40 #include "hw/i386/kvm/clock.h" 41 #include "hw/pci-host/q35.h" 42 #include "hw/pci/pcie_port.h" 43 #include "hw/qdev-properties.h" 44 #include "hw/i386/x86.h" 45 #include "hw/i386/pc.h" 46 #include "hw/i386/amd_iommu.h" 47 #include "hw/i386/intel_iommu.h" 48 #include "hw/virtio/virtio-iommu.h" 49 #include "hw/display/ramfb.h" 50 #include "hw/ide/pci.h" 51 #include "hw/ide/ahci-pci.h" 52 #include "hw/intc/ioapic.h" 53 #include "hw/southbridge/ich9.h" 54 #include "hw/usb.h" 55 #include "hw/usb/hcd-uhci.h" 56 #include "qapi/error.h" 57 #include "qemu/error-report.h" 58 #include "system/numa.h" 59 #include "hw/hyperv/vmbus-bridge.h" 60 #include "hw/mem/nvdimm.h" 61 #include "hw/uefi/var-service-api.h" 62 #include "hw/i386/acpi-build.h" 63 #include "target/i386/cpu.h" 64 65 /* ICH9 AHCI has 6 ports */ 66 #define MAX_SATA_PORTS 6 67 68 static GlobalProperty pc_q35_compat_defaults[] = { 69 { TYPE_VIRTIO_IOMMU_PCI, "aw-bits", "39" }, 70 }; 71 static const size_t pc_q35_compat_defaults_len = 72 G_N_ELEMENTS(pc_q35_compat_defaults); 73 74 struct ehci_companions { 75 const char *name; 76 int func; 77 int port; 78 }; 79 80 static const struct ehci_companions ich9_1d[] = { 81 { .name = TYPE_ICH9_USB_UHCI(1), .func = 0, .port = 0 }, 82 { .name = TYPE_ICH9_USB_UHCI(2), .func = 1, .port = 2 }, 83 { .name = TYPE_ICH9_USB_UHCI(3), .func = 2, .port = 4 }, 84 }; 85 86 static const struct ehci_companions ich9_1a[] = { 87 { .name = TYPE_ICH9_USB_UHCI(4), .func = 0, .port = 0 }, 88 { .name = TYPE_ICH9_USB_UHCI(5), .func = 1, .port = 2 }, 89 { .name = TYPE_ICH9_USB_UHCI(6), .func = 2, .port = 4 }, 90 }; 91 92 static int ehci_create_ich9_with_companions(PCIBus *bus, int slot) 93 { 94 const struct ehci_companions *comp; 95 PCIDevice *ehci, *uhci; 96 BusState *usbbus; 97 const char *name; 98 int i; 99 100 switch (slot) { 101 case 0x1d: 102 name = "ich9-usb-ehci1"; 103 comp = ich9_1d; 104 break; 105 case 0x1a: 106 name = "ich9-usb-ehci2"; 107 comp = ich9_1a; 108 break; 109 default: 110 return -1; 111 } 112 113 ehci = pci_new_multifunction(PCI_DEVFN(slot, 7), name); 114 pci_realize_and_unref(ehci, bus, &error_fatal); 115 usbbus = QLIST_FIRST(&ehci->qdev.child_bus); 116 117 for (i = 0; i < 3; i++) { 118 uhci = pci_new_multifunction(PCI_DEVFN(slot, comp[i].func), 119 comp[i].name); 120 qdev_prop_set_string(&uhci->qdev, "masterbus", usbbus->name); 121 qdev_prop_set_uint32(&uhci->qdev, "firstport", comp[i].port); 122 pci_realize_and_unref(uhci, bus, &error_fatal); 123 } 124 return 0; 125 } 126 127 /* PC hardware initialisation */ 128 static void pc_q35_init(MachineState *machine) 129 { 130 PCMachineState *pcms = PC_MACHINE(machine); 131 PCMachineClass *pcmc = PC_MACHINE_GET_CLASS(pcms); 132 X86MachineState *x86ms = X86_MACHINE(machine); 133 Object *phb; 134 PCIDevice *lpc; 135 DeviceState *lpc_dev; 136 MemoryRegion *system_memory = get_system_memory(); 137 MemoryRegion *system_io = get_system_io(); 138 MemoryRegion *pci_memory = g_new(MemoryRegion, 1); 139 GSIState *gsi_state; 140 ISABus *isa_bus; 141 int i; 142 ram_addr_t lowmem; 143 DriveInfo *hd[MAX_SATA_PORTS]; 144 MachineClass *mc = MACHINE_GET_CLASS(machine); 145 bool acpi_pcihp; 146 bool keep_pci_slot_hpc; 147 uint64_t pci_hole64_size = 0; 148 149 assert(pcmc->pci_enabled); 150 151 /* Check whether RAM fits below 4G (leaving 1/2 GByte for IO memory 152 * and 256 Mbytes for PCI Express Enhanced Configuration Access Mapping 153 * also known as MMCFG). 154 * If it doesn't, we need to split it in chunks below and above 4G. 155 * In any case, try to make sure that guest addresses aligned at 156 * 1G boundaries get mapped to host addresses aligned at 1G boundaries. 157 */ 158 if (machine->ram_size >= 0xb0000000) { 159 lowmem = 0x80000000; 160 } else { 161 lowmem = 0xb0000000; 162 } 163 164 /* Handle the machine opt max-ram-below-4g. It is basically doing 165 * min(qemu limit, user limit). 166 */ 167 if (!pcms->max_ram_below_4g) { 168 pcms->max_ram_below_4g = 4 * GiB; 169 } 170 if (lowmem > pcms->max_ram_below_4g) { 171 lowmem = pcms->max_ram_below_4g; 172 if (machine->ram_size - lowmem > lowmem && 173 lowmem & (1 * GiB - 1)) { 174 warn_report("There is possibly poor performance as the ram size " 175 " (0x%" PRIx64 ") is more then twice the size of" 176 " max-ram-below-4g (%"PRIu64") and" 177 " max-ram-below-4g is not a multiple of 1G.", 178 (uint64_t)machine->ram_size, pcms->max_ram_below_4g); 179 } 180 } 181 182 if (machine->ram_size >= lowmem) { 183 x86ms->above_4g_mem_size = machine->ram_size - lowmem; 184 x86ms->below_4g_mem_size = lowmem; 185 } else { 186 x86ms->above_4g_mem_size = 0; 187 x86ms->below_4g_mem_size = machine->ram_size; 188 } 189 190 pc_machine_init_sgx_epc(pcms); 191 x86_cpus_init(x86ms, pcmc->default_cpu_version); 192 193 if (kvm_enabled()) { 194 kvmclock_create(pcmc->kvmclock_create_always); 195 } 196 197 /* create pci host bus */ 198 phb = OBJECT(qdev_new(TYPE_Q35_HOST_DEVICE)); 199 200 pci_hole64_size = object_property_get_uint(phb, 201 PCI_HOST_PROP_PCI_HOLE64_SIZE, 202 &error_abort); 203 204 /* allocate ram and load rom/bios */ 205 memory_region_init(pci_memory, NULL, "pci", UINT64_MAX); 206 pc_memory_init(pcms, system_memory, pci_memory, pci_hole64_size); 207 208 object_property_add_child(OBJECT(machine), "q35", phb); 209 object_property_set_link(phb, PCI_HOST_PROP_RAM_MEM, 210 OBJECT(machine->ram), NULL); 211 object_property_set_link(phb, PCI_HOST_PROP_PCI_MEM, 212 OBJECT(pci_memory), NULL); 213 object_property_set_link(phb, PCI_HOST_PROP_SYSTEM_MEM, 214 OBJECT(system_memory), NULL); 215 object_property_set_link(phb, PCI_HOST_PROP_IO_MEM, 216 OBJECT(system_io), NULL); 217 object_property_set_int(phb, PCI_HOST_BELOW_4G_MEM_SIZE, 218 x86ms->below_4g_mem_size, NULL); 219 object_property_set_int(phb, PCI_HOST_ABOVE_4G_MEM_SIZE, 220 x86ms->above_4g_mem_size, NULL); 221 object_property_set_bool(phb, PCI_HOST_BYPASS_IOMMU, 222 pcms->default_bus_bypass_iommu, NULL); 223 object_property_set_bool(phb, PCI_HOST_PROP_SMM_RANGES, 224 x86_machine_is_smm_enabled(x86ms), NULL); 225 sysbus_realize_and_unref(SYS_BUS_DEVICE(phb), &error_fatal); 226 227 /* pci */ 228 pcms->pcibus = PCI_BUS(qdev_get_child_bus(DEVICE(phb), "pcie.0")); 229 230 /* irq lines */ 231 gsi_state = pc_gsi_create(&x86ms->gsi, true); 232 233 /* create ISA bus */ 234 lpc = pci_new_multifunction(PCI_DEVFN(ICH9_LPC_DEV, ICH9_LPC_FUNC), 235 TYPE_ICH9_LPC_DEVICE); 236 lpc_dev = DEVICE(lpc); 237 qdev_prop_set_bit(lpc_dev, "smm-enabled", 238 x86_machine_is_smm_enabled(x86ms)); 239 for (i = 0; i < IOAPIC_NUM_PINS; i++) { 240 qdev_connect_gpio_out_named(lpc_dev, ICH9_GPIO_GSI, i, x86ms->gsi[i]); 241 } 242 pci_realize_and_unref(lpc, pcms->pcibus, &error_fatal); 243 244 x86ms->rtc = ISA_DEVICE(object_resolve_path_component(OBJECT(lpc), "rtc")); 245 246 object_property_add_link(OBJECT(machine), PC_MACHINE_ACPI_DEVICE_PROP, 247 TYPE_HOTPLUG_HANDLER, 248 (Object **)&x86ms->acpi_dev, 249 object_property_allow_set_link, 250 OBJ_PROP_LINK_STRONG); 251 object_property_set_link(OBJECT(machine), PC_MACHINE_ACPI_DEVICE_PROP, 252 OBJECT(lpc), &error_abort); 253 254 acpi_pcihp = object_property_get_bool(OBJECT(lpc), 255 ACPI_PM_PROP_ACPI_PCIHP_BRIDGE, 256 NULL); 257 258 keep_pci_slot_hpc = object_property_get_bool(OBJECT(lpc), 259 "x-keep-pci-slot-hpc", 260 NULL); 261 262 if (!keep_pci_slot_hpc && acpi_pcihp) { 263 object_register_sugar_prop(TYPE_PCIE_SLOT, 264 "x-do-not-expose-native-hotplug-cap", 265 "true", true); 266 } 267 268 isa_bus = ISA_BUS(qdev_get_child_bus(lpc_dev, "isa.0")); 269 270 if (x86ms->pic == ON_OFF_AUTO_ON || x86ms->pic == ON_OFF_AUTO_AUTO) { 271 pc_i8259_create(isa_bus, gsi_state->i8259_irq); 272 } 273 274 ioapic_init_gsi(gsi_state, OBJECT(phb)); 275 276 if (tcg_enabled()) { 277 x86_register_ferr_irq(x86ms->gsi[13]); 278 } 279 280 /* init basic PC hardware */ 281 pc_basic_device_init(pcms, isa_bus, x86ms->gsi, x86ms->rtc, !mc->no_floppy, 282 0xff0104); 283 284 if (pcms->sata_enabled) { 285 PCIDevice *pdev; 286 AHCIPCIState *ich9; 287 288 /* ahci and SATA device, for q35 1 ahci controller is built-in */ 289 pdev = pci_create_simple_multifunction(pcms->pcibus, 290 PCI_DEVFN(ICH9_SATA1_DEV, 291 ICH9_SATA1_FUNC), 292 "ich9-ahci"); 293 ich9 = ICH9_AHCI(pdev); 294 pcms->idebus[0] = qdev_get_child_bus(DEVICE(pdev), "ide.0"); 295 pcms->idebus[1] = qdev_get_child_bus(DEVICE(pdev), "ide.1"); 296 g_assert(MAX_SATA_PORTS == ich9->ahci.ports); 297 ide_drive_get(hd, ich9->ahci.ports); 298 ahci_ide_create_devs(&ich9->ahci, hd); 299 } 300 301 if (machine_usb(machine)) { 302 /* Should we create 6 UHCI according to ich9 spec? */ 303 ehci_create_ich9_with_companions(pcms->pcibus, 0x1d); 304 } 305 306 if (pcms->smbus_enabled) { 307 PCIDevice *smb; 308 309 /* TODO: Populate SPD eeprom data. */ 310 smb = pci_create_simple_multifunction(pcms->pcibus, 311 PCI_DEVFN(ICH9_SMB_DEV, 312 ICH9_SMB_FUNC), 313 TYPE_ICH9_SMB_DEVICE); 314 pcms->smbus = I2C_BUS(qdev_get_child_bus(DEVICE(smb), "i2c")); 315 316 smbus_eeprom_init(pcms->smbus, 8, NULL, 0); 317 } 318 319 /* the rest devices to which pci devfn is automatically assigned */ 320 pc_vga_init(isa_bus, pcms->pcibus); 321 pc_nic_init(pcmc, isa_bus, pcms->pcibus); 322 323 if (machine->nvdimms_state->is_enabled) { 324 nvdimm_init_acpi_state(machine->nvdimms_state, system_io, 325 x86_nvdimm_acpi_dsmio, 326 x86ms->fw_cfg, OBJECT(pcms)); 327 } 328 } 329 330 #define DEFINE_Q35_MACHINE(major, minor) \ 331 DEFINE_PC_VER_MACHINE(pc_q35, "pc-q35", pc_q35_init, false, NULL, major, minor); 332 333 #define DEFINE_Q35_MACHINE_AS_LATEST(major, minor) \ 334 DEFINE_PC_VER_MACHINE(pc_q35, "pc-q35", pc_q35_init, false, "q35", major, minor); 335 336 #define DEFINE_Q35_MACHINE_BUGFIX(major, minor, micro) \ 337 DEFINE_PC_VER_MACHINE(pc_q35, "pc-q35", pc_q35_init, false, NULL, major, minor, micro); 338 339 static void pc_q35_machine_options(MachineClass *m) 340 { 341 PCMachineClass *pcmc = PC_MACHINE_CLASS(m); 342 pcmc->pci_root_uid = 0; 343 pcmc->default_cpu_version = 1; 344 345 m->family = "pc_q35"; 346 m->desc = "Standard PC (Q35 + ICH9, 2009)"; 347 m->units_per_default_bus = 1; 348 m->default_machine_opts = "firmware=bios-256k.bin"; 349 m->default_display = "std"; 350 m->default_nic = "e1000e"; 351 m->default_kernel_irqchip_split = false; 352 m->no_floppy = 1; 353 m->max_cpus = 4096; 354 m->no_parallel = !module_object_class_by_name(TYPE_ISA_PARALLEL); 355 machine_class_allow_dynamic_sysbus_dev(m, TYPE_AMD_IOMMU_DEVICE); 356 machine_class_allow_dynamic_sysbus_dev(m, TYPE_INTEL_IOMMU_DEVICE); 357 machine_class_allow_dynamic_sysbus_dev(m, TYPE_RAMFB_DEVICE); 358 machine_class_allow_dynamic_sysbus_dev(m, TYPE_VMBUS_BRIDGE); 359 machine_class_allow_dynamic_sysbus_dev(m, TYPE_UEFI_VARS_X64); 360 compat_props_add(m->compat_props, 361 pc_q35_compat_defaults, pc_q35_compat_defaults_len); 362 } 363 364 static void pc_q35_machine_10_0_options(MachineClass *m) 365 { 366 pc_q35_machine_options(m); 367 } 368 369 DEFINE_Q35_MACHINE_AS_LATEST(10, 0); 370 371 static void pc_q35_machine_9_2_options(MachineClass *m) 372 { 373 pc_q35_machine_10_0_options(m); 374 compat_props_add(m->compat_props, hw_compat_9_2, hw_compat_9_2_len); 375 compat_props_add(m->compat_props, pc_compat_9_2, pc_compat_9_2_len); 376 } 377 378 DEFINE_Q35_MACHINE(9, 2); 379 380 static void pc_q35_machine_9_1_options(MachineClass *m) 381 { 382 pc_q35_machine_9_2_options(m); 383 compat_props_add(m->compat_props, hw_compat_9_1, hw_compat_9_1_len); 384 compat_props_add(m->compat_props, pc_compat_9_1, pc_compat_9_1_len); 385 } 386 387 DEFINE_Q35_MACHINE(9, 1); 388 389 static void pc_q35_machine_9_0_options(MachineClass *m) 390 { 391 PCMachineClass *pcmc = PC_MACHINE_CLASS(m); 392 pc_q35_machine_9_1_options(m); 393 m->smbios_memory_device_size = 16 * GiB; 394 compat_props_add(m->compat_props, hw_compat_9_0, hw_compat_9_0_len); 395 compat_props_add(m->compat_props, pc_compat_9_0, pc_compat_9_0_len); 396 pcmc->isa_bios_alias = false; 397 } 398 399 DEFINE_Q35_MACHINE(9, 0); 400 401 static void pc_q35_machine_8_2_options(MachineClass *m) 402 { 403 PCMachineClass *pcmc = PC_MACHINE_CLASS(m); 404 pc_q35_machine_9_0_options(m); 405 m->max_cpus = 1024; 406 compat_props_add(m->compat_props, hw_compat_8_2, hw_compat_8_2_len); 407 compat_props_add(m->compat_props, pc_compat_8_2, pc_compat_8_2_len); 408 /* For pc-q35-8.2 and 8.1, use SMBIOS 3.X by default */ 409 pcmc->default_smbios_ep_type = SMBIOS_ENTRY_POINT_TYPE_64; 410 } 411 412 DEFINE_Q35_MACHINE(8, 2); 413 414 static void pc_q35_machine_8_1_options(MachineClass *m) 415 { 416 PCMachineClass *pcmc = PC_MACHINE_CLASS(m); 417 pc_q35_machine_8_2_options(m); 418 pcmc->broken_32bit_mem_addr_check = true; 419 compat_props_add(m->compat_props, hw_compat_8_1, hw_compat_8_1_len); 420 compat_props_add(m->compat_props, pc_compat_8_1, pc_compat_8_1_len); 421 } 422 423 DEFINE_Q35_MACHINE(8, 1); 424 425 static void pc_q35_machine_8_0_options(MachineClass *m) 426 { 427 PCMachineClass *pcmc = PC_MACHINE_CLASS(m); 428 429 pc_q35_machine_8_1_options(m); 430 compat_props_add(m->compat_props, hw_compat_8_0, hw_compat_8_0_len); 431 compat_props_add(m->compat_props, pc_compat_8_0, pc_compat_8_0_len); 432 433 /* For pc-q35-8.0 and older, use SMBIOS 2.8 by default */ 434 pcmc->default_smbios_ep_type = SMBIOS_ENTRY_POINT_TYPE_32; 435 m->max_cpus = 288; 436 } 437 438 DEFINE_Q35_MACHINE(8, 0); 439 440 static void pc_q35_machine_7_2_options(MachineClass *m) 441 { 442 pc_q35_machine_8_0_options(m); 443 compat_props_add(m->compat_props, hw_compat_7_2, hw_compat_7_2_len); 444 compat_props_add(m->compat_props, pc_compat_7_2, pc_compat_7_2_len); 445 } 446 447 DEFINE_Q35_MACHINE(7, 2); 448 449 static void pc_q35_machine_7_1_options(MachineClass *m) 450 { 451 pc_q35_machine_7_2_options(m); 452 compat_props_add(m->compat_props, hw_compat_7_1, hw_compat_7_1_len); 453 compat_props_add(m->compat_props, pc_compat_7_1, pc_compat_7_1_len); 454 } 455 456 DEFINE_Q35_MACHINE(7, 1); 457 458 static void pc_q35_machine_7_0_options(MachineClass *m) 459 { 460 PCMachineClass *pcmc = PC_MACHINE_CLASS(m); 461 pc_q35_machine_7_1_options(m); 462 pcmc->enforce_amd_1tb_hole = false; 463 compat_props_add(m->compat_props, hw_compat_7_0, hw_compat_7_0_len); 464 compat_props_add(m->compat_props, pc_compat_7_0, pc_compat_7_0_len); 465 } 466 467 DEFINE_Q35_MACHINE(7, 0); 468 469 static void pc_q35_machine_6_2_options(MachineClass *m) 470 { 471 pc_q35_machine_7_0_options(m); 472 compat_props_add(m->compat_props, hw_compat_6_2, hw_compat_6_2_len); 473 compat_props_add(m->compat_props, pc_compat_6_2, pc_compat_6_2_len); 474 } 475 476 DEFINE_Q35_MACHINE(6, 2); 477 478 static void pc_q35_machine_6_1_options(MachineClass *m) 479 { 480 pc_q35_machine_6_2_options(m); 481 compat_props_add(m->compat_props, hw_compat_6_1, hw_compat_6_1_len); 482 compat_props_add(m->compat_props, pc_compat_6_1, pc_compat_6_1_len); 483 m->smp_props.prefer_sockets = true; 484 } 485 486 DEFINE_Q35_MACHINE(6, 1); 487 488 static void pc_q35_machine_6_0_options(MachineClass *m) 489 { 490 pc_q35_machine_6_1_options(m); 491 compat_props_add(m->compat_props, hw_compat_6_0, hw_compat_6_0_len); 492 compat_props_add(m->compat_props, pc_compat_6_0, pc_compat_6_0_len); 493 } 494 495 DEFINE_Q35_MACHINE(6, 0); 496 497 static void pc_q35_machine_5_2_options(MachineClass *m) 498 { 499 pc_q35_machine_6_0_options(m); 500 compat_props_add(m->compat_props, hw_compat_5_2, hw_compat_5_2_len); 501 compat_props_add(m->compat_props, pc_compat_5_2, pc_compat_5_2_len); 502 } 503 504 DEFINE_Q35_MACHINE(5, 2); 505 506 static void pc_q35_machine_5_1_options(MachineClass *m) 507 { 508 PCMachineClass *pcmc = PC_MACHINE_CLASS(m); 509 510 pc_q35_machine_5_2_options(m); 511 compat_props_add(m->compat_props, hw_compat_5_1, hw_compat_5_1_len); 512 compat_props_add(m->compat_props, pc_compat_5_1, pc_compat_5_1_len); 513 pcmc->kvmclock_create_always = false; 514 pcmc->pci_root_uid = 1; 515 } 516 517 DEFINE_Q35_MACHINE(5, 1); 518 519 static void pc_q35_machine_5_0_options(MachineClass *m) 520 { 521 pc_q35_machine_5_1_options(m); 522 m->numa_mem_supported = true; 523 compat_props_add(m->compat_props, hw_compat_5_0, hw_compat_5_0_len); 524 compat_props_add(m->compat_props, pc_compat_5_0, pc_compat_5_0_len); 525 m->auto_enable_numa_with_memdev = false; 526 } 527 528 DEFINE_Q35_MACHINE(5, 0); 529 530 static void pc_q35_machine_4_2_options(MachineClass *m) 531 { 532 pc_q35_machine_5_0_options(m); 533 compat_props_add(m->compat_props, hw_compat_4_2, hw_compat_4_2_len); 534 compat_props_add(m->compat_props, pc_compat_4_2, pc_compat_4_2_len); 535 } 536 537 DEFINE_Q35_MACHINE(4, 2); 538 539 static void pc_q35_machine_4_1_options(MachineClass *m) 540 { 541 pc_q35_machine_4_2_options(m); 542 compat_props_add(m->compat_props, hw_compat_4_1, hw_compat_4_1_len); 543 compat_props_add(m->compat_props, pc_compat_4_1, pc_compat_4_1_len); 544 } 545 546 DEFINE_Q35_MACHINE(4, 1); 547 548 static void pc_q35_machine_4_0_1_options(MachineClass *m) 549 { 550 PCMachineClass *pcmc = PC_MACHINE_CLASS(m); 551 pc_q35_machine_4_1_options(m); 552 pcmc->default_cpu_version = CPU_VERSION_LEGACY; 553 /* 554 * This is the default machine for the 4.0-stable branch. It is basically 555 * a 4.0 that doesn't use split irqchip by default. It MUST hence apply the 556 * 4.0 compat props. 557 */ 558 compat_props_add(m->compat_props, hw_compat_4_0, hw_compat_4_0_len); 559 compat_props_add(m->compat_props, pc_compat_4_0, pc_compat_4_0_len); 560 } 561 562 DEFINE_Q35_MACHINE_BUGFIX(4, 0, 1); 563 564 static void pc_q35_machine_4_0_options(MachineClass *m) 565 { 566 pc_q35_machine_4_0_1_options(m); 567 m->default_kernel_irqchip_split = true; 568 /* Compat props are applied by the 4.0.1 machine */ 569 } 570 571 DEFINE_Q35_MACHINE(4, 0); 572 573 static void pc_q35_machine_3_1_options(MachineClass *m) 574 { 575 PCMachineClass *pcmc = PC_MACHINE_CLASS(m); 576 577 pc_q35_machine_4_0_options(m); 578 m->default_kernel_irqchip_split = false; 579 m->smbus_no_migration_support = true; 580 pcmc->pvh_enabled = false; 581 compat_props_add(m->compat_props, hw_compat_3_1, hw_compat_3_1_len); 582 compat_props_add(m->compat_props, pc_compat_3_1, pc_compat_3_1_len); 583 } 584 585 DEFINE_Q35_MACHINE(3, 1); 586 587 static void pc_q35_machine_3_0_options(MachineClass *m) 588 { 589 pc_q35_machine_3_1_options(m); 590 compat_props_add(m->compat_props, hw_compat_3_0, hw_compat_3_0_len); 591 compat_props_add(m->compat_props, pc_compat_3_0, pc_compat_3_0_len); 592 } 593 594 DEFINE_Q35_MACHINE(3, 0); 595 596 static void pc_q35_machine_2_12_options(MachineClass *m) 597 { 598 pc_q35_machine_3_0_options(m); 599 compat_props_add(m->compat_props, hw_compat_2_12, hw_compat_2_12_len); 600 compat_props_add(m->compat_props, pc_compat_2_12, pc_compat_2_12_len); 601 } 602 603 DEFINE_Q35_MACHINE(2, 12); 604 605 static void pc_q35_machine_2_11_options(MachineClass *m) 606 { 607 pc_q35_machine_2_12_options(m); 608 m->default_nic = "e1000"; 609 compat_props_add(m->compat_props, hw_compat_2_11, hw_compat_2_11_len); 610 compat_props_add(m->compat_props, pc_compat_2_11, pc_compat_2_11_len); 611 } 612 613 DEFINE_Q35_MACHINE(2, 11); 614 615 static void pc_q35_machine_2_10_options(MachineClass *m) 616 { 617 pc_q35_machine_2_11_options(m); 618 compat_props_add(m->compat_props, hw_compat_2_10, hw_compat_2_10_len); 619 compat_props_add(m->compat_props, pc_compat_2_10, pc_compat_2_10_len); 620 m->auto_enable_numa_with_memhp = false; 621 } 622 623 DEFINE_Q35_MACHINE(2, 10); 624 625 static void pc_q35_machine_2_9_options(MachineClass *m) 626 { 627 pc_q35_machine_2_10_options(m); 628 compat_props_add(m->compat_props, hw_compat_2_9, hw_compat_2_9_len); 629 compat_props_add(m->compat_props, pc_compat_2_9, pc_compat_2_9_len); 630 } 631 632 DEFINE_Q35_MACHINE(2, 9); 633 634 static void pc_q35_machine_2_8_options(MachineClass *m) 635 { 636 pc_q35_machine_2_9_options(m); 637 compat_props_add(m->compat_props, hw_compat_2_8, hw_compat_2_8_len); 638 compat_props_add(m->compat_props, pc_compat_2_8, pc_compat_2_8_len); 639 } 640 641 DEFINE_Q35_MACHINE(2, 8); 642 643 static void pc_q35_machine_2_7_options(MachineClass *m) 644 { 645 pc_q35_machine_2_8_options(m); 646 m->max_cpus = 255; 647 compat_props_add(m->compat_props, hw_compat_2_7, hw_compat_2_7_len); 648 compat_props_add(m->compat_props, pc_compat_2_7, pc_compat_2_7_len); 649 } 650 651 DEFINE_Q35_MACHINE(2, 7); 652 653 static void pc_q35_machine_2_6_options(MachineClass *m) 654 { 655 X86MachineClass *x86mc = X86_MACHINE_CLASS(m); 656 PCMachineClass *pcmc = PC_MACHINE_CLASS(m); 657 658 pc_q35_machine_2_7_options(m); 659 pcmc->legacy_cpu_hotplug = true; 660 x86mc->fwcfg_dma_enabled = false; 661 compat_props_add(m->compat_props, hw_compat_2_6, hw_compat_2_6_len); 662 compat_props_add(m->compat_props, pc_compat_2_6, pc_compat_2_6_len); 663 } 664 665 DEFINE_Q35_MACHINE(2, 6); 666 667 static void pc_q35_machine_2_5_options(MachineClass *m) 668 { 669 X86MachineClass *x86mc = X86_MACHINE_CLASS(m); 670 671 pc_q35_machine_2_6_options(m); 672 x86mc->save_tsc_khz = false; 673 m->legacy_fw_cfg_order = 1; 674 compat_props_add(m->compat_props, hw_compat_2_5, hw_compat_2_5_len); 675 compat_props_add(m->compat_props, pc_compat_2_5, pc_compat_2_5_len); 676 } 677 678 DEFINE_Q35_MACHINE(2, 5); 679 680 static void pc_q35_machine_2_4_options(MachineClass *m) 681 { 682 PCMachineClass *pcmc = PC_MACHINE_CLASS(m); 683 684 pc_q35_machine_2_5_options(m); 685 m->hw_version = "2.4.0"; 686 pcmc->broken_reserved_end = true; 687 compat_props_add(m->compat_props, hw_compat_2_4, hw_compat_2_4_len); 688 compat_props_add(m->compat_props, pc_compat_2_4, pc_compat_2_4_len); 689 } 690 691 DEFINE_Q35_MACHINE(2, 4); 692