1 /* 2 * Q35 chipset based pc system emulator 3 * 4 * Copyright (c) 2003-2004 Fabrice Bellard 5 * Copyright (c) 2009, 2010 6 * Isaku Yamahata <yamahata at valinux co jp> 7 * VA Linux Systems Japan K.K. 8 * Copyright (C) 2012 Jason Baron <jbaron@redhat.com> 9 * 10 * This is based on pc.c, but heavily modified. 11 * 12 * Permission is hereby granted, free of charge, to any person obtaining a copy 13 * of this software and associated documentation files (the "Software"), to deal 14 * in the Software without restriction, including without limitation the rights 15 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 16 * copies of the Software, and to permit persons to whom the Software is 17 * furnished to do so, subject to the following conditions: 18 * 19 * The above copyright notice and this permission notice shall be included in 20 * all copies or substantial portions of the Software. 21 * 22 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 23 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 24 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 25 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 26 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 27 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN 28 * THE SOFTWARE. 29 */ 30 #include "hw/hw.h" 31 #include "hw/loader.h" 32 #include "sysemu/arch_init.h" 33 #include "hw/i2c/smbus.h" 34 #include "hw/boards.h" 35 #include "hw/timer/mc146818rtc.h" 36 #include "hw/xen/xen.h" 37 #include "sysemu/kvm.h" 38 #include "hw/kvm/clock.h" 39 #include "hw/pci-host/q35.h" 40 #include "exec/address-spaces.h" 41 #include "hw/i386/ich9.h" 42 #include "hw/ide/pci.h" 43 #include "hw/ide/ahci.h" 44 #include "hw/usb.h" 45 #include "hw/cpu/icc_bus.h" 46 47 /* ICH9 AHCI has 6 ports */ 48 #define MAX_SATA_PORTS 6 49 50 static bool has_pci_info; 51 static bool has_acpi_build = true; 52 53 /* PC hardware initialisation */ 54 static void pc_q35_init(QEMUMachineInitArgs *args) 55 { 56 ram_addr_t below_4g_mem_size, above_4g_mem_size; 57 Q35PCIHost *q35_host; 58 PCIHostState *phb; 59 PCIBus *host_bus; 60 PCIDevice *lpc; 61 BusState *idebus[MAX_SATA_PORTS]; 62 ISADevice *rtc_state; 63 ISADevice *floppy; 64 MemoryRegion *pci_memory; 65 MemoryRegion *rom_memory; 66 MemoryRegion *ram_memory; 67 GSIState *gsi_state; 68 ISABus *isa_bus; 69 int pci_enabled = 1; 70 qemu_irq *cpu_irq; 71 qemu_irq *gsi; 72 qemu_irq *i8259; 73 int i; 74 ICH9LPCState *ich9_lpc; 75 PCIDevice *ahci; 76 DeviceState *icc_bridge; 77 PcGuestInfo *guest_info; 78 79 if (xen_enabled() && xen_hvm_init(&ram_memory) != 0) { 80 fprintf(stderr, "xen hardware virtual machine initialisation failed\n"); 81 exit(1); 82 } 83 84 icc_bridge = qdev_create(NULL, TYPE_ICC_BRIDGE); 85 object_property_add_child(qdev_get_machine(), "icc-bridge", 86 OBJECT(icc_bridge), NULL); 87 88 pc_cpus_init(args->cpu_model, icc_bridge); 89 pc_acpi_init("q35-acpi-dsdt.aml"); 90 91 kvmclock_create(); 92 93 if (args->ram_size >= 0xb0000000) { 94 above_4g_mem_size = args->ram_size - 0xb0000000; 95 below_4g_mem_size = 0xb0000000; 96 } else { 97 above_4g_mem_size = 0; 98 below_4g_mem_size = args->ram_size; 99 } 100 101 /* pci enabled */ 102 if (pci_enabled) { 103 pci_memory = g_new(MemoryRegion, 1); 104 memory_region_init(pci_memory, NULL, "pci", INT64_MAX); 105 rom_memory = pci_memory; 106 } else { 107 pci_memory = NULL; 108 rom_memory = get_system_memory(); 109 } 110 111 guest_info = pc_guest_info_init(below_4g_mem_size, above_4g_mem_size); 112 guest_info->has_pci_info = has_pci_info; 113 guest_info->isapc_ram_fw = false; 114 guest_info->has_acpi_build = has_acpi_build; 115 116 /* allocate ram and load rom/bios */ 117 if (!xen_enabled()) { 118 pc_memory_init(get_system_memory(), 119 args->kernel_filename, args->kernel_cmdline, 120 args->initrd_filename, 121 below_4g_mem_size, above_4g_mem_size, 122 rom_memory, &ram_memory, guest_info); 123 } 124 125 /* irq lines */ 126 gsi_state = g_malloc0(sizeof(*gsi_state)); 127 if (kvm_irqchip_in_kernel()) { 128 kvm_pc_setup_irq_routing(pci_enabled); 129 gsi = qemu_allocate_irqs(kvm_pc_gsi_handler, gsi_state, 130 GSI_NUM_PINS); 131 } else { 132 gsi = qemu_allocate_irqs(gsi_handler, gsi_state, GSI_NUM_PINS); 133 } 134 135 /* create pci host bus */ 136 q35_host = Q35_HOST_DEVICE(qdev_create(NULL, TYPE_Q35_HOST_DEVICE)); 137 138 object_property_add_child(qdev_get_machine(), "q35", OBJECT(q35_host), NULL); 139 q35_host->mch.ram_memory = ram_memory; 140 q35_host->mch.pci_address_space = pci_memory; 141 q35_host->mch.system_memory = get_system_memory(); 142 q35_host->mch.address_space_io = get_system_io(); 143 q35_host->mch.below_4g_mem_size = below_4g_mem_size; 144 q35_host->mch.above_4g_mem_size = above_4g_mem_size; 145 q35_host->mch.guest_info = guest_info; 146 /* pci */ 147 qdev_init_nofail(DEVICE(q35_host)); 148 phb = PCI_HOST_BRIDGE(q35_host); 149 host_bus = phb->bus; 150 /* create ISA bus */ 151 lpc = pci_create_simple_multifunction(host_bus, PCI_DEVFN(ICH9_LPC_DEV, 152 ICH9_LPC_FUNC), true, 153 TYPE_ICH9_LPC_DEVICE); 154 ich9_lpc = ICH9_LPC_DEVICE(lpc); 155 ich9_lpc->pic = gsi; 156 ich9_lpc->ioapic = gsi_state->ioapic_irq; 157 pci_bus_irqs(host_bus, ich9_lpc_set_irq, ich9_lpc_map_irq, ich9_lpc, 158 ICH9_LPC_NB_PIRQS); 159 pci_bus_set_route_irq_fn(host_bus, ich9_route_intx_pin_to_irq); 160 isa_bus = ich9_lpc->isa_bus; 161 162 /*end early*/ 163 isa_bus_irqs(isa_bus, gsi); 164 165 if (kvm_irqchip_in_kernel()) { 166 i8259 = kvm_i8259_init(isa_bus); 167 } else if (xen_enabled()) { 168 i8259 = xen_interrupt_controller_init(); 169 } else { 170 cpu_irq = pc_allocate_cpu_irq(); 171 i8259 = i8259_init(isa_bus, cpu_irq[0]); 172 } 173 174 for (i = 0; i < ISA_NUM_IRQS; i++) { 175 gsi_state->i8259_irq[i] = i8259[i]; 176 } 177 if (pci_enabled) { 178 ioapic_init_gsi(gsi_state, NULL); 179 } 180 qdev_init_nofail(icc_bridge); 181 182 pc_register_ferr_irq(gsi[13]); 183 184 /* init basic PC hardware */ 185 pc_basic_device_init(isa_bus, gsi, &rtc_state, &floppy, false); 186 187 /* connect pm stuff to lpc */ 188 ich9_lpc_pm_init(lpc); 189 190 /* ahci and SATA device, for q35 1 ahci controller is built-in */ 191 ahci = pci_create_simple_multifunction(host_bus, 192 PCI_DEVFN(ICH9_SATA1_DEV, 193 ICH9_SATA1_FUNC), 194 true, "ich9-ahci"); 195 idebus[0] = qdev_get_child_bus(&ahci->qdev, "ide.0"); 196 idebus[1] = qdev_get_child_bus(&ahci->qdev, "ide.1"); 197 198 if (usb_enabled(false)) { 199 /* Should we create 6 UHCI according to ich9 spec? */ 200 ehci_create_ich9_with_companions(host_bus, 0x1d); 201 } 202 203 /* TODO: Populate SPD eeprom data. */ 204 smbus_eeprom_init(ich9_smb_init(host_bus, 205 PCI_DEVFN(ICH9_SMB_DEV, ICH9_SMB_FUNC), 206 0xb100), 207 8, NULL, 0); 208 209 pc_cmos_init(below_4g_mem_size, above_4g_mem_size, args->boot_order, 210 floppy, idebus[0], idebus[1], rtc_state); 211 212 /* the rest devices to which pci devfn is automatically assigned */ 213 pc_vga_init(isa_bus, host_bus); 214 pc_nic_init(isa_bus, host_bus); 215 if (pci_enabled) { 216 pc_pci_device_init(host_bus); 217 } 218 } 219 220 static void pc_compat_1_6(QEMUMachineInitArgs *args) 221 { 222 has_pci_info = false; 223 rom_file_in_ram = false; 224 has_acpi_build = false; 225 } 226 227 static void pc_compat_1_5(QEMUMachineInitArgs *args) 228 { 229 pc_compat_1_6(args); 230 } 231 232 static void pc_compat_1_4(QEMUMachineInitArgs *args) 233 { 234 pc_compat_1_5(args); 235 x86_cpu_compat_set_features("n270", FEAT_1_ECX, 0, CPUID_EXT_MOVBE); 236 x86_cpu_compat_set_features("Westmere", FEAT_1_ECX, 0, CPUID_EXT_PCLMULQDQ); 237 } 238 239 static void pc_q35_init_1_6(QEMUMachineInitArgs *args) 240 { 241 pc_compat_1_6(args); 242 pc_q35_init(args); 243 } 244 245 static void pc_q35_init_1_5(QEMUMachineInitArgs *args) 246 { 247 pc_compat_1_5(args); 248 pc_q35_init(args); 249 } 250 251 static void pc_q35_init_1_4(QEMUMachineInitArgs *args) 252 { 253 pc_compat_1_4(args); 254 pc_q35_init(args); 255 } 256 257 #define PC_Q35_MACHINE_OPTIONS \ 258 PC_DEFAULT_MACHINE_OPTIONS, \ 259 .desc = "Standard PC (Q35 + ICH9, 2009)", \ 260 .hot_add_cpu = pc_hot_add_cpu 261 262 #define PC_Q35_1_7_MACHINE_OPTIONS PC_Q35_MACHINE_OPTIONS 263 264 static QEMUMachine pc_q35_machine_v1_7 = { 265 PC_Q35_1_7_MACHINE_OPTIONS, 266 .name = "pc-q35-1.7", 267 .alias = "q35", 268 .init = pc_q35_init, 269 }; 270 271 #define PC_Q35_1_6_MACHINE_OPTIONS PC_Q35_MACHINE_OPTIONS 272 273 static QEMUMachine pc_q35_machine_v1_6 = { 274 PC_Q35_1_6_MACHINE_OPTIONS, 275 .name = "pc-q35-1.6", 276 .init = pc_q35_init_1_6, 277 .compat_props = (GlobalProperty[]) { 278 PC_COMPAT_1_6, 279 { /* end of list */ } 280 }, 281 }; 282 283 static QEMUMachine pc_q35_machine_v1_5 = { 284 PC_Q35_1_6_MACHINE_OPTIONS, 285 .name = "pc-q35-1.5", 286 .init = pc_q35_init_1_5, 287 .compat_props = (GlobalProperty[]) { 288 PC_COMPAT_1_5, 289 { /* end of list */ } 290 }, 291 }; 292 293 #define PC_Q35_1_4_MACHINE_OPTIONS \ 294 PC_Q35_1_6_MACHINE_OPTIONS, \ 295 .hot_add_cpu = NULL 296 297 static QEMUMachine pc_q35_machine_v1_4 = { 298 PC_Q35_1_4_MACHINE_OPTIONS, 299 .name = "pc-q35-1.4", 300 .init = pc_q35_init_1_4, 301 .compat_props = (GlobalProperty[]) { 302 PC_COMPAT_1_4, 303 { /* end of list */ } 304 }, 305 }; 306 307 static void pc_q35_machine_init(void) 308 { 309 qemu_register_machine(&pc_q35_machine_v1_7); 310 qemu_register_machine(&pc_q35_machine_v1_6); 311 qemu_register_machine(&pc_q35_machine_v1_5); 312 qemu_register_machine(&pc_q35_machine_v1_4); 313 } 314 315 machine_init(pc_q35_machine_init); 316