1 /* 2 * QEMU PC System Emulator 3 * 4 * Copyright (c) 2003-2004 Fabrice Bellard 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a copy 7 * of this software and associated documentation files (the "Software"), to deal 8 * in the Software without restriction, including without limitation the rights 9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 10 * copies of the Software, and to permit persons to whom the Software is 11 * furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice shall be included in 14 * all copies or substantial portions of the Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN 22 * THE SOFTWARE. 23 */ 24 25 #include "qemu/osdep.h" 26 #include CONFIG_DEVICES 27 28 #include "qemu/units.h" 29 #include "hw/char/parallel-isa.h" 30 #include "hw/dma/i8257.h" 31 #include "hw/loader.h" 32 #include "hw/i386/x86.h" 33 #include "hw/i386/pc.h" 34 #include "hw/i386/apic.h" 35 #include "hw/pci-host/i440fx.h" 36 #include "hw/rtc/mc146818rtc.h" 37 #include "hw/southbridge/piix.h" 38 #include "hw/display/ramfb.h" 39 #include "hw/pci/pci.h" 40 #include "hw/pci/pci_ids.h" 41 #include "hw/usb.h" 42 #include "net/net.h" 43 #include "hw/ide/isa.h" 44 #include "hw/ide/pci.h" 45 #include "hw/irq.h" 46 #include "system/kvm.h" 47 #include "hw/i386/kvm/clock.h" 48 #include "hw/sysbus.h" 49 #include "hw/i2c/smbus_eeprom.h" 50 #include "exec/memory.h" 51 #include "hw/acpi/acpi.h" 52 #include "qapi/error.h" 53 #include "qemu/error-report.h" 54 #include "system/xen.h" 55 #ifdef CONFIG_XEN 56 #include <xen/hvm/hvm_info_table.h> 57 #include "hw/xen/xen_pt.h" 58 #include "hw/xen/xen_igd.h" 59 #endif 60 #include "hw/xen/xen-x86.h" 61 #include "hw/xen/xen.h" 62 #include "migration/global_state.h" 63 #include "migration/misc.h" 64 #include "system/runstate.h" 65 #include "system/numa.h" 66 #include "hw/hyperv/vmbus-bridge.h" 67 #include "hw/mem/nvdimm.h" 68 #include "hw/uefi/var-service-api.h" 69 #include "hw/i386/acpi-build.h" 70 #include "target/i386/cpu.h" 71 72 #define XEN_IOAPIC_NUM_PIRQS 128ULL 73 74 #ifdef CONFIG_IDE_ISA 75 static const int ide_iobase[MAX_IDE_BUS] = { 0x1f0, 0x170 }; 76 static const int ide_iobase2[MAX_IDE_BUS] = { 0x3f6, 0x376 }; 77 static const int ide_irq[MAX_IDE_BUS] = { 14, 15 }; 78 #endif 79 80 /* 81 * Return the global irq number corresponding to a given device irq 82 * pin. We could also use the bus number to have a more precise mapping. 83 */ 84 static int pc_pci_slot_get_pirq(PCIDevice *pci_dev, int pci_intx) 85 { 86 int slot_addend; 87 slot_addend = PCI_SLOT(pci_dev->devfn) - 1; 88 return (pci_intx + slot_addend) & 3; 89 } 90 91 static void piix_intx_routing_notifier_xen(PCIDevice *dev) 92 { 93 int i; 94 95 /* Scan for updates to PCI link routes. */ 96 for (i = 0; i < PIIX_NUM_PIRQS; i++) { 97 const PCIINTxRoute route = pci_device_route_intx_to_irq(dev, i); 98 const uint8_t v = route.mode == PCI_INTX_ENABLED ? route.irq : 0; 99 xen_set_pci_link_route(i, v); 100 } 101 } 102 103 /* PC hardware initialisation */ 104 static void pc_init1(MachineState *machine, const char *pci_type) 105 { 106 PCMachineState *pcms = PC_MACHINE(machine); 107 PCMachineClass *pcmc = PC_MACHINE_GET_CLASS(pcms); 108 X86MachineState *x86ms = X86_MACHINE(machine); 109 MemoryRegion *system_memory = get_system_memory(); 110 MemoryRegion *system_io = get_system_io(); 111 Object *phb = NULL; 112 ISABus *isa_bus; 113 Object *piix4_pm = NULL; 114 qemu_irq smi_irq; 115 GSIState *gsi_state; 116 MemoryRegion *ram_memory; 117 MemoryRegion *pci_memory = NULL; 118 MemoryRegion *rom_memory = system_memory; 119 ram_addr_t lowmem; 120 uint64_t hole64_size = 0; 121 122 /* 123 * Calculate ram split, for memory below and above 4G. It's a bit 124 * complicated for backward compatibility reasons ... 125 * 126 * - Traditional split is 3.5G (lowmem = 0xe0000000). This is the 127 * default value for max_ram_below_4g now. 128 * 129 * - Then, to gigabyte align the memory, we move the split to 3G 130 * (lowmem = 0xc0000000). But only in case we have to split in 131 * the first place, i.e. ram_size is larger than (traditional) 132 * lowmem. And for new machine types (gigabyte_align = true) 133 * only, for live migration compatibility reasons. 134 * 135 * - Next the max-ram-below-4g option was added, which allowed to 136 * reduce lowmem to a smaller value, to allow a larger PCI I/O 137 * window below 4G. qemu doesn't enforce gigabyte alignment here, 138 * but prints a warning. 139 * 140 * - Finally max-ram-below-4g got updated to also allow raising lowmem, 141 * so legacy non-PAE guests can get as much memory as possible in 142 * the 32bit address space below 4G. 143 * 144 * - Note that Xen has its own ram setup code in xen_ram_init(), 145 * called via xen_hvm_init_pc(). 146 * 147 * Examples: 148 * qemu -M pc-1.7 -m 4G (old default) -> 3584M low, 512M high 149 * qemu -M pc -m 4G (new default) -> 3072M low, 1024M high 150 * qemu -M pc,max-ram-below-4g=2G -m 4G -> 2048M low, 2048M high 151 * qemu -M pc,max-ram-below-4g=4G -m 3968M -> 3968M low (=4G-128M) 152 */ 153 if (xen_enabled()) { 154 xen_hvm_init_pc(pcms, &ram_memory); 155 } else { 156 ram_memory = machine->ram; 157 if (!pcms->max_ram_below_4g) { 158 pcms->max_ram_below_4g = 0xe0000000; /* default: 3.5G */ 159 } 160 lowmem = pcms->max_ram_below_4g; 161 if (machine->ram_size >= pcms->max_ram_below_4g) { 162 if (pcmc->gigabyte_align) { 163 if (lowmem > 0xc0000000) { 164 lowmem = 0xc0000000; 165 } 166 if (lowmem & (1 * GiB - 1)) { 167 warn_report("Large machine and max_ram_below_4g " 168 "(%" PRIu64 ") not a multiple of 1G; " 169 "possible bad performance.", 170 pcms->max_ram_below_4g); 171 } 172 } 173 } 174 175 if (machine->ram_size >= lowmem) { 176 x86ms->above_4g_mem_size = machine->ram_size - lowmem; 177 x86ms->below_4g_mem_size = lowmem; 178 } else { 179 x86ms->above_4g_mem_size = 0; 180 x86ms->below_4g_mem_size = machine->ram_size; 181 } 182 } 183 184 pc_machine_init_sgx_epc(pcms); 185 x86_cpus_init(x86ms, pcmc->default_cpu_version); 186 187 if (kvm_enabled()) { 188 kvmclock_create(pcmc->kvmclock_create_always); 189 } 190 191 if (pcmc->pci_enabled) { 192 pci_memory = g_new(MemoryRegion, 1); 193 memory_region_init(pci_memory, NULL, "pci", UINT64_MAX); 194 rom_memory = pci_memory; 195 196 phb = OBJECT(qdev_new(TYPE_I440FX_PCI_HOST_BRIDGE)); 197 object_property_add_child(OBJECT(machine), "i440fx", phb); 198 object_property_set_link(phb, PCI_HOST_PROP_RAM_MEM, 199 OBJECT(ram_memory), &error_fatal); 200 object_property_set_link(phb, PCI_HOST_PROP_PCI_MEM, 201 OBJECT(pci_memory), &error_fatal); 202 object_property_set_link(phb, PCI_HOST_PROP_SYSTEM_MEM, 203 OBJECT(system_memory), &error_fatal); 204 object_property_set_link(phb, PCI_HOST_PROP_IO_MEM, 205 OBJECT(system_io), &error_fatal); 206 object_property_set_uint(phb, PCI_HOST_BELOW_4G_MEM_SIZE, 207 x86ms->below_4g_mem_size, &error_fatal); 208 object_property_set_uint(phb, PCI_HOST_ABOVE_4G_MEM_SIZE, 209 x86ms->above_4g_mem_size, &error_fatal); 210 object_property_set_str(phb, I440FX_HOST_PROP_PCI_TYPE, pci_type, 211 &error_fatal); 212 sysbus_realize_and_unref(SYS_BUS_DEVICE(phb), &error_fatal); 213 214 pcms->pcibus = PCI_BUS(qdev_get_child_bus(DEVICE(phb), "pci.0")); 215 pci_bus_map_irqs(pcms->pcibus, 216 xen_enabled() ? xen_pci_slot_get_pirq 217 : pc_pci_slot_get_pirq); 218 219 hole64_size = object_property_get_uint(phb, 220 PCI_HOST_PROP_PCI_HOLE64_SIZE, 221 &error_abort); 222 } 223 224 /* allocate ram and load rom/bios */ 225 if (!xen_enabled()) { 226 pc_memory_init(pcms, system_memory, rom_memory, hole64_size); 227 } else { 228 assert(machine->ram_size == x86ms->below_4g_mem_size + 229 x86ms->above_4g_mem_size); 230 231 pc_system_flash_cleanup_unused(pcms); 232 if (machine->kernel_filename != NULL) { 233 /* For xen HVM direct kernel boot, load linux here */ 234 xen_load_linux(pcms); 235 } 236 } 237 238 gsi_state = pc_gsi_create(&x86ms->gsi, pcmc->pci_enabled); 239 240 if (pcmc->pci_enabled) { 241 PCIDevice *pci_dev; 242 DeviceState *dev; 243 size_t i; 244 245 pci_dev = pci_new_multifunction(-1, pcms->south_bridge); 246 object_property_set_bool(OBJECT(pci_dev), "has-usb", 247 machine_usb(machine), &error_abort); 248 object_property_set_bool(OBJECT(pci_dev), "has-acpi", 249 x86_machine_is_acpi_enabled(x86ms), 250 &error_abort); 251 object_property_set_bool(OBJECT(pci_dev), "has-pic", false, 252 &error_abort); 253 object_property_set_bool(OBJECT(pci_dev), "has-pit", false, 254 &error_abort); 255 qdev_prop_set_uint32(DEVICE(pci_dev), "smb_io_base", 0xb100); 256 object_property_set_bool(OBJECT(pci_dev), "smm-enabled", 257 x86_machine_is_smm_enabled(x86ms), 258 &error_abort); 259 dev = DEVICE(pci_dev); 260 for (i = 0; i < ISA_NUM_IRQS; i++) { 261 qdev_connect_gpio_out_named(dev, "isa-irqs", i, x86ms->gsi[i]); 262 } 263 pci_realize_and_unref(pci_dev, pcms->pcibus, &error_fatal); 264 265 if (xen_enabled()) { 266 pci_device_set_intx_routing_notifier( 267 pci_dev, piix_intx_routing_notifier_xen); 268 269 /* 270 * Xen supports additional interrupt routes from the PCI devices to 271 * the IOAPIC: the four pins of each PCI device on the bus are also 272 * connected to the IOAPIC directly. 273 * These additional routes can be discovered through ACPI. 274 */ 275 pci_bus_irqs(pcms->pcibus, xen_intx_set_irq, pci_dev, 276 XEN_IOAPIC_NUM_PIRQS); 277 } 278 279 isa_bus = ISA_BUS(qdev_get_child_bus(DEVICE(pci_dev), "isa.0")); 280 x86ms->rtc = ISA_DEVICE(object_resolve_path_component(OBJECT(pci_dev), 281 "rtc")); 282 piix4_pm = object_resolve_path_component(OBJECT(pci_dev), "pm"); 283 dev = DEVICE(object_resolve_path_component(OBJECT(pci_dev), "ide")); 284 pci_ide_create_devs(PCI_DEVICE(dev)); 285 pcms->idebus[0] = qdev_get_child_bus(dev, "ide.0"); 286 pcms->idebus[1] = qdev_get_child_bus(dev, "ide.1"); 287 } else { 288 isa_bus = isa_bus_new(NULL, system_memory, system_io, 289 &error_abort); 290 isa_bus_register_input_irqs(isa_bus, x86ms->gsi); 291 292 x86ms->rtc = isa_new(TYPE_MC146818_RTC); 293 qdev_prop_set_int32(DEVICE(x86ms->rtc), "base_year", 2000); 294 isa_realize_and_unref(x86ms->rtc, isa_bus, &error_fatal); 295 296 i8257_dma_init(OBJECT(machine), isa_bus, 0); 297 pcms->hpet_enabled = false; 298 } 299 300 if (x86ms->pic == ON_OFF_AUTO_ON || x86ms->pic == ON_OFF_AUTO_AUTO) { 301 pc_i8259_create(isa_bus, gsi_state->i8259_irq); 302 } 303 304 if (phb) { 305 ioapic_init_gsi(gsi_state, phb); 306 } 307 308 if (tcg_enabled()) { 309 x86_register_ferr_irq(x86ms->gsi[13]); 310 } 311 312 pc_vga_init(isa_bus, pcmc->pci_enabled ? pcms->pcibus : NULL); 313 314 /* init basic PC hardware */ 315 pc_basic_device_init(pcms, isa_bus, x86ms->gsi, x86ms->rtc, 316 !MACHINE_CLASS(pcmc)->no_floppy, 0x4); 317 318 pc_nic_init(pcmc, isa_bus, pcms->pcibus); 319 320 #ifdef CONFIG_IDE_ISA 321 if (!pcmc->pci_enabled) { 322 DriveInfo *hd[MAX_IDE_BUS * MAX_IDE_DEVS]; 323 int i; 324 325 ide_drive_get(hd, ARRAY_SIZE(hd)); 326 for (i = 0; i < MAX_IDE_BUS; i++) { 327 ISADevice *dev; 328 char busname[] = "ide.0"; 329 dev = isa_ide_init(isa_bus, ide_iobase[i], ide_iobase2[i], 330 ide_irq[i], 331 hd[MAX_IDE_DEVS * i], hd[MAX_IDE_DEVS * i + 1]); 332 /* 333 * The ide bus name is ide.0 for the first bus and ide.1 for the 334 * second one. 335 */ 336 busname[4] = '0' + i; 337 pcms->idebus[i] = qdev_get_child_bus(DEVICE(dev), busname); 338 } 339 } 340 #endif 341 342 if (piix4_pm) { 343 smi_irq = qemu_allocate_irq(pc_acpi_smi_interrupt, first_cpu, 0); 344 345 qdev_connect_gpio_out_named(DEVICE(piix4_pm), "smi-irq", 0, smi_irq); 346 pcms->smbus = I2C_BUS(qdev_get_child_bus(DEVICE(piix4_pm), "i2c")); 347 /* TODO: Populate SPD eeprom data. */ 348 smbus_eeprom_init(pcms->smbus, 8, NULL, 0); 349 350 object_property_add_link(OBJECT(machine), PC_MACHINE_ACPI_DEVICE_PROP, 351 TYPE_HOTPLUG_HANDLER, 352 (Object **)&x86ms->acpi_dev, 353 object_property_allow_set_link, 354 OBJ_PROP_LINK_STRONG); 355 object_property_set_link(OBJECT(machine), PC_MACHINE_ACPI_DEVICE_PROP, 356 piix4_pm, &error_abort); 357 } 358 359 if (machine->nvdimms_state->is_enabled) { 360 nvdimm_init_acpi_state(machine->nvdimms_state, system_io, 361 x86_nvdimm_acpi_dsmio, 362 x86ms->fw_cfg, OBJECT(pcms)); 363 } 364 } 365 366 typedef enum PCSouthBridgeOption { 367 PC_SOUTH_BRIDGE_OPTION_PIIX3, 368 PC_SOUTH_BRIDGE_OPTION_PIIX4, 369 PC_SOUTH_BRIDGE_OPTION_MAX, 370 } PCSouthBridgeOption; 371 372 static const QEnumLookup PCSouthBridgeOption_lookup = { 373 .array = (const char *const[]) { 374 [PC_SOUTH_BRIDGE_OPTION_PIIX3] = TYPE_PIIX3_DEVICE, 375 [PC_SOUTH_BRIDGE_OPTION_PIIX4] = TYPE_PIIX4_PCI_DEVICE, 376 }, 377 .size = PC_SOUTH_BRIDGE_OPTION_MAX 378 }; 379 380 static int pc_get_south_bridge(Object *obj, Error **errp) 381 { 382 PCMachineState *pcms = PC_MACHINE(obj); 383 int i; 384 385 for (i = 0; i < PCSouthBridgeOption_lookup.size; i++) { 386 if (g_strcmp0(PCSouthBridgeOption_lookup.array[i], 387 pcms->south_bridge) == 0) { 388 return i; 389 } 390 } 391 392 error_setg(errp, "Invalid south bridge value set"); 393 return 0; 394 } 395 396 static void pc_set_south_bridge(Object *obj, int value, Error **errp) 397 { 398 PCMachineState *pcms = PC_MACHINE(obj); 399 400 if (value < 0) { 401 error_setg(errp, "Value can't be negative"); 402 return; 403 } 404 405 if (value >= PCSouthBridgeOption_lookup.size) { 406 error_setg(errp, "Value too big"); 407 return; 408 } 409 410 pcms->south_bridge = PCSouthBridgeOption_lookup.array[value]; 411 } 412 413 #ifdef CONFIG_ISAPC 414 static void pc_init_isa(MachineState *machine) 415 { 416 pc_init1(machine, NULL); 417 } 418 #endif 419 420 #ifdef CONFIG_XEN 421 static void pc_xen_hvm_init_pci(MachineState *machine) 422 { 423 const char *pci_type = xen_igd_gfx_pt_enabled() ? 424 TYPE_IGD_PASSTHROUGH_I440FX_PCI_DEVICE : TYPE_I440FX_PCI_DEVICE; 425 426 pc_init1(machine, pci_type); 427 } 428 429 static void pc_xen_hvm_init(MachineState *machine) 430 { 431 PCMachineState *pcms = PC_MACHINE(machine); 432 433 if (!xen_enabled()) { 434 error_report("xenfv machine requires the xen accelerator"); 435 exit(1); 436 } 437 438 pc_xen_hvm_init_pci(machine); 439 xen_igd_reserve_slot(pcms->pcibus); 440 pci_create_simple(pcms->pcibus, -1, "xen-platform"); 441 } 442 #endif 443 444 static void pc_i440fx_init(MachineState *machine) 445 { 446 pc_init1(machine, TYPE_I440FX_PCI_DEVICE); 447 } 448 449 #define DEFINE_I440FX_MACHINE(major, minor) \ 450 DEFINE_PC_VER_MACHINE(pc_i440fx, "pc-i440fx", pc_i440fx_init, false, NULL, major, minor); 451 452 #define DEFINE_I440FX_MACHINE_AS_LATEST(major, minor) \ 453 DEFINE_PC_VER_MACHINE(pc_i440fx, "pc-i440fx", pc_i440fx_init, true, "pc", major, minor); 454 455 static void pc_i440fx_machine_options(MachineClass *m) 456 { 457 PCMachineClass *pcmc = PC_MACHINE_CLASS(m); 458 ObjectClass *oc = OBJECT_CLASS(m); 459 pcmc->default_south_bridge = TYPE_PIIX3_DEVICE; 460 pcmc->pci_root_uid = 0; 461 pcmc->default_cpu_version = 1; 462 463 m->family = "pc_piix"; 464 m->desc = "Standard PC (i440FX + PIIX, 1996)"; 465 m->default_machine_opts = "firmware=bios-256k.bin"; 466 m->default_display = "std"; 467 m->default_nic = "e1000"; 468 m->no_floppy = !module_object_class_by_name(TYPE_ISA_FDC); 469 m->no_parallel = !module_object_class_by_name(TYPE_ISA_PARALLEL); 470 machine_class_allow_dynamic_sysbus_dev(m, TYPE_RAMFB_DEVICE); 471 machine_class_allow_dynamic_sysbus_dev(m, TYPE_VMBUS_BRIDGE); 472 machine_class_allow_dynamic_sysbus_dev(m, TYPE_UEFI_VARS_X64); 473 474 object_class_property_add_enum(oc, "x-south-bridge", "PCSouthBridgeOption", 475 &PCSouthBridgeOption_lookup, 476 pc_get_south_bridge, 477 pc_set_south_bridge); 478 object_class_property_set_description(oc, "x-south-bridge", 479 "Use a different south bridge than PIIX3"); 480 } 481 482 static void pc_i440fx_machine_10_0_options(MachineClass *m) 483 { 484 pc_i440fx_machine_options(m); 485 } 486 487 DEFINE_I440FX_MACHINE_AS_LATEST(10, 0); 488 489 static void pc_i440fx_machine_9_2_options(MachineClass *m) 490 { 491 pc_i440fx_machine_10_0_options(m); 492 compat_props_add(m->compat_props, hw_compat_9_2, hw_compat_9_2_len); 493 compat_props_add(m->compat_props, pc_compat_9_2, pc_compat_9_2_len); 494 } 495 496 DEFINE_I440FX_MACHINE(9, 2); 497 498 static void pc_i440fx_machine_9_1_options(MachineClass *m) 499 { 500 pc_i440fx_machine_9_2_options(m); 501 compat_props_add(m->compat_props, hw_compat_9_1, hw_compat_9_1_len); 502 compat_props_add(m->compat_props, pc_compat_9_1, pc_compat_9_1_len); 503 } 504 505 DEFINE_I440FX_MACHINE(9, 1); 506 507 static void pc_i440fx_machine_9_0_options(MachineClass *m) 508 { 509 PCMachineClass *pcmc = PC_MACHINE_CLASS(m); 510 511 pc_i440fx_machine_9_1_options(m); 512 m->smbios_memory_device_size = 16 * GiB; 513 514 compat_props_add(m->compat_props, hw_compat_9_0, hw_compat_9_0_len); 515 compat_props_add(m->compat_props, pc_compat_9_0, pc_compat_9_0_len); 516 pcmc->isa_bios_alias = false; 517 } 518 519 DEFINE_I440FX_MACHINE(9, 0); 520 521 static void pc_i440fx_machine_8_2_options(MachineClass *m) 522 { 523 PCMachineClass *pcmc = PC_MACHINE_CLASS(m); 524 525 pc_i440fx_machine_9_0_options(m); 526 527 compat_props_add(m->compat_props, hw_compat_8_2, hw_compat_8_2_len); 528 compat_props_add(m->compat_props, pc_compat_8_2, pc_compat_8_2_len); 529 /* For pc-i44fx-8.2 and 8.1, use SMBIOS 3.X by default */ 530 pcmc->default_smbios_ep_type = SMBIOS_ENTRY_POINT_TYPE_64; 531 } 532 533 DEFINE_I440FX_MACHINE(8, 2); 534 535 static void pc_i440fx_machine_8_1_options(MachineClass *m) 536 { 537 PCMachineClass *pcmc = PC_MACHINE_CLASS(m); 538 539 pc_i440fx_machine_8_2_options(m); 540 pcmc->broken_32bit_mem_addr_check = true; 541 542 compat_props_add(m->compat_props, hw_compat_8_1, hw_compat_8_1_len); 543 compat_props_add(m->compat_props, pc_compat_8_1, pc_compat_8_1_len); 544 } 545 546 DEFINE_I440FX_MACHINE(8, 1); 547 548 static void pc_i440fx_machine_8_0_options(MachineClass *m) 549 { 550 PCMachineClass *pcmc = PC_MACHINE_CLASS(m); 551 552 pc_i440fx_machine_8_1_options(m); 553 compat_props_add(m->compat_props, hw_compat_8_0, hw_compat_8_0_len); 554 compat_props_add(m->compat_props, pc_compat_8_0, pc_compat_8_0_len); 555 556 /* For pc-i44fx-8.0 and older, use SMBIOS 2.8 by default */ 557 pcmc->default_smbios_ep_type = SMBIOS_ENTRY_POINT_TYPE_32; 558 } 559 560 DEFINE_I440FX_MACHINE(8, 0); 561 562 static void pc_i440fx_machine_7_2_options(MachineClass *m) 563 { 564 pc_i440fx_machine_8_0_options(m); 565 compat_props_add(m->compat_props, hw_compat_7_2, hw_compat_7_2_len); 566 compat_props_add(m->compat_props, pc_compat_7_2, pc_compat_7_2_len); 567 } 568 569 DEFINE_I440FX_MACHINE(7, 2) 570 571 static void pc_i440fx_machine_7_1_options(MachineClass *m) 572 { 573 pc_i440fx_machine_7_2_options(m); 574 compat_props_add(m->compat_props, hw_compat_7_1, hw_compat_7_1_len); 575 compat_props_add(m->compat_props, pc_compat_7_1, pc_compat_7_1_len); 576 } 577 578 DEFINE_I440FX_MACHINE(7, 1); 579 580 static void pc_i440fx_machine_7_0_options(MachineClass *m) 581 { 582 PCMachineClass *pcmc = PC_MACHINE_CLASS(m); 583 pc_i440fx_machine_7_1_options(m); 584 pcmc->enforce_amd_1tb_hole = false; 585 compat_props_add(m->compat_props, hw_compat_7_0, hw_compat_7_0_len); 586 compat_props_add(m->compat_props, pc_compat_7_0, pc_compat_7_0_len); 587 } 588 589 DEFINE_I440FX_MACHINE(7, 0); 590 591 static void pc_i440fx_machine_6_2_options(MachineClass *m) 592 { 593 pc_i440fx_machine_7_0_options(m); 594 compat_props_add(m->compat_props, hw_compat_6_2, hw_compat_6_2_len); 595 compat_props_add(m->compat_props, pc_compat_6_2, pc_compat_6_2_len); 596 } 597 598 DEFINE_I440FX_MACHINE(6, 2); 599 600 static void pc_i440fx_machine_6_1_options(MachineClass *m) 601 { 602 pc_i440fx_machine_6_2_options(m); 603 compat_props_add(m->compat_props, hw_compat_6_1, hw_compat_6_1_len); 604 compat_props_add(m->compat_props, pc_compat_6_1, pc_compat_6_1_len); 605 m->smp_props.prefer_sockets = true; 606 } 607 608 DEFINE_I440FX_MACHINE(6, 1); 609 610 static void pc_i440fx_machine_6_0_options(MachineClass *m) 611 { 612 pc_i440fx_machine_6_1_options(m); 613 compat_props_add(m->compat_props, hw_compat_6_0, hw_compat_6_0_len); 614 compat_props_add(m->compat_props, pc_compat_6_0, pc_compat_6_0_len); 615 } 616 617 DEFINE_I440FX_MACHINE(6, 0); 618 619 static void pc_i440fx_machine_5_2_options(MachineClass *m) 620 { 621 pc_i440fx_machine_6_0_options(m); 622 compat_props_add(m->compat_props, hw_compat_5_2, hw_compat_5_2_len); 623 compat_props_add(m->compat_props, pc_compat_5_2, pc_compat_5_2_len); 624 } 625 626 DEFINE_I440FX_MACHINE(5, 2); 627 628 static void pc_i440fx_machine_5_1_options(MachineClass *m) 629 { 630 PCMachineClass *pcmc = PC_MACHINE_CLASS(m); 631 632 pc_i440fx_machine_5_2_options(m); 633 compat_props_add(m->compat_props, hw_compat_5_1, hw_compat_5_1_len); 634 compat_props_add(m->compat_props, pc_compat_5_1, pc_compat_5_1_len); 635 pcmc->kvmclock_create_always = false; 636 pcmc->pci_root_uid = 1; 637 } 638 639 DEFINE_I440FX_MACHINE(5, 1); 640 641 static void pc_i440fx_machine_5_0_options(MachineClass *m) 642 { 643 pc_i440fx_machine_5_1_options(m); 644 m->numa_mem_supported = true; 645 compat_props_add(m->compat_props, hw_compat_5_0, hw_compat_5_0_len); 646 compat_props_add(m->compat_props, pc_compat_5_0, pc_compat_5_0_len); 647 m->auto_enable_numa_with_memdev = false; 648 } 649 650 DEFINE_I440FX_MACHINE(5, 0); 651 652 static void pc_i440fx_machine_4_2_options(MachineClass *m) 653 { 654 pc_i440fx_machine_5_0_options(m); 655 compat_props_add(m->compat_props, hw_compat_4_2, hw_compat_4_2_len); 656 compat_props_add(m->compat_props, pc_compat_4_2, pc_compat_4_2_len); 657 } 658 659 DEFINE_I440FX_MACHINE(4, 2); 660 661 static void pc_i440fx_machine_4_1_options(MachineClass *m) 662 { 663 pc_i440fx_machine_4_2_options(m); 664 compat_props_add(m->compat_props, hw_compat_4_1, hw_compat_4_1_len); 665 compat_props_add(m->compat_props, pc_compat_4_1, pc_compat_4_1_len); 666 } 667 668 DEFINE_I440FX_MACHINE(4, 1); 669 670 static void pc_i440fx_machine_4_0_options(MachineClass *m) 671 { 672 PCMachineClass *pcmc = PC_MACHINE_CLASS(m); 673 pc_i440fx_machine_4_1_options(m); 674 pcmc->default_cpu_version = CPU_VERSION_LEGACY; 675 compat_props_add(m->compat_props, hw_compat_4_0, hw_compat_4_0_len); 676 compat_props_add(m->compat_props, pc_compat_4_0, pc_compat_4_0_len); 677 } 678 679 DEFINE_I440FX_MACHINE(4, 0); 680 681 static void pc_i440fx_machine_3_1_options(MachineClass *m) 682 { 683 PCMachineClass *pcmc = PC_MACHINE_CLASS(m); 684 685 pc_i440fx_machine_4_0_options(m); 686 m->smbus_no_migration_support = true; 687 pcmc->pvh_enabled = false; 688 compat_props_add(m->compat_props, hw_compat_3_1, hw_compat_3_1_len); 689 compat_props_add(m->compat_props, pc_compat_3_1, pc_compat_3_1_len); 690 } 691 692 DEFINE_I440FX_MACHINE(3, 1); 693 694 static void pc_i440fx_machine_3_0_options(MachineClass *m) 695 { 696 pc_i440fx_machine_3_1_options(m); 697 compat_props_add(m->compat_props, hw_compat_3_0, hw_compat_3_0_len); 698 compat_props_add(m->compat_props, pc_compat_3_0, pc_compat_3_0_len); 699 } 700 701 DEFINE_I440FX_MACHINE(3, 0); 702 703 static void pc_i440fx_machine_2_12_options(MachineClass *m) 704 { 705 pc_i440fx_machine_3_0_options(m); 706 compat_props_add(m->compat_props, hw_compat_2_12, hw_compat_2_12_len); 707 compat_props_add(m->compat_props, pc_compat_2_12, pc_compat_2_12_len); 708 } 709 710 DEFINE_I440FX_MACHINE(2, 12); 711 712 static void pc_i440fx_machine_2_11_options(MachineClass *m) 713 { 714 pc_i440fx_machine_2_12_options(m); 715 compat_props_add(m->compat_props, hw_compat_2_11, hw_compat_2_11_len); 716 compat_props_add(m->compat_props, pc_compat_2_11, pc_compat_2_11_len); 717 } 718 719 DEFINE_I440FX_MACHINE(2, 11); 720 721 static void pc_i440fx_machine_2_10_options(MachineClass *m) 722 { 723 pc_i440fx_machine_2_11_options(m); 724 compat_props_add(m->compat_props, hw_compat_2_10, hw_compat_2_10_len); 725 compat_props_add(m->compat_props, pc_compat_2_10, pc_compat_2_10_len); 726 m->auto_enable_numa_with_memhp = false; 727 } 728 729 DEFINE_I440FX_MACHINE(2, 10); 730 731 static void pc_i440fx_machine_2_9_options(MachineClass *m) 732 { 733 pc_i440fx_machine_2_10_options(m); 734 compat_props_add(m->compat_props, hw_compat_2_9, hw_compat_2_9_len); 735 compat_props_add(m->compat_props, pc_compat_2_9, pc_compat_2_9_len); 736 } 737 738 DEFINE_I440FX_MACHINE(2, 9); 739 740 static void pc_i440fx_machine_2_8_options(MachineClass *m) 741 { 742 pc_i440fx_machine_2_9_options(m); 743 compat_props_add(m->compat_props, hw_compat_2_8, hw_compat_2_8_len); 744 compat_props_add(m->compat_props, pc_compat_2_8, pc_compat_2_8_len); 745 } 746 747 DEFINE_I440FX_MACHINE(2, 8); 748 749 static void pc_i440fx_machine_2_7_options(MachineClass *m) 750 { 751 pc_i440fx_machine_2_8_options(m); 752 compat_props_add(m->compat_props, hw_compat_2_7, hw_compat_2_7_len); 753 compat_props_add(m->compat_props, pc_compat_2_7, pc_compat_2_7_len); 754 } 755 756 DEFINE_I440FX_MACHINE(2, 7); 757 758 static void pc_i440fx_machine_2_6_options(MachineClass *m) 759 { 760 X86MachineClass *x86mc = X86_MACHINE_CLASS(m); 761 PCMachineClass *pcmc = PC_MACHINE_CLASS(m); 762 763 pc_i440fx_machine_2_7_options(m); 764 pcmc->legacy_cpu_hotplug = true; 765 x86mc->fwcfg_dma_enabled = false; 766 compat_props_add(m->compat_props, hw_compat_2_6, hw_compat_2_6_len); 767 compat_props_add(m->compat_props, pc_compat_2_6, pc_compat_2_6_len); 768 } 769 770 DEFINE_I440FX_MACHINE(2, 6); 771 772 static void pc_i440fx_machine_2_5_options(MachineClass *m) 773 { 774 X86MachineClass *x86mc = X86_MACHINE_CLASS(m); 775 776 pc_i440fx_machine_2_6_options(m); 777 x86mc->save_tsc_khz = false; 778 m->legacy_fw_cfg_order = 1; 779 compat_props_add(m->compat_props, hw_compat_2_5, hw_compat_2_5_len); 780 compat_props_add(m->compat_props, pc_compat_2_5, pc_compat_2_5_len); 781 } 782 783 DEFINE_I440FX_MACHINE(2, 5); 784 785 static void pc_i440fx_machine_2_4_options(MachineClass *m) 786 { 787 PCMachineClass *pcmc = PC_MACHINE_CLASS(m); 788 789 pc_i440fx_machine_2_5_options(m); 790 m->hw_version = "2.4.0"; 791 pcmc->broken_reserved_end = true; 792 compat_props_add(m->compat_props, hw_compat_2_4, hw_compat_2_4_len); 793 compat_props_add(m->compat_props, pc_compat_2_4, pc_compat_2_4_len); 794 } 795 796 DEFINE_I440FX_MACHINE(2, 4); 797 798 #ifdef CONFIG_ISAPC 799 static void isapc_machine_options(MachineClass *m) 800 { 801 PCMachineClass *pcmc = PC_MACHINE_CLASS(m); 802 m->desc = "ISA-only PC"; 803 m->max_cpus = 1; 804 m->option_rom_has_mr = true; 805 m->rom_file_has_mr = false; 806 pcmc->pci_enabled = false; 807 pcmc->has_acpi_build = false; 808 pcmc->smbios_defaults = false; 809 pcmc->gigabyte_align = false; 810 pcmc->smbios_legacy_mode = true; 811 pcmc->has_reserved_memory = false; 812 m->default_nic = "ne2k_isa"; 813 m->default_cpu_type = X86_CPU_TYPE_NAME("486"); 814 m->no_floppy = !module_object_class_by_name(TYPE_ISA_FDC); 815 m->no_parallel = !module_object_class_by_name(TYPE_ISA_PARALLEL); 816 } 817 818 DEFINE_PC_MACHINE(isapc, "isapc", pc_init_isa, 819 isapc_machine_options); 820 #endif 821 822 #ifdef CONFIG_XEN 823 static void xenfv_machine_4_2_options(MachineClass *m) 824 { 825 pc_i440fx_machine_4_2_options(m); 826 m->desc = "Xen Fully-virtualized PC"; 827 m->max_cpus = HVM_MAX_VCPUS; 828 m->default_machine_opts = "accel=xen,suppress-vmdesc=on"; 829 } 830 831 DEFINE_PC_MACHINE(xenfv_4_2, "xenfv-4.2", pc_xen_hvm_init, 832 xenfv_machine_4_2_options); 833 834 static void xenfv_machine_3_1_options(MachineClass *m) 835 { 836 pc_i440fx_machine_3_1_options(m); 837 m->desc = "Xen Fully-virtualized PC"; 838 m->alias = "xenfv"; 839 m->max_cpus = HVM_MAX_VCPUS; 840 m->default_machine_opts = "accel=xen,suppress-vmdesc=on"; 841 } 842 843 DEFINE_PC_MACHINE(xenfv, "xenfv-3.1", pc_xen_hvm_init, 844 xenfv_machine_3_1_options); 845 #endif 846