1 /* 2 * QEMU PC System Emulator 3 * 4 * Copyright (c) 2003-2004 Fabrice Bellard 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a copy 7 * of this software and associated documentation files (the "Software"), to deal 8 * in the Software without restriction, including without limitation the rights 9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 10 * copies of the Software, and to permit persons to whom the Software is 11 * furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice shall be included in 14 * all copies or substantial portions of the Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN 22 * THE SOFTWARE. 23 */ 24 #include "hw/hw.h" 25 #include "hw/i386/pc.h" 26 #include "hw/char/serial.h" 27 #include "hw/i386/apic.h" 28 #include "hw/block/fdc.h" 29 #include "hw/ide.h" 30 #include "hw/pci/pci.h" 31 #include "monitor/monitor.h" 32 #include "hw/nvram/fw_cfg.h" 33 #include "hw/timer/hpet.h" 34 #include "hw/i386/smbios.h" 35 #include "hw/loader.h" 36 #include "elf.h" 37 #include "multiboot.h" 38 #include "hw/timer/mc146818rtc.h" 39 #include "hw/timer/i8254.h" 40 #include "hw/audio/pcspk.h" 41 #include "hw/pci/msi.h" 42 #include "hw/sysbus.h" 43 #include "sysemu/sysemu.h" 44 #include "sysemu/kvm.h" 45 #include "kvm_i386.h" 46 #include "hw/xen/xen.h" 47 #include "sysemu/blockdev.h" 48 #include "hw/block/block.h" 49 #include "ui/qemu-spice.h" 50 #include "exec/memory.h" 51 #include "exec/address-spaces.h" 52 #include "sysemu/arch_init.h" 53 #include "qemu/bitmap.h" 54 #include "qemu/config-file.h" 55 #include "hw/acpi/acpi.h" 56 57 /* debug PC/ISA interrupts */ 58 //#define DEBUG_IRQ 59 60 #ifdef DEBUG_IRQ 61 #define DPRINTF(fmt, ...) \ 62 do { printf("CPUIRQ: " fmt , ## __VA_ARGS__); } while (0) 63 #else 64 #define DPRINTF(fmt, ...) 65 #endif 66 67 /* Leave a chunk of memory at the top of RAM for the BIOS ACPI tables. */ 68 #define ACPI_DATA_SIZE 0x10000 69 #define BIOS_CFG_IOPORT 0x510 70 #define FW_CFG_ACPI_TABLES (FW_CFG_ARCH_LOCAL + 0) 71 #define FW_CFG_SMBIOS_ENTRIES (FW_CFG_ARCH_LOCAL + 1) 72 #define FW_CFG_IRQ0_OVERRIDE (FW_CFG_ARCH_LOCAL + 2) 73 #define FW_CFG_E820_TABLE (FW_CFG_ARCH_LOCAL + 3) 74 #define FW_CFG_HPET (FW_CFG_ARCH_LOCAL + 4) 75 76 #define IO_APIC_DEFAULT_ADDRESS 0xfec00000 77 78 #define E820_NR_ENTRIES 16 79 80 struct e820_entry { 81 uint64_t address; 82 uint64_t length; 83 uint32_t type; 84 } QEMU_PACKED __attribute((__aligned__(4))); 85 86 struct e820_table { 87 uint32_t count; 88 struct e820_entry entry[E820_NR_ENTRIES]; 89 } QEMU_PACKED __attribute((__aligned__(4))); 90 91 static struct e820_table e820_table; 92 struct hpet_fw_config hpet_cfg = {.count = UINT8_MAX}; 93 94 void gsi_handler(void *opaque, int n, int level) 95 { 96 GSIState *s = opaque; 97 98 DPRINTF("pc: %s GSI %d\n", level ? "raising" : "lowering", n); 99 if (n < ISA_NUM_IRQS) { 100 qemu_set_irq(s->i8259_irq[n], level); 101 } 102 qemu_set_irq(s->ioapic_irq[n], level); 103 } 104 105 static void ioport80_write(void *opaque, hwaddr addr, uint64_t data, 106 unsigned size) 107 { 108 } 109 110 static uint64_t ioport80_read(void *opaque, hwaddr addr, unsigned size) 111 { 112 return 0xffffffffffffffffULL; 113 } 114 115 /* MSDOS compatibility mode FPU exception support */ 116 static qemu_irq ferr_irq; 117 118 void pc_register_ferr_irq(qemu_irq irq) 119 { 120 ferr_irq = irq; 121 } 122 123 /* XXX: add IGNNE support */ 124 void cpu_set_ferr(CPUX86State *s) 125 { 126 qemu_irq_raise(ferr_irq); 127 } 128 129 static void ioportF0_write(void *opaque, hwaddr addr, uint64_t data, 130 unsigned size) 131 { 132 qemu_irq_lower(ferr_irq); 133 } 134 135 static uint64_t ioportF0_read(void *opaque, hwaddr addr, unsigned size) 136 { 137 return 0xffffffffffffffffULL; 138 } 139 140 /* TSC handling */ 141 uint64_t cpu_get_tsc(CPUX86State *env) 142 { 143 return cpu_get_ticks(); 144 } 145 146 /* SMM support */ 147 148 static cpu_set_smm_t smm_set; 149 static void *smm_arg; 150 151 void cpu_smm_register(cpu_set_smm_t callback, void *arg) 152 { 153 assert(smm_set == NULL); 154 assert(smm_arg == NULL); 155 smm_set = callback; 156 smm_arg = arg; 157 } 158 159 void cpu_smm_update(CPUX86State *env) 160 { 161 if (smm_set && smm_arg && env == first_cpu) 162 smm_set(!!(env->hflags & HF_SMM_MASK), smm_arg); 163 } 164 165 166 /* IRQ handling */ 167 int cpu_get_pic_interrupt(CPUX86State *env) 168 { 169 int intno; 170 171 intno = apic_get_interrupt(env->apic_state); 172 if (intno >= 0) { 173 return intno; 174 } 175 /* read the irq from the PIC */ 176 if (!apic_accept_pic_intr(env->apic_state)) { 177 return -1; 178 } 179 180 intno = pic_read_irq(isa_pic); 181 return intno; 182 } 183 184 static void pic_irq_request(void *opaque, int irq, int level) 185 { 186 CPUX86State *env = first_cpu; 187 188 DPRINTF("pic_irqs: %s irq %d\n", level? "raise" : "lower", irq); 189 if (env->apic_state) { 190 while (env) { 191 if (apic_accept_pic_intr(env->apic_state)) { 192 apic_deliver_pic_intr(env->apic_state, level); 193 } 194 env = env->next_cpu; 195 } 196 } else { 197 CPUState *cs = CPU(x86_env_get_cpu(env)); 198 if (level) { 199 cpu_interrupt(cs, CPU_INTERRUPT_HARD); 200 } else { 201 cpu_reset_interrupt(cs, CPU_INTERRUPT_HARD); 202 } 203 } 204 } 205 206 /* PC cmos mappings */ 207 208 #define REG_EQUIPMENT_BYTE 0x14 209 210 static int cmos_get_fd_drive_type(FDriveType fd0) 211 { 212 int val; 213 214 switch (fd0) { 215 case FDRIVE_DRV_144: 216 /* 1.44 Mb 3"5 drive */ 217 val = 4; 218 break; 219 case FDRIVE_DRV_288: 220 /* 2.88 Mb 3"5 drive */ 221 val = 5; 222 break; 223 case FDRIVE_DRV_120: 224 /* 1.2 Mb 5"5 drive */ 225 val = 2; 226 break; 227 case FDRIVE_DRV_NONE: 228 default: 229 val = 0; 230 break; 231 } 232 return val; 233 } 234 235 static void cmos_init_hd(ISADevice *s, int type_ofs, int info_ofs, 236 int16_t cylinders, int8_t heads, int8_t sectors) 237 { 238 rtc_set_memory(s, type_ofs, 47); 239 rtc_set_memory(s, info_ofs, cylinders); 240 rtc_set_memory(s, info_ofs + 1, cylinders >> 8); 241 rtc_set_memory(s, info_ofs + 2, heads); 242 rtc_set_memory(s, info_ofs + 3, 0xff); 243 rtc_set_memory(s, info_ofs + 4, 0xff); 244 rtc_set_memory(s, info_ofs + 5, 0xc0 | ((heads > 8) << 3)); 245 rtc_set_memory(s, info_ofs + 6, cylinders); 246 rtc_set_memory(s, info_ofs + 7, cylinders >> 8); 247 rtc_set_memory(s, info_ofs + 8, sectors); 248 } 249 250 /* convert boot_device letter to something recognizable by the bios */ 251 static int boot_device2nibble(char boot_device) 252 { 253 switch(boot_device) { 254 case 'a': 255 case 'b': 256 return 0x01; /* floppy boot */ 257 case 'c': 258 return 0x02; /* hard drive boot */ 259 case 'd': 260 return 0x03; /* CD-ROM boot */ 261 case 'n': 262 return 0x04; /* Network boot */ 263 } 264 return 0; 265 } 266 267 static int set_boot_dev(ISADevice *s, const char *boot_device, int fd_bootchk) 268 { 269 #define PC_MAX_BOOT_DEVICES 3 270 int nbds, bds[3] = { 0, }; 271 int i; 272 273 nbds = strlen(boot_device); 274 if (nbds > PC_MAX_BOOT_DEVICES) { 275 error_report("Too many boot devices for PC"); 276 return(1); 277 } 278 for (i = 0; i < nbds; i++) { 279 bds[i] = boot_device2nibble(boot_device[i]); 280 if (bds[i] == 0) { 281 error_report("Invalid boot device for PC: '%c'", 282 boot_device[i]); 283 return(1); 284 } 285 } 286 rtc_set_memory(s, 0x3d, (bds[1] << 4) | bds[0]); 287 rtc_set_memory(s, 0x38, (bds[2] << 4) | (fd_bootchk ? 0x0 : 0x1)); 288 return(0); 289 } 290 291 static int pc_boot_set(void *opaque, const char *boot_device) 292 { 293 return set_boot_dev(opaque, boot_device, 0); 294 } 295 296 typedef struct pc_cmos_init_late_arg { 297 ISADevice *rtc_state; 298 BusState *idebus[2]; 299 } pc_cmos_init_late_arg; 300 301 static void pc_cmos_init_late(void *opaque) 302 { 303 pc_cmos_init_late_arg *arg = opaque; 304 ISADevice *s = arg->rtc_state; 305 int16_t cylinders; 306 int8_t heads, sectors; 307 int val; 308 int i, trans; 309 310 val = 0; 311 if (ide_get_geometry(arg->idebus[0], 0, 312 &cylinders, &heads, §ors) >= 0) { 313 cmos_init_hd(s, 0x19, 0x1b, cylinders, heads, sectors); 314 val |= 0xf0; 315 } 316 if (ide_get_geometry(arg->idebus[0], 1, 317 &cylinders, &heads, §ors) >= 0) { 318 cmos_init_hd(s, 0x1a, 0x24, cylinders, heads, sectors); 319 val |= 0x0f; 320 } 321 rtc_set_memory(s, 0x12, val); 322 323 val = 0; 324 for (i = 0; i < 4; i++) { 325 /* NOTE: ide_get_geometry() returns the physical 326 geometry. It is always such that: 1 <= sects <= 63, 1 327 <= heads <= 16, 1 <= cylinders <= 16383. The BIOS 328 geometry can be different if a translation is done. */ 329 if (ide_get_geometry(arg->idebus[i / 2], i % 2, 330 &cylinders, &heads, §ors) >= 0) { 331 trans = ide_get_bios_chs_trans(arg->idebus[i / 2], i % 2) - 1; 332 assert((trans & ~3) == 0); 333 val |= trans << (i * 2); 334 } 335 } 336 rtc_set_memory(s, 0x39, val); 337 338 qemu_unregister_reset(pc_cmos_init_late, opaque); 339 } 340 341 void pc_cmos_init(ram_addr_t ram_size, ram_addr_t above_4g_mem_size, 342 const char *boot_device, 343 ISADevice *floppy, BusState *idebus0, BusState *idebus1, 344 ISADevice *s) 345 { 346 int val, nb, i; 347 FDriveType fd_type[2] = { FDRIVE_DRV_NONE, FDRIVE_DRV_NONE }; 348 static pc_cmos_init_late_arg arg; 349 350 /* various important CMOS locations needed by PC/Bochs bios */ 351 352 /* memory size */ 353 /* base memory (first MiB) */ 354 val = MIN(ram_size / 1024, 640); 355 rtc_set_memory(s, 0x15, val); 356 rtc_set_memory(s, 0x16, val >> 8); 357 /* extended memory (next 64MiB) */ 358 if (ram_size > 1024 * 1024) { 359 val = (ram_size - 1024 * 1024) / 1024; 360 } else { 361 val = 0; 362 } 363 if (val > 65535) 364 val = 65535; 365 rtc_set_memory(s, 0x17, val); 366 rtc_set_memory(s, 0x18, val >> 8); 367 rtc_set_memory(s, 0x30, val); 368 rtc_set_memory(s, 0x31, val >> 8); 369 /* memory between 16MiB and 4GiB */ 370 if (ram_size > 16 * 1024 * 1024) { 371 val = (ram_size - 16 * 1024 * 1024) / 65536; 372 } else { 373 val = 0; 374 } 375 if (val > 65535) 376 val = 65535; 377 rtc_set_memory(s, 0x34, val); 378 rtc_set_memory(s, 0x35, val >> 8); 379 /* memory above 4GiB */ 380 val = above_4g_mem_size / 65536; 381 rtc_set_memory(s, 0x5b, val); 382 rtc_set_memory(s, 0x5c, val >> 8); 383 rtc_set_memory(s, 0x5d, val >> 16); 384 385 /* set the number of CPU */ 386 rtc_set_memory(s, 0x5f, smp_cpus - 1); 387 388 /* set boot devices, and disable floppy signature check if requested */ 389 if (set_boot_dev(s, boot_device, fd_bootchk)) { 390 exit(1); 391 } 392 393 /* floppy type */ 394 if (floppy) { 395 for (i = 0; i < 2; i++) { 396 fd_type[i] = isa_fdc_get_drive_type(floppy, i); 397 } 398 } 399 val = (cmos_get_fd_drive_type(fd_type[0]) << 4) | 400 cmos_get_fd_drive_type(fd_type[1]); 401 rtc_set_memory(s, 0x10, val); 402 403 val = 0; 404 nb = 0; 405 if (fd_type[0] < FDRIVE_DRV_NONE) { 406 nb++; 407 } 408 if (fd_type[1] < FDRIVE_DRV_NONE) { 409 nb++; 410 } 411 switch (nb) { 412 case 0: 413 break; 414 case 1: 415 val |= 0x01; /* 1 drive, ready for boot */ 416 break; 417 case 2: 418 val |= 0x41; /* 2 drives, ready for boot */ 419 break; 420 } 421 val |= 0x02; /* FPU is there */ 422 val |= 0x04; /* PS/2 mouse installed */ 423 rtc_set_memory(s, REG_EQUIPMENT_BYTE, val); 424 425 /* hard drives */ 426 arg.rtc_state = s; 427 arg.idebus[0] = idebus0; 428 arg.idebus[1] = idebus1; 429 qemu_register_reset(pc_cmos_init_late, &arg); 430 } 431 432 /* port 92 stuff: could be split off */ 433 typedef struct Port92State { 434 ISADevice dev; 435 MemoryRegion io; 436 uint8_t outport; 437 qemu_irq *a20_out; 438 } Port92State; 439 440 static void port92_write(void *opaque, hwaddr addr, uint64_t val, 441 unsigned size) 442 { 443 Port92State *s = opaque; 444 445 DPRINTF("port92: write 0x%02x\n", val); 446 s->outport = val; 447 qemu_set_irq(*s->a20_out, (val >> 1) & 1); 448 if (val & 1) { 449 qemu_system_reset_request(); 450 } 451 } 452 453 static uint64_t port92_read(void *opaque, hwaddr addr, 454 unsigned size) 455 { 456 Port92State *s = opaque; 457 uint32_t ret; 458 459 ret = s->outport; 460 DPRINTF("port92: read 0x%02x\n", ret); 461 return ret; 462 } 463 464 static void port92_init(ISADevice *dev, qemu_irq *a20_out) 465 { 466 Port92State *s = DO_UPCAST(Port92State, dev, dev); 467 468 s->a20_out = a20_out; 469 } 470 471 static const VMStateDescription vmstate_port92_isa = { 472 .name = "port92", 473 .version_id = 1, 474 .minimum_version_id = 1, 475 .minimum_version_id_old = 1, 476 .fields = (VMStateField []) { 477 VMSTATE_UINT8(outport, Port92State), 478 VMSTATE_END_OF_LIST() 479 } 480 }; 481 482 static void port92_reset(DeviceState *d) 483 { 484 Port92State *s = container_of(d, Port92State, dev.qdev); 485 486 s->outport &= ~1; 487 } 488 489 static const MemoryRegionOps port92_ops = { 490 .read = port92_read, 491 .write = port92_write, 492 .impl = { 493 .min_access_size = 1, 494 .max_access_size = 1, 495 }, 496 .endianness = DEVICE_LITTLE_ENDIAN, 497 }; 498 499 static int port92_initfn(ISADevice *dev) 500 { 501 Port92State *s = DO_UPCAST(Port92State, dev, dev); 502 503 memory_region_init_io(&s->io, &port92_ops, s, "port92", 1); 504 isa_register_ioport(dev, &s->io, 0x92); 505 506 s->outport = 0; 507 return 0; 508 } 509 510 static void port92_class_initfn(ObjectClass *klass, void *data) 511 { 512 DeviceClass *dc = DEVICE_CLASS(klass); 513 ISADeviceClass *ic = ISA_DEVICE_CLASS(klass); 514 ic->init = port92_initfn; 515 dc->no_user = 1; 516 dc->reset = port92_reset; 517 dc->vmsd = &vmstate_port92_isa; 518 } 519 520 static const TypeInfo port92_info = { 521 .name = "port92", 522 .parent = TYPE_ISA_DEVICE, 523 .instance_size = sizeof(Port92State), 524 .class_init = port92_class_initfn, 525 }; 526 527 static void port92_register_types(void) 528 { 529 type_register_static(&port92_info); 530 } 531 532 type_init(port92_register_types) 533 534 static void handle_a20_line_change(void *opaque, int irq, int level) 535 { 536 X86CPU *cpu = opaque; 537 538 /* XXX: send to all CPUs ? */ 539 /* XXX: add logic to handle multiple A20 line sources */ 540 x86_cpu_set_a20(cpu, level); 541 } 542 543 int e820_add_entry(uint64_t address, uint64_t length, uint32_t type) 544 { 545 int index = le32_to_cpu(e820_table.count); 546 struct e820_entry *entry; 547 548 if (index >= E820_NR_ENTRIES) 549 return -EBUSY; 550 entry = &e820_table.entry[index++]; 551 552 entry->address = cpu_to_le64(address); 553 entry->length = cpu_to_le64(length); 554 entry->type = cpu_to_le32(type); 555 556 e820_table.count = cpu_to_le32(index); 557 return index; 558 } 559 560 /* Calculates the limit to CPU APIC ID values 561 * 562 * This function returns the limit for the APIC ID value, so that all 563 * CPU APIC IDs are < pc_apic_id_limit(). 564 * 565 * This is used for FW_CFG_MAX_CPUS. See comments on bochs_bios_init(). 566 */ 567 static unsigned int pc_apic_id_limit(unsigned int max_cpus) 568 { 569 return x86_cpu_apic_id_from_index(max_cpus - 1) + 1; 570 } 571 572 static void *bochs_bios_init(void) 573 { 574 void *fw_cfg; 575 uint8_t *smbios_table; 576 size_t smbios_len; 577 uint64_t *numa_fw_cfg; 578 int i, j; 579 unsigned int apic_id_limit = pc_apic_id_limit(max_cpus); 580 581 fw_cfg = fw_cfg_init(BIOS_CFG_IOPORT, BIOS_CFG_IOPORT + 1, 0, 0); 582 /* FW_CFG_MAX_CPUS is a bit confusing/problematic on x86: 583 * 584 * SeaBIOS needs FW_CFG_MAX_CPUS for CPU hotplug, but the CPU hotplug 585 * QEMU<->SeaBIOS interface is not based on the "CPU index", but on the APIC 586 * ID of hotplugged CPUs[1]. This means that FW_CFG_MAX_CPUS is not the 587 * "maximum number of CPUs", but the "limit to the APIC ID values SeaBIOS 588 * may see". 589 * 590 * So, this means we must not use max_cpus, here, but the maximum possible 591 * APIC ID value, plus one. 592 * 593 * [1] The only kind of "CPU identifier" used between SeaBIOS and QEMU is 594 * the APIC ID, not the "CPU index" 595 */ 596 fw_cfg_add_i16(fw_cfg, FW_CFG_MAX_CPUS, (uint16_t)apic_id_limit); 597 fw_cfg_add_i32(fw_cfg, FW_CFG_ID, 1); 598 fw_cfg_add_i64(fw_cfg, FW_CFG_RAM_SIZE, (uint64_t)ram_size); 599 fw_cfg_add_bytes(fw_cfg, FW_CFG_ACPI_TABLES, 600 acpi_tables, acpi_tables_len); 601 fw_cfg_add_i32(fw_cfg, FW_CFG_IRQ0_OVERRIDE, kvm_allows_irq0_override()); 602 603 smbios_table = smbios_get_table(&smbios_len); 604 if (smbios_table) 605 fw_cfg_add_bytes(fw_cfg, FW_CFG_SMBIOS_ENTRIES, 606 smbios_table, smbios_len); 607 fw_cfg_add_bytes(fw_cfg, FW_CFG_E820_TABLE, 608 &e820_table, sizeof(e820_table)); 609 610 fw_cfg_add_bytes(fw_cfg, FW_CFG_HPET, &hpet_cfg, sizeof(hpet_cfg)); 611 /* allocate memory for the NUMA channel: one (64bit) word for the number 612 * of nodes, one word for each VCPU->node and one word for each node to 613 * hold the amount of memory. 614 */ 615 numa_fw_cfg = g_new0(uint64_t, 1 + apic_id_limit + nb_numa_nodes); 616 numa_fw_cfg[0] = cpu_to_le64(nb_numa_nodes); 617 for (i = 0; i < max_cpus; i++) { 618 unsigned int apic_id = x86_cpu_apic_id_from_index(i); 619 assert(apic_id < apic_id_limit); 620 for (j = 0; j < nb_numa_nodes; j++) { 621 if (test_bit(i, node_cpumask[j])) { 622 numa_fw_cfg[apic_id + 1] = cpu_to_le64(j); 623 break; 624 } 625 } 626 } 627 for (i = 0; i < nb_numa_nodes; i++) { 628 numa_fw_cfg[apic_id_limit + 1 + i] = cpu_to_le64(node_mem[i]); 629 } 630 fw_cfg_add_bytes(fw_cfg, FW_CFG_NUMA, numa_fw_cfg, 631 (1 + apic_id_limit + nb_numa_nodes) * 632 sizeof(*numa_fw_cfg)); 633 634 return fw_cfg; 635 } 636 637 static long get_file_size(FILE *f) 638 { 639 long where, size; 640 641 /* XXX: on Unix systems, using fstat() probably makes more sense */ 642 643 where = ftell(f); 644 fseek(f, 0, SEEK_END); 645 size = ftell(f); 646 fseek(f, where, SEEK_SET); 647 648 return size; 649 } 650 651 static void load_linux(void *fw_cfg, 652 const char *kernel_filename, 653 const char *initrd_filename, 654 const char *kernel_cmdline, 655 hwaddr max_ram_size) 656 { 657 uint16_t protocol; 658 int setup_size, kernel_size, initrd_size = 0, cmdline_size; 659 uint32_t initrd_max; 660 uint8_t header[8192], *setup, *kernel, *initrd_data; 661 hwaddr real_addr, prot_addr, cmdline_addr, initrd_addr = 0; 662 FILE *f; 663 char *vmode; 664 665 /* Align to 16 bytes as a paranoia measure */ 666 cmdline_size = (strlen(kernel_cmdline)+16) & ~15; 667 668 /* load the kernel header */ 669 f = fopen(kernel_filename, "rb"); 670 if (!f || !(kernel_size = get_file_size(f)) || 671 fread(header, 1, MIN(ARRAY_SIZE(header), kernel_size), f) != 672 MIN(ARRAY_SIZE(header), kernel_size)) { 673 fprintf(stderr, "qemu: could not load kernel '%s': %s\n", 674 kernel_filename, strerror(errno)); 675 exit(1); 676 } 677 678 /* kernel protocol version */ 679 #if 0 680 fprintf(stderr, "header magic: %#x\n", ldl_p(header+0x202)); 681 #endif 682 if (ldl_p(header+0x202) == 0x53726448) { 683 protocol = lduw_p(header+0x206); 684 } else { 685 /* This looks like a multiboot kernel. If it is, let's stop 686 treating it like a Linux kernel. */ 687 if (load_multiboot(fw_cfg, f, kernel_filename, initrd_filename, 688 kernel_cmdline, kernel_size, header)) { 689 return; 690 } 691 protocol = 0; 692 } 693 694 if (protocol < 0x200 || !(header[0x211] & 0x01)) { 695 /* Low kernel */ 696 real_addr = 0x90000; 697 cmdline_addr = 0x9a000 - cmdline_size; 698 prot_addr = 0x10000; 699 } else if (protocol < 0x202) { 700 /* High but ancient kernel */ 701 real_addr = 0x90000; 702 cmdline_addr = 0x9a000 - cmdline_size; 703 prot_addr = 0x100000; 704 } else { 705 /* High and recent kernel */ 706 real_addr = 0x10000; 707 cmdline_addr = 0x20000; 708 prot_addr = 0x100000; 709 } 710 711 #if 0 712 fprintf(stderr, 713 "qemu: real_addr = 0x" TARGET_FMT_plx "\n" 714 "qemu: cmdline_addr = 0x" TARGET_FMT_plx "\n" 715 "qemu: prot_addr = 0x" TARGET_FMT_plx "\n", 716 real_addr, 717 cmdline_addr, 718 prot_addr); 719 #endif 720 721 /* highest address for loading the initrd */ 722 if (protocol >= 0x203) { 723 initrd_max = ldl_p(header+0x22c); 724 } else { 725 initrd_max = 0x37ffffff; 726 } 727 728 if (initrd_max >= max_ram_size-ACPI_DATA_SIZE) 729 initrd_max = max_ram_size-ACPI_DATA_SIZE-1; 730 731 fw_cfg_add_i32(fw_cfg, FW_CFG_CMDLINE_ADDR, cmdline_addr); 732 fw_cfg_add_i32(fw_cfg, FW_CFG_CMDLINE_SIZE, strlen(kernel_cmdline)+1); 733 fw_cfg_add_string(fw_cfg, FW_CFG_CMDLINE_DATA, kernel_cmdline); 734 735 if (protocol >= 0x202) { 736 stl_p(header+0x228, cmdline_addr); 737 } else { 738 stw_p(header+0x20, 0xA33F); 739 stw_p(header+0x22, cmdline_addr-real_addr); 740 } 741 742 /* handle vga= parameter */ 743 vmode = strstr(kernel_cmdline, "vga="); 744 if (vmode) { 745 unsigned int video_mode; 746 /* skip "vga=" */ 747 vmode += 4; 748 if (!strncmp(vmode, "normal", 6)) { 749 video_mode = 0xffff; 750 } else if (!strncmp(vmode, "ext", 3)) { 751 video_mode = 0xfffe; 752 } else if (!strncmp(vmode, "ask", 3)) { 753 video_mode = 0xfffd; 754 } else { 755 video_mode = strtol(vmode, NULL, 0); 756 } 757 stw_p(header+0x1fa, video_mode); 758 } 759 760 /* loader type */ 761 /* High nybble = B reserved for QEMU; low nybble is revision number. 762 If this code is substantially changed, you may want to consider 763 incrementing the revision. */ 764 if (protocol >= 0x200) { 765 header[0x210] = 0xB0; 766 } 767 /* heap */ 768 if (protocol >= 0x201) { 769 header[0x211] |= 0x80; /* CAN_USE_HEAP */ 770 stw_p(header+0x224, cmdline_addr-real_addr-0x200); 771 } 772 773 /* load initrd */ 774 if (initrd_filename) { 775 if (protocol < 0x200) { 776 fprintf(stderr, "qemu: linux kernel too old to load a ram disk\n"); 777 exit(1); 778 } 779 780 initrd_size = get_image_size(initrd_filename); 781 if (initrd_size < 0) { 782 fprintf(stderr, "qemu: error reading initrd %s\n", 783 initrd_filename); 784 exit(1); 785 } 786 787 initrd_addr = (initrd_max-initrd_size) & ~4095; 788 789 initrd_data = g_malloc(initrd_size); 790 load_image(initrd_filename, initrd_data); 791 792 fw_cfg_add_i32(fw_cfg, FW_CFG_INITRD_ADDR, initrd_addr); 793 fw_cfg_add_i32(fw_cfg, FW_CFG_INITRD_SIZE, initrd_size); 794 fw_cfg_add_bytes(fw_cfg, FW_CFG_INITRD_DATA, initrd_data, initrd_size); 795 796 stl_p(header+0x218, initrd_addr); 797 stl_p(header+0x21c, initrd_size); 798 } 799 800 /* load kernel and setup */ 801 setup_size = header[0x1f1]; 802 if (setup_size == 0) { 803 setup_size = 4; 804 } 805 setup_size = (setup_size+1)*512; 806 kernel_size -= setup_size; 807 808 setup = g_malloc(setup_size); 809 kernel = g_malloc(kernel_size); 810 fseek(f, 0, SEEK_SET); 811 if (fread(setup, 1, setup_size, f) != setup_size) { 812 fprintf(stderr, "fread() failed\n"); 813 exit(1); 814 } 815 if (fread(kernel, 1, kernel_size, f) != kernel_size) { 816 fprintf(stderr, "fread() failed\n"); 817 exit(1); 818 } 819 fclose(f); 820 memcpy(setup, header, MIN(sizeof(header), setup_size)); 821 822 fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_ADDR, prot_addr); 823 fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_SIZE, kernel_size); 824 fw_cfg_add_bytes(fw_cfg, FW_CFG_KERNEL_DATA, kernel, kernel_size); 825 826 fw_cfg_add_i32(fw_cfg, FW_CFG_SETUP_ADDR, real_addr); 827 fw_cfg_add_i32(fw_cfg, FW_CFG_SETUP_SIZE, setup_size); 828 fw_cfg_add_bytes(fw_cfg, FW_CFG_SETUP_DATA, setup, setup_size); 829 830 option_rom[nb_option_roms].name = "linuxboot.bin"; 831 option_rom[nb_option_roms].bootindex = 0; 832 nb_option_roms++; 833 } 834 835 #define NE2000_NB_MAX 6 836 837 static const int ne2000_io[NE2000_NB_MAX] = { 0x300, 0x320, 0x340, 0x360, 838 0x280, 0x380 }; 839 static const int ne2000_irq[NE2000_NB_MAX] = { 9, 10, 11, 3, 4, 5 }; 840 841 static const int parallel_io[MAX_PARALLEL_PORTS] = { 0x378, 0x278, 0x3bc }; 842 static const int parallel_irq[MAX_PARALLEL_PORTS] = { 7, 7, 7 }; 843 844 void pc_init_ne2k_isa(ISABus *bus, NICInfo *nd) 845 { 846 static int nb_ne2k = 0; 847 848 if (nb_ne2k == NE2000_NB_MAX) 849 return; 850 isa_ne2000_init(bus, ne2000_io[nb_ne2k], 851 ne2000_irq[nb_ne2k], nd); 852 nb_ne2k++; 853 } 854 855 DeviceState *cpu_get_current_apic(void) 856 { 857 if (cpu_single_env) { 858 return cpu_single_env->apic_state; 859 } else { 860 return NULL; 861 } 862 } 863 864 void pc_acpi_smi_interrupt(void *opaque, int irq, int level) 865 { 866 X86CPU *cpu = opaque; 867 868 if (level) { 869 cpu_interrupt(CPU(cpu), CPU_INTERRUPT_SMI); 870 } 871 } 872 873 void pc_cpus_init(const char *cpu_model) 874 { 875 int i; 876 877 /* init CPUs */ 878 if (cpu_model == NULL) { 879 #ifdef TARGET_X86_64 880 cpu_model = "qemu64"; 881 #else 882 cpu_model = "qemu32"; 883 #endif 884 } 885 886 for (i = 0; i < smp_cpus; i++) { 887 if (!cpu_x86_init(cpu_model)) { 888 exit(1); 889 } 890 } 891 } 892 893 void pc_acpi_init(const char *default_dsdt) 894 { 895 char *filename; 896 897 if (acpi_tables != NULL) { 898 /* manually set via -acpitable, leave it alone */ 899 return; 900 } 901 902 filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, default_dsdt); 903 if (filename == NULL) { 904 fprintf(stderr, "WARNING: failed to find %s\n", default_dsdt); 905 } else { 906 char *arg; 907 QemuOpts *opts; 908 Error *err = NULL; 909 910 arg = g_strdup_printf("file=%s", filename); 911 912 /* creates a deep copy of "arg" */ 913 opts = qemu_opts_parse(qemu_find_opts("acpi"), arg, 0); 914 g_assert(opts != NULL); 915 916 acpi_table_add(opts, &err); 917 if (err) { 918 fprintf(stderr, "WARNING: failed to load %s: %s\n", filename, 919 error_get_pretty(err)); 920 error_free(err); 921 } 922 g_free(arg); 923 g_free(filename); 924 } 925 } 926 927 void *pc_memory_init(MemoryRegion *system_memory, 928 const char *kernel_filename, 929 const char *kernel_cmdline, 930 const char *initrd_filename, 931 ram_addr_t below_4g_mem_size, 932 ram_addr_t above_4g_mem_size, 933 MemoryRegion *rom_memory, 934 MemoryRegion **ram_memory) 935 { 936 int linux_boot, i; 937 MemoryRegion *ram, *option_rom_mr; 938 MemoryRegion *ram_below_4g, *ram_above_4g; 939 void *fw_cfg; 940 941 linux_boot = (kernel_filename != NULL); 942 943 /* Allocate RAM. We allocate it as a single memory region and use 944 * aliases to address portions of it, mostly for backwards compatibility 945 * with older qemus that used qemu_ram_alloc(). 946 */ 947 ram = g_malloc(sizeof(*ram)); 948 memory_region_init_ram(ram, "pc.ram", 949 below_4g_mem_size + above_4g_mem_size); 950 vmstate_register_ram_global(ram); 951 *ram_memory = ram; 952 ram_below_4g = g_malloc(sizeof(*ram_below_4g)); 953 memory_region_init_alias(ram_below_4g, "ram-below-4g", ram, 954 0, below_4g_mem_size); 955 memory_region_add_subregion(system_memory, 0, ram_below_4g); 956 if (above_4g_mem_size > 0) { 957 ram_above_4g = g_malloc(sizeof(*ram_above_4g)); 958 memory_region_init_alias(ram_above_4g, "ram-above-4g", ram, 959 below_4g_mem_size, above_4g_mem_size); 960 memory_region_add_subregion(system_memory, 0x100000000ULL, 961 ram_above_4g); 962 } 963 964 965 /* Initialize PC system firmware */ 966 pc_system_firmware_init(rom_memory); 967 968 option_rom_mr = g_malloc(sizeof(*option_rom_mr)); 969 memory_region_init_ram(option_rom_mr, "pc.rom", PC_ROM_SIZE); 970 vmstate_register_ram_global(option_rom_mr); 971 memory_region_add_subregion_overlap(rom_memory, 972 PC_ROM_MIN_VGA, 973 option_rom_mr, 974 1); 975 976 fw_cfg = bochs_bios_init(); 977 rom_set_fw(fw_cfg); 978 979 if (linux_boot) { 980 load_linux(fw_cfg, kernel_filename, initrd_filename, kernel_cmdline, below_4g_mem_size); 981 } 982 983 for (i = 0; i < nb_option_roms; i++) { 984 rom_add_option(option_rom[i].name, option_rom[i].bootindex); 985 } 986 return fw_cfg; 987 } 988 989 qemu_irq *pc_allocate_cpu_irq(void) 990 { 991 return qemu_allocate_irqs(pic_irq_request, NULL, 1); 992 } 993 994 DeviceState *pc_vga_init(ISABus *isa_bus, PCIBus *pci_bus) 995 { 996 DeviceState *dev = NULL; 997 998 if (pci_bus) { 999 PCIDevice *pcidev = pci_vga_init(pci_bus); 1000 dev = pcidev ? &pcidev->qdev : NULL; 1001 } else if (isa_bus) { 1002 ISADevice *isadev = isa_vga_init(isa_bus); 1003 dev = isadev ? &isadev->qdev : NULL; 1004 } 1005 return dev; 1006 } 1007 1008 static void cpu_request_exit(void *opaque, int irq, int level) 1009 { 1010 CPUX86State *env = cpu_single_env; 1011 1012 if (env && level) { 1013 cpu_exit(env); 1014 } 1015 } 1016 1017 static const MemoryRegionOps ioport80_io_ops = { 1018 .write = ioport80_write, 1019 .read = ioport80_read, 1020 .endianness = DEVICE_NATIVE_ENDIAN, 1021 .impl = { 1022 .min_access_size = 1, 1023 .max_access_size = 1, 1024 }, 1025 }; 1026 1027 static const MemoryRegionOps ioportF0_io_ops = { 1028 .write = ioportF0_write, 1029 .read = ioportF0_read, 1030 .endianness = DEVICE_NATIVE_ENDIAN, 1031 .impl = { 1032 .min_access_size = 1, 1033 .max_access_size = 1, 1034 }, 1035 }; 1036 1037 void pc_basic_device_init(ISABus *isa_bus, qemu_irq *gsi, 1038 ISADevice **rtc_state, 1039 ISADevice **floppy, 1040 bool no_vmport) 1041 { 1042 int i; 1043 DriveInfo *fd[MAX_FD]; 1044 DeviceState *hpet = NULL; 1045 int pit_isa_irq = 0; 1046 qemu_irq pit_alt_irq = NULL; 1047 qemu_irq rtc_irq = NULL; 1048 qemu_irq *a20_line; 1049 ISADevice *i8042, *port92, *vmmouse, *pit = NULL; 1050 qemu_irq *cpu_exit_irq; 1051 MemoryRegion *ioport80_io = g_new(MemoryRegion, 1); 1052 MemoryRegion *ioportF0_io = g_new(MemoryRegion, 1); 1053 1054 memory_region_init_io(ioport80_io, &ioport80_io_ops, NULL, "ioport80", 1); 1055 memory_region_add_subregion(isa_bus->address_space_io, 0x80, ioport80_io); 1056 1057 memory_region_init_io(ioportF0_io, &ioportF0_io_ops, NULL, "ioportF0", 1); 1058 memory_region_add_subregion(isa_bus->address_space_io, 0xf0, ioportF0_io); 1059 1060 /* 1061 * Check if an HPET shall be created. 1062 * 1063 * Without KVM_CAP_PIT_STATE2, we cannot switch off the in-kernel PIT 1064 * when the HPET wants to take over. Thus we have to disable the latter. 1065 */ 1066 if (!no_hpet && (!kvm_irqchip_in_kernel() || kvm_has_pit_state2())) { 1067 hpet = sysbus_try_create_simple("hpet", HPET_BASE, NULL); 1068 1069 if (hpet) { 1070 for (i = 0; i < GSI_NUM_PINS; i++) { 1071 sysbus_connect_irq(SYS_BUS_DEVICE(hpet), i, gsi[i]); 1072 } 1073 pit_isa_irq = -1; 1074 pit_alt_irq = qdev_get_gpio_in(hpet, HPET_LEGACY_PIT_INT); 1075 rtc_irq = qdev_get_gpio_in(hpet, HPET_LEGACY_RTC_INT); 1076 } 1077 } 1078 *rtc_state = rtc_init(isa_bus, 2000, rtc_irq); 1079 1080 qemu_register_boot_set(pc_boot_set, *rtc_state); 1081 1082 if (!xen_enabled()) { 1083 if (kvm_irqchip_in_kernel()) { 1084 pit = kvm_pit_init(isa_bus, 0x40); 1085 } else { 1086 pit = pit_init(isa_bus, 0x40, pit_isa_irq, pit_alt_irq); 1087 } 1088 if (hpet) { 1089 /* connect PIT to output control line of the HPET */ 1090 qdev_connect_gpio_out(hpet, 0, qdev_get_gpio_in(&pit->qdev, 0)); 1091 } 1092 pcspk_init(isa_bus, pit); 1093 } 1094 1095 for(i = 0; i < MAX_SERIAL_PORTS; i++) { 1096 if (serial_hds[i]) { 1097 serial_isa_init(isa_bus, i, serial_hds[i]); 1098 } 1099 } 1100 1101 for(i = 0; i < MAX_PARALLEL_PORTS; i++) { 1102 if (parallel_hds[i]) { 1103 parallel_init(isa_bus, i, parallel_hds[i]); 1104 } 1105 } 1106 1107 a20_line = qemu_allocate_irqs(handle_a20_line_change, 1108 x86_env_get_cpu(first_cpu), 2); 1109 i8042 = isa_create_simple(isa_bus, "i8042"); 1110 i8042_setup_a20_line(i8042, &a20_line[0]); 1111 if (!no_vmport) { 1112 vmport_init(isa_bus); 1113 vmmouse = isa_try_create(isa_bus, "vmmouse"); 1114 } else { 1115 vmmouse = NULL; 1116 } 1117 if (vmmouse) { 1118 qdev_prop_set_ptr(&vmmouse->qdev, "ps2_mouse", i8042); 1119 qdev_init_nofail(&vmmouse->qdev); 1120 } 1121 port92 = isa_create_simple(isa_bus, "port92"); 1122 port92_init(port92, &a20_line[1]); 1123 1124 cpu_exit_irq = qemu_allocate_irqs(cpu_request_exit, NULL, 1); 1125 DMA_init(0, cpu_exit_irq); 1126 1127 for(i = 0; i < MAX_FD; i++) { 1128 fd[i] = drive_get(IF_FLOPPY, 0, i); 1129 } 1130 *floppy = fdctrl_init_isa(isa_bus, fd); 1131 } 1132 1133 void pc_nic_init(ISABus *isa_bus, PCIBus *pci_bus) 1134 { 1135 int i; 1136 1137 for (i = 0; i < nb_nics; i++) { 1138 NICInfo *nd = &nd_table[i]; 1139 1140 if (!pci_bus || (nd->model && strcmp(nd->model, "ne2k_isa") == 0)) { 1141 pc_init_ne2k_isa(isa_bus, nd); 1142 } else { 1143 pci_nic_init_nofail(nd, "e1000", NULL); 1144 } 1145 } 1146 } 1147 1148 void pc_pci_device_init(PCIBus *pci_bus) 1149 { 1150 int max_bus; 1151 int bus; 1152 1153 max_bus = drive_get_max_bus(IF_SCSI); 1154 for (bus = 0; bus <= max_bus; bus++) { 1155 pci_create_simple(pci_bus, -1, "lsi53c895a"); 1156 } 1157 } 1158 1159 void ioapic_init_gsi(GSIState *gsi_state, const char *parent_name) 1160 { 1161 DeviceState *dev; 1162 SysBusDevice *d; 1163 unsigned int i; 1164 1165 if (kvm_irqchip_in_kernel()) { 1166 dev = qdev_create(NULL, "kvm-ioapic"); 1167 } else { 1168 dev = qdev_create(NULL, "ioapic"); 1169 } 1170 if (parent_name) { 1171 object_property_add_child(object_resolve_path(parent_name, NULL), 1172 "ioapic", OBJECT(dev), NULL); 1173 } 1174 qdev_init_nofail(dev); 1175 d = SYS_BUS_DEVICE(dev); 1176 sysbus_mmio_map(d, 0, IO_APIC_DEFAULT_ADDRESS); 1177 1178 for (i = 0; i < IOAPIC_NUM_PINS; i++) { 1179 gsi_state->ioapic_irq[i] = qdev_get_gpio_in(dev, i); 1180 } 1181 } 1182