1 /* 2 * QEMU PC System Emulator 3 * 4 * Copyright (c) 2003-2004 Fabrice Bellard 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a copy 7 * of this software and associated documentation files (the "Software"), to deal 8 * in the Software without restriction, including without limitation the rights 9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 10 * copies of the Software, and to permit persons to whom the Software is 11 * furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice shall be included in 14 * all copies or substantial portions of the Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN 22 * THE SOFTWARE. 23 */ 24 25 #include "qemu/osdep.h" 26 #include "qemu/units.h" 27 #include "hw/i386/pc.h" 28 #include "hw/char/serial-isa.h" 29 #include "hw/char/parallel.h" 30 #include "hw/hyperv/hv-balloon.h" 31 #include "hw/i386/fw_cfg.h" 32 #include "hw/i386/vmport.h" 33 #include "system/cpus.h" 34 #include "hw/ide/ide-bus.h" 35 #include "hw/timer/hpet.h" 36 #include "hw/loader.h" 37 #include "hw/rtc/mc146818rtc.h" 38 #include "hw/intc/i8259.h" 39 #include "hw/timer/i8254.h" 40 #include "hw/input/i8042.h" 41 #include "hw/audio/pcspk.h" 42 #include "system/system.h" 43 #include "system/xen.h" 44 #include "system/reset.h" 45 #include "kvm/kvm_i386.h" 46 #include "hw/xen/xen.h" 47 #include "qapi/qmp/qlist.h" 48 #include "qemu/error-report.h" 49 #include "hw/acpi/cpu_hotplug.h" 50 #include "acpi-build.h" 51 #include "hw/mem/nvdimm.h" 52 #include "hw/cxl/cxl_host.h" 53 #include "hw/usb.h" 54 #include "hw/i386/intel_iommu.h" 55 #include "hw/net/ne2000-isa.h" 56 #include "hw/virtio/virtio-iommu.h" 57 #include "hw/virtio/virtio-md-pci.h" 58 #include "hw/i386/kvm/xen_overlay.h" 59 #include "hw/i386/kvm/xen_evtchn.h" 60 #include "hw/i386/kvm/xen_gnttab.h" 61 #include "hw/i386/kvm/xen_xenstore.h" 62 #include "hw/mem/memory-device.h" 63 #include "e820_memory_layout.h" 64 #include "trace.h" 65 #include "sev.h" 66 #include CONFIG_DEVICES 67 68 #ifdef CONFIG_XEN_EMU 69 #include "hw/xen/xen-legacy-backend.h" 70 #include "hw/xen/xen-bus.h" 71 #endif 72 73 /* 74 * Helper for setting model-id for CPU models that changed model-id 75 * depending on QEMU versions up to QEMU 2.4. 76 */ 77 #define PC_CPU_MODEL_IDS(v) \ 78 { "qemu32-" TYPE_X86_CPU, "model-id", "QEMU Virtual CPU version " v, },\ 79 { "qemu64-" TYPE_X86_CPU, "model-id", "QEMU Virtual CPU version " v, },\ 80 { "athlon-" TYPE_X86_CPU, "model-id", "QEMU Virtual CPU version " v, }, 81 82 GlobalProperty pc_compat_9_2[] = {}; 83 const size_t pc_compat_9_2_len = G_N_ELEMENTS(pc_compat_9_2); 84 85 GlobalProperty pc_compat_9_1[] = { 86 { "ICH9-LPC", "x-smi-swsmi-timer", "off" }, 87 { "ICH9-LPC", "x-smi-periodic-timer", "off" }, 88 { TYPE_INTEL_IOMMU_DEVICE, "stale-tm", "on" }, 89 }; 90 const size_t pc_compat_9_1_len = G_N_ELEMENTS(pc_compat_9_1); 91 92 GlobalProperty pc_compat_9_0[] = { 93 { TYPE_X86_CPU, "x-amd-topoext-features-only", "false" }, 94 { TYPE_X86_CPU, "x-l1-cache-per-thread", "false" }, 95 { TYPE_X86_CPU, "guest-phys-bits", "0" }, 96 { "sev-guest", "legacy-vm-type", "on" }, 97 { TYPE_X86_CPU, "legacy-multi-node", "on" }, 98 }; 99 const size_t pc_compat_9_0_len = G_N_ELEMENTS(pc_compat_9_0); 100 101 GlobalProperty pc_compat_8_2[] = {}; 102 const size_t pc_compat_8_2_len = G_N_ELEMENTS(pc_compat_8_2); 103 104 GlobalProperty pc_compat_8_1[] = {}; 105 const size_t pc_compat_8_1_len = G_N_ELEMENTS(pc_compat_8_1); 106 107 GlobalProperty pc_compat_8_0[] = { 108 { "virtio-mem", "unplugged-inaccessible", "auto" }, 109 }; 110 const size_t pc_compat_8_0_len = G_N_ELEMENTS(pc_compat_8_0); 111 112 GlobalProperty pc_compat_7_2[] = { 113 { "ICH9-LPC", "noreboot", "true" }, 114 }; 115 const size_t pc_compat_7_2_len = G_N_ELEMENTS(pc_compat_7_2); 116 117 GlobalProperty pc_compat_7_1[] = {}; 118 const size_t pc_compat_7_1_len = G_N_ELEMENTS(pc_compat_7_1); 119 120 GlobalProperty pc_compat_7_0[] = {}; 121 const size_t pc_compat_7_0_len = G_N_ELEMENTS(pc_compat_7_0); 122 123 GlobalProperty pc_compat_6_2[] = { 124 { "virtio-mem", "unplugged-inaccessible", "off" }, 125 }; 126 const size_t pc_compat_6_2_len = G_N_ELEMENTS(pc_compat_6_2); 127 128 GlobalProperty pc_compat_6_1[] = { 129 { TYPE_X86_CPU, "hv-version-id-build", "0x1bbc" }, 130 { TYPE_X86_CPU, "hv-version-id-major", "0x0006" }, 131 { TYPE_X86_CPU, "hv-version-id-minor", "0x0001" }, 132 { "ICH9-LPC", "x-keep-pci-slot-hpc", "false" }, 133 }; 134 const size_t pc_compat_6_1_len = G_N_ELEMENTS(pc_compat_6_1); 135 136 GlobalProperty pc_compat_6_0[] = { 137 { "qemu64" "-" TYPE_X86_CPU, "family", "6" }, 138 { "qemu64" "-" TYPE_X86_CPU, "model", "6" }, 139 { "qemu64" "-" TYPE_X86_CPU, "stepping", "3" }, 140 { TYPE_X86_CPU, "x-vendor-cpuid-only", "off" }, 141 { "ICH9-LPC", ACPI_PM_PROP_ACPI_PCIHP_BRIDGE, "off" }, 142 { "ICH9-LPC", "x-keep-pci-slot-hpc", "true" }, 143 }; 144 const size_t pc_compat_6_0_len = G_N_ELEMENTS(pc_compat_6_0); 145 146 GlobalProperty pc_compat_5_2[] = { 147 { "ICH9-LPC", "x-smi-cpu-hotunplug", "off" }, 148 }; 149 const size_t pc_compat_5_2_len = G_N_ELEMENTS(pc_compat_5_2); 150 151 GlobalProperty pc_compat_5_1[] = { 152 { "ICH9-LPC", "x-smi-cpu-hotplug", "off" }, 153 { TYPE_X86_CPU, "kvm-msi-ext-dest-id", "off" }, 154 }; 155 const size_t pc_compat_5_1_len = G_N_ELEMENTS(pc_compat_5_1); 156 157 GlobalProperty pc_compat_5_0[] = { 158 }; 159 const size_t pc_compat_5_0_len = G_N_ELEMENTS(pc_compat_5_0); 160 161 GlobalProperty pc_compat_4_2[] = { 162 { "mch", "smbase-smram", "off" }, 163 }; 164 const size_t pc_compat_4_2_len = G_N_ELEMENTS(pc_compat_4_2); 165 166 GlobalProperty pc_compat_4_1[] = {}; 167 const size_t pc_compat_4_1_len = G_N_ELEMENTS(pc_compat_4_1); 168 169 GlobalProperty pc_compat_4_0[] = {}; 170 const size_t pc_compat_4_0_len = G_N_ELEMENTS(pc_compat_4_0); 171 172 GlobalProperty pc_compat_3_1[] = { 173 { "intel-iommu", "dma-drain", "off" }, 174 { "Opteron_G3" "-" TYPE_X86_CPU, "rdtscp", "off" }, 175 { "Opteron_G4" "-" TYPE_X86_CPU, "rdtscp", "off" }, 176 { "Opteron_G4" "-" TYPE_X86_CPU, "npt", "off" }, 177 { "Opteron_G4" "-" TYPE_X86_CPU, "nrip-save", "off" }, 178 { "Opteron_G5" "-" TYPE_X86_CPU, "rdtscp", "off" }, 179 { "Opteron_G5" "-" TYPE_X86_CPU, "npt", "off" }, 180 { "Opteron_G5" "-" TYPE_X86_CPU, "nrip-save", "off" }, 181 { "EPYC" "-" TYPE_X86_CPU, "npt", "off" }, 182 { "EPYC" "-" TYPE_X86_CPU, "nrip-save", "off" }, 183 { "EPYC-IBPB" "-" TYPE_X86_CPU, "npt", "off" }, 184 { "EPYC-IBPB" "-" TYPE_X86_CPU, "nrip-save", "off" }, 185 { "Skylake-Client" "-" TYPE_X86_CPU, "mpx", "on" }, 186 { "Skylake-Client-IBRS" "-" TYPE_X86_CPU, "mpx", "on" }, 187 { "Skylake-Server" "-" TYPE_X86_CPU, "mpx", "on" }, 188 { "Skylake-Server-IBRS" "-" TYPE_X86_CPU, "mpx", "on" }, 189 { "Cascadelake-Server" "-" TYPE_X86_CPU, "mpx", "on" }, 190 { "Icelake-Client" "-" TYPE_X86_CPU, "mpx", "on" }, 191 { "Icelake-Server" "-" TYPE_X86_CPU, "mpx", "on" }, 192 { "Cascadelake-Server" "-" TYPE_X86_CPU, "stepping", "5" }, 193 { TYPE_X86_CPU, "x-intel-pt-auto-level", "off" }, 194 }; 195 const size_t pc_compat_3_1_len = G_N_ELEMENTS(pc_compat_3_1); 196 197 GlobalProperty pc_compat_3_0[] = { 198 { TYPE_X86_CPU, "x-hv-synic-kvm-only", "on" }, 199 { "Skylake-Server" "-" TYPE_X86_CPU, "pku", "off" }, 200 { "Skylake-Server-IBRS" "-" TYPE_X86_CPU, "pku", "off" }, 201 }; 202 const size_t pc_compat_3_0_len = G_N_ELEMENTS(pc_compat_3_0); 203 204 GlobalProperty pc_compat_2_12[] = { 205 { TYPE_X86_CPU, "legacy-cache", "on" }, 206 { TYPE_X86_CPU, "topoext", "off" }, 207 { "EPYC-" TYPE_X86_CPU, "xlevel", "0x8000000a" }, 208 { "EPYC-IBPB-" TYPE_X86_CPU, "xlevel", "0x8000000a" }, 209 }; 210 const size_t pc_compat_2_12_len = G_N_ELEMENTS(pc_compat_2_12); 211 212 GlobalProperty pc_compat_2_11[] = { 213 { TYPE_X86_CPU, "x-migrate-smi-count", "off" }, 214 { "Skylake-Server" "-" TYPE_X86_CPU, "clflushopt", "off" }, 215 }; 216 const size_t pc_compat_2_11_len = G_N_ELEMENTS(pc_compat_2_11); 217 218 GlobalProperty pc_compat_2_10[] = { 219 { TYPE_X86_CPU, "x-hv-max-vps", "0x40" }, 220 { "i440FX-pcihost", "x-pci-hole64-fix", "off" }, 221 { "q35-pcihost", "x-pci-hole64-fix", "off" }, 222 }; 223 const size_t pc_compat_2_10_len = G_N_ELEMENTS(pc_compat_2_10); 224 225 GlobalProperty pc_compat_2_9[] = { 226 { "mch", "extended-tseg-mbytes", "0" }, 227 }; 228 const size_t pc_compat_2_9_len = G_N_ELEMENTS(pc_compat_2_9); 229 230 GlobalProperty pc_compat_2_8[] = { 231 { TYPE_X86_CPU, "tcg-cpuid", "off" }, 232 { "kvmclock", "x-mach-use-reliable-get-clock", "off" }, 233 { "ICH9-LPC", "x-smi-broadcast", "off" }, 234 { TYPE_X86_CPU, "vmware-cpuid-freq", "off" }, 235 { "Haswell-" TYPE_X86_CPU, "stepping", "1" }, 236 }; 237 const size_t pc_compat_2_8_len = G_N_ELEMENTS(pc_compat_2_8); 238 239 GlobalProperty pc_compat_2_7[] = { 240 { TYPE_X86_CPU, "l3-cache", "off" }, 241 { TYPE_X86_CPU, "full-cpuid-auto-level", "off" }, 242 { "Opteron_G3" "-" TYPE_X86_CPU, "family", "15" }, 243 { "Opteron_G3" "-" TYPE_X86_CPU, "model", "6" }, 244 { "Opteron_G3" "-" TYPE_X86_CPU, "stepping", "1" }, 245 { "isa-pcspk", "migrate", "off" }, 246 }; 247 const size_t pc_compat_2_7_len = G_N_ELEMENTS(pc_compat_2_7); 248 249 GlobalProperty pc_compat_2_6[] = { 250 { TYPE_X86_CPU, "cpuid-0xb", "off" }, 251 { "vmxnet3", "romfile", "" }, 252 { TYPE_X86_CPU, "fill-mtrr-mask", "off" }, 253 { "apic-common", "legacy-instance-id", "on", } 254 }; 255 const size_t pc_compat_2_6_len = G_N_ELEMENTS(pc_compat_2_6); 256 257 GlobalProperty pc_compat_2_5[] = {}; 258 const size_t pc_compat_2_5_len = G_N_ELEMENTS(pc_compat_2_5); 259 260 GlobalProperty pc_compat_2_4[] = { 261 PC_CPU_MODEL_IDS("2.4.0") 262 { "Haswell-" TYPE_X86_CPU, "abm", "off" }, 263 { "Haswell-noTSX-" TYPE_X86_CPU, "abm", "off" }, 264 { "Broadwell-" TYPE_X86_CPU, "abm", "off" }, 265 { "Broadwell-noTSX-" TYPE_X86_CPU, "abm", "off" }, 266 { "host" "-" TYPE_X86_CPU, "host-cache-info", "on" }, 267 { TYPE_X86_CPU, "check", "off" }, 268 { "qemu64" "-" TYPE_X86_CPU, "sse4a", "on" }, 269 { "qemu64" "-" TYPE_X86_CPU, "abm", "on" }, 270 { "qemu64" "-" TYPE_X86_CPU, "popcnt", "on" }, 271 { "qemu32" "-" TYPE_X86_CPU, "popcnt", "on" }, 272 { "Opteron_G2" "-" TYPE_X86_CPU, "rdtscp", "on" }, 273 { "Opteron_G3" "-" TYPE_X86_CPU, "rdtscp", "on" }, 274 { "Opteron_G4" "-" TYPE_X86_CPU, "rdtscp", "on" }, 275 { "Opteron_G5" "-" TYPE_X86_CPU, "rdtscp", "on", } 276 }; 277 const size_t pc_compat_2_4_len = G_N_ELEMENTS(pc_compat_2_4); 278 279 /* 280 * @PC_FW_DATA: 281 * Size of the chunk of memory at the top of RAM for the BIOS ACPI tables 282 * and other BIOS datastructures. 283 * 284 * BIOS ACPI tables: 128K. Other BIOS datastructures: less than 4K 285 * reported to be used at the moment, 32K should be enough for a while. 286 */ 287 #define PC_FW_DATA (0x20000 + 0x8000) 288 289 GSIState *pc_gsi_create(qemu_irq **irqs, bool pci_enabled) 290 { 291 GSIState *s; 292 293 s = g_new0(GSIState, 1); 294 if (kvm_ioapic_in_kernel()) { 295 kvm_pc_setup_irq_routing(pci_enabled); 296 } 297 *irqs = qemu_allocate_irqs(gsi_handler, s, IOAPIC_NUM_PINS); 298 299 return s; 300 } 301 302 static void ioport80_write(void *opaque, hwaddr addr, uint64_t data, 303 unsigned size) 304 { 305 } 306 307 static uint64_t ioport80_read(void *opaque, hwaddr addr, unsigned size) 308 { 309 return 0xffffffffffffffffULL; 310 } 311 312 /* MS-DOS compatibility mode FPU exception support */ 313 static void ioportF0_write(void *opaque, hwaddr addr, uint64_t data, 314 unsigned size) 315 { 316 if (tcg_enabled()) { 317 cpu_set_ignne(); 318 } 319 } 320 321 static uint64_t ioportF0_read(void *opaque, hwaddr addr, unsigned size) 322 { 323 return 0xffffffffffffffffULL; 324 } 325 326 /* PC cmos mappings */ 327 328 #define REG_EQUIPMENT_BYTE 0x14 329 330 static void cmos_init_hd(MC146818RtcState *s, int type_ofs, int info_ofs, 331 int16_t cylinders, int8_t heads, int8_t sectors) 332 { 333 mc146818rtc_set_cmos_data(s, type_ofs, 47); 334 mc146818rtc_set_cmos_data(s, info_ofs, cylinders); 335 mc146818rtc_set_cmos_data(s, info_ofs + 1, cylinders >> 8); 336 mc146818rtc_set_cmos_data(s, info_ofs + 2, heads); 337 mc146818rtc_set_cmos_data(s, info_ofs + 3, 0xff); 338 mc146818rtc_set_cmos_data(s, info_ofs + 4, 0xff); 339 mc146818rtc_set_cmos_data(s, info_ofs + 5, 0xc0 | ((heads > 8) << 3)); 340 mc146818rtc_set_cmos_data(s, info_ofs + 6, cylinders); 341 mc146818rtc_set_cmos_data(s, info_ofs + 7, cylinders >> 8); 342 mc146818rtc_set_cmos_data(s, info_ofs + 8, sectors); 343 } 344 345 /* convert boot_device letter to something recognizable by the bios */ 346 static int boot_device2nibble(char boot_device) 347 { 348 switch(boot_device) { 349 case 'a': 350 case 'b': 351 return 0x01; /* floppy boot */ 352 case 'c': 353 return 0x02; /* hard drive boot */ 354 case 'd': 355 return 0x03; /* CD-ROM boot */ 356 case 'n': 357 return 0x04; /* Network boot */ 358 } 359 return 0; 360 } 361 362 static void set_boot_dev(PCMachineState *pcms, MC146818RtcState *s, 363 const char *boot_device, Error **errp) 364 { 365 #define PC_MAX_BOOT_DEVICES 3 366 int nbds, bds[3] = { 0, }; 367 int i; 368 369 nbds = strlen(boot_device); 370 if (nbds > PC_MAX_BOOT_DEVICES) { 371 error_setg(errp, "Too many boot devices for PC"); 372 return; 373 } 374 for (i = 0; i < nbds; i++) { 375 bds[i] = boot_device2nibble(boot_device[i]); 376 if (bds[i] == 0) { 377 error_setg(errp, "Invalid boot device for PC: '%c'", 378 boot_device[i]); 379 return; 380 } 381 } 382 mc146818rtc_set_cmos_data(s, 0x3d, (bds[1] << 4) | bds[0]); 383 mc146818rtc_set_cmos_data(s, 0x38, (bds[2] << 4) | !pcms->fd_bootchk); 384 } 385 386 static void pc_boot_set(void *opaque, const char *boot_device, Error **errp) 387 { 388 PCMachineState *pcms = opaque; 389 X86MachineState *x86ms = X86_MACHINE(pcms); 390 391 set_boot_dev(pcms, MC146818_RTC(x86ms->rtc), boot_device, errp); 392 } 393 394 static void pc_cmos_init_floppy(MC146818RtcState *rtc_state, ISADevice *floppy) 395 { 396 int val, nb; 397 FloppyDriveType fd_type[2] = { FLOPPY_DRIVE_TYPE_NONE, 398 FLOPPY_DRIVE_TYPE_NONE }; 399 400 #ifdef CONFIG_FDC_ISA 401 /* floppy type */ 402 if (floppy) { 403 for (int i = 0; i < 2; i++) { 404 fd_type[i] = isa_fdc_get_drive_type(floppy, i); 405 } 406 } 407 #endif 408 409 val = (cmos_get_fd_drive_type(fd_type[0]) << 4) | 410 cmos_get_fd_drive_type(fd_type[1]); 411 mc146818rtc_set_cmos_data(rtc_state, 0x10, val); 412 413 val = mc146818rtc_get_cmos_data(rtc_state, REG_EQUIPMENT_BYTE); 414 nb = 0; 415 if (fd_type[0] != FLOPPY_DRIVE_TYPE_NONE) { 416 nb++; 417 } 418 if (fd_type[1] != FLOPPY_DRIVE_TYPE_NONE) { 419 nb++; 420 } 421 switch (nb) { 422 case 0: 423 break; 424 case 1: 425 val |= 0x01; /* 1 drive, ready for boot */ 426 break; 427 case 2: 428 val |= 0x41; /* 2 drives, ready for boot */ 429 break; 430 } 431 mc146818rtc_set_cmos_data(rtc_state, REG_EQUIPMENT_BYTE, val); 432 } 433 434 typedef struct check_fdc_state { 435 ISADevice *floppy; 436 bool multiple; 437 } CheckFdcState; 438 439 static int check_fdc(Object *obj, void *opaque) 440 { 441 CheckFdcState *state = opaque; 442 Object *fdc; 443 uint32_t iobase; 444 Error *local_err = NULL; 445 446 fdc = object_dynamic_cast(obj, TYPE_ISA_FDC); 447 if (!fdc) { 448 return 0; 449 } 450 451 iobase = object_property_get_uint(obj, "iobase", &local_err); 452 if (local_err || iobase != 0x3f0) { 453 error_free(local_err); 454 return 0; 455 } 456 457 if (state->floppy) { 458 state->multiple = true; 459 } else { 460 state->floppy = ISA_DEVICE(obj); 461 } 462 return 0; 463 } 464 465 static const char * const fdc_container_path[] = { 466 "/unattached", "/peripheral", "/peripheral-anon" 467 }; 468 469 /* 470 * Locate the FDC at IO address 0x3f0, in order to configure the CMOS registers 471 * and ACPI objects. 472 */ 473 static ISADevice *pc_find_fdc0(void) 474 { 475 int i; 476 Object *container; 477 CheckFdcState state = { 0 }; 478 479 for (i = 0; i < ARRAY_SIZE(fdc_container_path); i++) { 480 container = container_get(qdev_get_machine(), fdc_container_path[i]); 481 object_child_foreach(container, check_fdc, &state); 482 } 483 484 if (state.multiple) { 485 warn_report("multiple floppy disk controllers with " 486 "iobase=0x3f0 have been found"); 487 error_printf("the one being picked for CMOS setup might not reflect " 488 "your intent"); 489 } 490 491 return state.floppy; 492 } 493 494 static void pc_cmos_init_late(PCMachineState *pcms) 495 { 496 X86MachineState *x86ms = X86_MACHINE(pcms); 497 MC146818RtcState *s = MC146818_RTC(x86ms->rtc); 498 int16_t cylinders; 499 int8_t heads, sectors; 500 int val; 501 int i, trans; 502 503 val = 0; 504 if (pcms->idebus[0] && 505 ide_get_geometry(pcms->idebus[0], 0, 506 &cylinders, &heads, §ors) >= 0) { 507 cmos_init_hd(s, 0x19, 0x1b, cylinders, heads, sectors); 508 val |= 0xf0; 509 } 510 if (pcms->idebus[0] && 511 ide_get_geometry(pcms->idebus[0], 1, 512 &cylinders, &heads, §ors) >= 0) { 513 cmos_init_hd(s, 0x1a, 0x24, cylinders, heads, sectors); 514 val |= 0x0f; 515 } 516 mc146818rtc_set_cmos_data(s, 0x12, val); 517 518 val = 0; 519 for (i = 0; i < 4; i++) { 520 /* NOTE: ide_get_geometry() returns the physical 521 geometry. It is always such that: 1 <= sects <= 63, 1 522 <= heads <= 16, 1 <= cylinders <= 16383. The BIOS 523 geometry can be different if a translation is done. */ 524 BusState *idebus = pcms->idebus[i / 2]; 525 if (idebus && 526 ide_get_geometry(idebus, i % 2, 527 &cylinders, &heads, §ors) >= 0) { 528 trans = ide_get_bios_chs_trans(idebus, i % 2) - 1; 529 assert((trans & ~3) == 0); 530 val |= trans << (i * 2); 531 } 532 } 533 mc146818rtc_set_cmos_data(s, 0x39, val); 534 535 pc_cmos_init_floppy(s, pc_find_fdc0()); 536 537 /* various important CMOS locations needed by PC/Bochs bios */ 538 539 /* memory size */ 540 /* base memory (first MiB) */ 541 val = MIN(x86ms->below_4g_mem_size / KiB, 640); 542 mc146818rtc_set_cmos_data(s, 0x15, val); 543 mc146818rtc_set_cmos_data(s, 0x16, val >> 8); 544 /* extended memory (next 64MiB) */ 545 if (x86ms->below_4g_mem_size > 1 * MiB) { 546 val = (x86ms->below_4g_mem_size - 1 * MiB) / KiB; 547 } else { 548 val = 0; 549 } 550 if (val > 65535) 551 val = 65535; 552 mc146818rtc_set_cmos_data(s, 0x17, val); 553 mc146818rtc_set_cmos_data(s, 0x18, val >> 8); 554 mc146818rtc_set_cmos_data(s, 0x30, val); 555 mc146818rtc_set_cmos_data(s, 0x31, val >> 8); 556 /* memory between 16MiB and 4GiB */ 557 if (x86ms->below_4g_mem_size > 16 * MiB) { 558 val = (x86ms->below_4g_mem_size - 16 * MiB) / (64 * KiB); 559 } else { 560 val = 0; 561 } 562 if (val > 65535) 563 val = 65535; 564 mc146818rtc_set_cmos_data(s, 0x34, val); 565 mc146818rtc_set_cmos_data(s, 0x35, val >> 8); 566 /* memory above 4GiB */ 567 val = x86ms->above_4g_mem_size / 65536; 568 mc146818rtc_set_cmos_data(s, 0x5b, val); 569 mc146818rtc_set_cmos_data(s, 0x5c, val >> 8); 570 mc146818rtc_set_cmos_data(s, 0x5d, val >> 16); 571 572 val = 0; 573 val |= 0x02; /* FPU is there */ 574 val |= 0x04; /* PS/2 mouse installed */ 575 mc146818rtc_set_cmos_data(s, REG_EQUIPMENT_BYTE, val); 576 } 577 578 static void handle_a20_line_change(void *opaque, int irq, int level) 579 { 580 X86CPU *cpu = opaque; 581 582 /* XXX: send to all CPUs ? */ 583 /* XXX: add logic to handle multiple A20 line sources */ 584 x86_cpu_set_a20(cpu, level); 585 } 586 587 #define NE2000_NB_MAX 6 588 589 static const int ne2000_io[NE2000_NB_MAX] = { 0x300, 0x320, 0x340, 0x360, 590 0x280, 0x380 }; 591 static const int ne2000_irq[NE2000_NB_MAX] = { 9, 10, 11, 3, 4, 5 }; 592 593 static gboolean pc_init_ne2k_isa(ISABus *bus, NICInfo *nd, Error **errp) 594 { 595 static int nb_ne2k = 0; 596 597 if (nb_ne2k == NE2000_NB_MAX) { 598 error_setg(errp, 599 "maximum number of ISA NE2000 devices exceeded"); 600 return false; 601 } 602 isa_ne2000_init(bus, ne2000_io[nb_ne2k], 603 ne2000_irq[nb_ne2k], nd); 604 nb_ne2k++; 605 return true; 606 } 607 608 void pc_acpi_smi_interrupt(void *opaque, int irq, int level) 609 { 610 X86CPU *cpu = opaque; 611 612 if (level) { 613 cpu_interrupt(CPU(cpu), CPU_INTERRUPT_SMI); 614 } 615 } 616 617 static 618 void pc_machine_done(Notifier *notifier, void *data) 619 { 620 PCMachineState *pcms = container_of(notifier, 621 PCMachineState, machine_done); 622 X86MachineState *x86ms = X86_MACHINE(pcms); 623 624 cxl_hook_up_pxb_registers(pcms->pcibus, &pcms->cxl_devices_state, 625 &error_fatal); 626 627 if (pcms->cxl_devices_state.is_enabled) { 628 cxl_fmws_link_targets(&pcms->cxl_devices_state, &error_fatal); 629 } 630 631 /* set the number of CPUs */ 632 x86_rtc_set_cpus_count(x86ms->rtc, x86ms->boot_cpus); 633 634 pci_bus_add_fw_cfg_extra_pci_roots(x86ms->fw_cfg, pcms->pcibus, 635 &error_abort); 636 637 acpi_setup(); 638 if (x86ms->fw_cfg) { 639 fw_cfg_build_smbios(pcms, x86ms->fw_cfg, pcms->smbios_entry_point_type); 640 fw_cfg_add_e820(x86ms->fw_cfg); 641 fw_cfg_build_feature_control(MACHINE(pcms), x86ms->fw_cfg); 642 /* update FW_CFG_NB_CPUS to account for -device added CPUs */ 643 fw_cfg_modify_i16(x86ms->fw_cfg, FW_CFG_NB_CPUS, x86ms->boot_cpus); 644 } 645 646 pc_cmos_init_late(pcms); 647 } 648 649 /* setup pci memory address space mapping into system address space */ 650 void pc_pci_as_mapping_init(MemoryRegion *system_memory, 651 MemoryRegion *pci_address_space) 652 { 653 /* Set to lower priority than RAM */ 654 memory_region_add_subregion_overlap(system_memory, 0x0, 655 pci_address_space, -1); 656 } 657 658 void xen_load_linux(PCMachineState *pcms) 659 { 660 int i; 661 FWCfgState *fw_cfg; 662 PCMachineClass *pcmc = PC_MACHINE_GET_CLASS(pcms); 663 X86MachineState *x86ms = X86_MACHINE(pcms); 664 665 assert(MACHINE(pcms)->kernel_filename != NULL); 666 667 fw_cfg = fw_cfg_init_io_dma(FW_CFG_IO_BASE, FW_CFG_IO_BASE + 4, 668 &address_space_memory); 669 fw_cfg_add_i16(fw_cfg, FW_CFG_NB_CPUS, x86ms->boot_cpus); 670 rom_set_fw(fw_cfg); 671 672 x86_load_linux(x86ms, fw_cfg, PC_FW_DATA, pcmc->pvh_enabled); 673 for (i = 0; i < nb_option_roms; i++) { 674 assert(!strcmp(option_rom[i].name, "linuxboot.bin") || 675 !strcmp(option_rom[i].name, "linuxboot_dma.bin") || 676 !strcmp(option_rom[i].name, "pvh.bin") || 677 !strcmp(option_rom[i].name, "multiboot.bin") || 678 !strcmp(option_rom[i].name, "multiboot_dma.bin")); 679 rom_add_option(option_rom[i].name, option_rom[i].bootindex); 680 } 681 x86ms->fw_cfg = fw_cfg; 682 } 683 684 #define PC_ROM_MIN_VGA 0xc0000 685 #define PC_ROM_MIN_OPTION 0xc8000 686 #define PC_ROM_MAX 0xe0000 687 #define PC_ROM_ALIGN 0x800 688 #define PC_ROM_SIZE (PC_ROM_MAX - PC_ROM_MIN_VGA) 689 690 static hwaddr pc_above_4g_end(PCMachineState *pcms) 691 { 692 X86MachineState *x86ms = X86_MACHINE(pcms); 693 694 if (pcms->sgx_epc.size != 0) { 695 return sgx_epc_above_4g_end(&pcms->sgx_epc); 696 } 697 698 return x86ms->above_4g_mem_start + x86ms->above_4g_mem_size; 699 } 700 701 static void pc_get_device_memory_range(PCMachineState *pcms, 702 hwaddr *base, 703 ram_addr_t *device_mem_size) 704 { 705 MachineState *machine = MACHINE(pcms); 706 ram_addr_t size; 707 hwaddr addr; 708 709 size = machine->maxram_size - machine->ram_size; 710 addr = ROUND_UP(pc_above_4g_end(pcms), 1 * GiB); 711 712 /* size device region assuming 1G page max alignment per slot */ 713 size += (1 * GiB) * machine->ram_slots; 714 715 *base = addr; 716 *device_mem_size = size; 717 } 718 719 static uint64_t pc_get_cxl_range_start(PCMachineState *pcms) 720 { 721 PCMachineClass *pcmc = PC_MACHINE_GET_CLASS(pcms); 722 MachineState *ms = MACHINE(pcms); 723 hwaddr cxl_base; 724 ram_addr_t size; 725 726 if (pcmc->has_reserved_memory && 727 (ms->ram_size < ms->maxram_size)) { 728 pc_get_device_memory_range(pcms, &cxl_base, &size); 729 cxl_base += size; 730 } else { 731 cxl_base = pc_above_4g_end(pcms); 732 } 733 734 return cxl_base; 735 } 736 737 static uint64_t pc_get_cxl_range_end(PCMachineState *pcms) 738 { 739 uint64_t start = pc_get_cxl_range_start(pcms) + MiB; 740 741 if (pcms->cxl_devices_state.fixed_windows) { 742 GList *it; 743 744 start = ROUND_UP(start, 256 * MiB); 745 for (it = pcms->cxl_devices_state.fixed_windows; it; it = it->next) { 746 CXLFixedWindow *fw = it->data; 747 start += fw->size; 748 } 749 } 750 751 return start; 752 } 753 754 static hwaddr pc_max_used_gpa(PCMachineState *pcms, uint64_t pci_hole64_size) 755 { 756 X86CPU *cpu = X86_CPU(first_cpu); 757 PCMachineClass *pcmc = PC_MACHINE_GET_CLASS(pcms); 758 MachineState *ms = MACHINE(pcms); 759 760 if (cpu->env.features[FEAT_8000_0001_EDX] & CPUID_EXT2_LM) { 761 /* 64-bit systems */ 762 return pc_pci_hole64_start() + pci_hole64_size - 1; 763 } 764 765 /* 32-bit systems */ 766 if (pcmc->broken_32bit_mem_addr_check) { 767 /* old value for compatibility reasons */ 768 return ((hwaddr)1 << cpu->phys_bits) - 1; 769 } 770 771 /* 772 * 32-bit systems don't have hole64 but they might have a region for 773 * memory devices. Even if additional hotplugged memory devices might 774 * not be usable by most guest OSes, we need to still consider them for 775 * calculating the highest possible GPA so that we can properly report 776 * if someone configures them on a CPU that cannot possibly address them. 777 */ 778 if (pcmc->has_reserved_memory && 779 (ms->ram_size < ms->maxram_size)) { 780 hwaddr devmem_start; 781 ram_addr_t devmem_size; 782 783 pc_get_device_memory_range(pcms, &devmem_start, &devmem_size); 784 devmem_start += devmem_size; 785 return devmem_start - 1; 786 } 787 788 /* configuration without any memory hotplug */ 789 return pc_above_4g_end(pcms) - 1; 790 } 791 792 /* 793 * AMD systems with an IOMMU have an additional hole close to the 794 * 1Tb, which are special GPAs that cannot be DMA mapped. Depending 795 * on kernel version, VFIO may or may not let you DMA map those ranges. 796 * Starting Linux v5.4 we validate it, and can't create guests on AMD machines 797 * with certain memory sizes. It's also wrong to use those IOVA ranges 798 * in detriment of leading to IOMMU INVALID_DEVICE_REQUEST or worse. 799 * The ranges reserved for Hyper-Transport are: 800 * 801 * FD_0000_0000h - FF_FFFF_FFFFh 802 * 803 * The ranges represent the following: 804 * 805 * Base Address Top Address Use 806 * 807 * FD_0000_0000h FD_F7FF_FFFFh Reserved interrupt address space 808 * FD_F800_0000h FD_F8FF_FFFFh Interrupt/EOI IntCtl 809 * FD_F900_0000h FD_F90F_FFFFh Legacy PIC IACK 810 * FD_F910_0000h FD_F91F_FFFFh System Management 811 * FD_F920_0000h FD_FAFF_FFFFh Reserved Page Tables 812 * FD_FB00_0000h FD_FBFF_FFFFh Address Translation 813 * FD_FC00_0000h FD_FDFF_FFFFh I/O Space 814 * FD_FE00_0000h FD_FFFF_FFFFh Configuration 815 * FE_0000_0000h FE_1FFF_FFFFh Extended Configuration/Device Messages 816 * FE_2000_0000h FF_FFFF_FFFFh Reserved 817 * 818 * See AMD IOMMU spec, section 2.1.2 "IOMMU Logical Topology", 819 * Table 3: Special Address Controls (GPA) for more information. 820 */ 821 #define AMD_HT_START 0xfd00000000UL 822 #define AMD_HT_END 0xffffffffffUL 823 #define AMD_ABOVE_1TB_START (AMD_HT_END + 1) 824 #define AMD_HT_SIZE (AMD_ABOVE_1TB_START - AMD_HT_START) 825 826 void pc_memory_init(PCMachineState *pcms, 827 MemoryRegion *system_memory, 828 MemoryRegion *rom_memory, 829 uint64_t pci_hole64_size) 830 { 831 int linux_boot, i; 832 MemoryRegion *option_rom_mr; 833 MemoryRegion *ram_below_4g, *ram_above_4g; 834 FWCfgState *fw_cfg; 835 MachineState *machine = MACHINE(pcms); 836 MachineClass *mc = MACHINE_GET_CLASS(machine); 837 PCMachineClass *pcmc = PC_MACHINE_GET_CLASS(pcms); 838 X86MachineState *x86ms = X86_MACHINE(pcms); 839 hwaddr maxphysaddr, maxusedaddr; 840 hwaddr cxl_base, cxl_resv_end = 0; 841 X86CPU *cpu = X86_CPU(first_cpu); 842 843 assert(machine->ram_size == x86ms->below_4g_mem_size + 844 x86ms->above_4g_mem_size); 845 846 linux_boot = (machine->kernel_filename != NULL); 847 848 /* 849 * The HyperTransport range close to the 1T boundary is unique to AMD 850 * hosts with IOMMUs enabled. Restrict the ram-above-4g relocation 851 * to above 1T to AMD vCPUs only. @enforce_amd_1tb_hole is only false in 852 * older machine types (<= 7.0) for compatibility purposes. 853 */ 854 if (IS_AMD_CPU(&cpu->env) && pcmc->enforce_amd_1tb_hole) { 855 /* Bail out if max possible address does not cross HT range */ 856 if (pc_max_used_gpa(pcms, pci_hole64_size) >= AMD_HT_START) { 857 x86ms->above_4g_mem_start = AMD_ABOVE_1TB_START; 858 } 859 860 /* 861 * Advertise the HT region if address space covers the reserved 862 * region or if we relocate. 863 */ 864 if (cpu->phys_bits >= 40) { 865 e820_add_entry(AMD_HT_START, AMD_HT_SIZE, E820_RESERVED); 866 } 867 } 868 869 /* 870 * phys-bits is required to be appropriately configured 871 * to make sure max used GPA is reachable. 872 */ 873 maxusedaddr = pc_max_used_gpa(pcms, pci_hole64_size); 874 maxphysaddr = ((hwaddr)1 << cpu->phys_bits) - 1; 875 if (maxphysaddr < maxusedaddr) { 876 error_report("Address space limit 0x%"PRIx64" < 0x%"PRIx64 877 " phys-bits too low (%u)", 878 maxphysaddr, maxusedaddr, cpu->phys_bits); 879 exit(EXIT_FAILURE); 880 } 881 882 /* 883 * Split single memory region and use aliases to address portions of it, 884 * done for backwards compatibility with older qemus. 885 */ 886 ram_below_4g = g_malloc(sizeof(*ram_below_4g)); 887 memory_region_init_alias(ram_below_4g, NULL, "ram-below-4g", machine->ram, 888 0, x86ms->below_4g_mem_size); 889 memory_region_add_subregion(system_memory, 0, ram_below_4g); 890 e820_add_entry(0, x86ms->below_4g_mem_size, E820_RAM); 891 if (x86ms->above_4g_mem_size > 0) { 892 ram_above_4g = g_malloc(sizeof(*ram_above_4g)); 893 memory_region_init_alias(ram_above_4g, NULL, "ram-above-4g", 894 machine->ram, 895 x86ms->below_4g_mem_size, 896 x86ms->above_4g_mem_size); 897 memory_region_add_subregion(system_memory, x86ms->above_4g_mem_start, 898 ram_above_4g); 899 e820_add_entry(x86ms->above_4g_mem_start, x86ms->above_4g_mem_size, 900 E820_RAM); 901 } 902 903 if (pcms->sgx_epc.size != 0) { 904 e820_add_entry(pcms->sgx_epc.base, pcms->sgx_epc.size, E820_RESERVED); 905 } 906 907 if (!pcmc->has_reserved_memory && 908 (machine->ram_slots || 909 (machine->maxram_size > machine->ram_size))) { 910 911 error_report("\"-memory 'slots|maxmem'\" is not supported by: %s", 912 mc->name); 913 exit(EXIT_FAILURE); 914 } 915 916 /* initialize device memory address space */ 917 if (pcmc->has_reserved_memory && 918 (machine->ram_size < machine->maxram_size)) { 919 ram_addr_t device_mem_size; 920 hwaddr device_mem_base; 921 922 if (machine->ram_slots > ACPI_MAX_RAM_SLOTS) { 923 error_report("unsupported amount of memory slots: %"PRIu64, 924 machine->ram_slots); 925 exit(EXIT_FAILURE); 926 } 927 928 if (QEMU_ALIGN_UP(machine->maxram_size, 929 TARGET_PAGE_SIZE) != machine->maxram_size) { 930 error_report("maximum memory size must by aligned to multiple of " 931 "%d bytes", TARGET_PAGE_SIZE); 932 exit(EXIT_FAILURE); 933 } 934 935 pc_get_device_memory_range(pcms, &device_mem_base, &device_mem_size); 936 937 if (device_mem_base + device_mem_size < device_mem_size) { 938 error_report("unsupported amount of maximum memory: " RAM_ADDR_FMT, 939 machine->maxram_size); 940 exit(EXIT_FAILURE); 941 } 942 machine_memory_devices_init(machine, device_mem_base, device_mem_size); 943 } 944 945 if (pcms->cxl_devices_state.is_enabled) { 946 MemoryRegion *mr = &pcms->cxl_devices_state.host_mr; 947 hwaddr cxl_size = MiB; 948 949 cxl_base = pc_get_cxl_range_start(pcms); 950 memory_region_init(mr, OBJECT(machine), "cxl_host_reg", cxl_size); 951 memory_region_add_subregion(system_memory, cxl_base, mr); 952 cxl_resv_end = cxl_base + cxl_size; 953 if (pcms->cxl_devices_state.fixed_windows) { 954 hwaddr cxl_fmw_base; 955 GList *it; 956 957 cxl_fmw_base = ROUND_UP(cxl_base + cxl_size, 256 * MiB); 958 for (it = pcms->cxl_devices_state.fixed_windows; it; it = it->next) { 959 CXLFixedWindow *fw = it->data; 960 961 fw->base = cxl_fmw_base; 962 memory_region_init_io(&fw->mr, OBJECT(machine), &cfmws_ops, fw, 963 "cxl-fixed-memory-region", fw->size); 964 memory_region_add_subregion(system_memory, fw->base, &fw->mr); 965 cxl_fmw_base += fw->size; 966 cxl_resv_end = cxl_fmw_base; 967 } 968 } 969 } 970 971 /* Initialize PC system firmware */ 972 pc_system_firmware_init(pcms, rom_memory); 973 974 option_rom_mr = g_malloc(sizeof(*option_rom_mr)); 975 if (machine_require_guest_memfd(machine)) { 976 memory_region_init_ram_guest_memfd(option_rom_mr, NULL, "pc.rom", 977 PC_ROM_SIZE, &error_fatal); 978 } else { 979 memory_region_init_ram(option_rom_mr, NULL, "pc.rom", PC_ROM_SIZE, 980 &error_fatal); 981 if (pcmc->pci_enabled) { 982 memory_region_set_readonly(option_rom_mr, true); 983 } 984 } 985 memory_region_add_subregion_overlap(rom_memory, 986 PC_ROM_MIN_VGA, 987 option_rom_mr, 988 1); 989 990 fw_cfg = fw_cfg_arch_create(machine, 991 x86ms->boot_cpus, x86ms->apic_id_limit); 992 993 rom_set_fw(fw_cfg); 994 995 if (machine->device_memory) { 996 uint64_t *val = g_malloc(sizeof(*val)); 997 uint64_t res_mem_end = machine->device_memory->base; 998 999 if (!pcmc->broken_reserved_end) { 1000 res_mem_end += memory_region_size(&machine->device_memory->mr); 1001 } 1002 1003 if (pcms->cxl_devices_state.is_enabled) { 1004 res_mem_end = cxl_resv_end; 1005 } 1006 *val = cpu_to_le64(ROUND_UP(res_mem_end, 1 * GiB)); 1007 fw_cfg_add_file(fw_cfg, "etc/reserved-memory-end", val, sizeof(*val)); 1008 } 1009 1010 if (linux_boot) { 1011 x86_load_linux(x86ms, fw_cfg, PC_FW_DATA, pcmc->pvh_enabled); 1012 } 1013 1014 for (i = 0; i < nb_option_roms; i++) { 1015 rom_add_option(option_rom[i].name, option_rom[i].bootindex); 1016 } 1017 x86ms->fw_cfg = fw_cfg; 1018 1019 /* Init default IOAPIC address space */ 1020 x86ms->ioapic_as = &address_space_memory; 1021 1022 /* Init ACPI memory hotplug IO base address */ 1023 pcms->memhp_io_base = ACPI_MEMORY_HOTPLUG_BASE; 1024 } 1025 1026 /* 1027 * The 64bit pci hole starts after "above 4G RAM" and 1028 * potentially the space reserved for memory hotplug. 1029 */ 1030 uint64_t pc_pci_hole64_start(void) 1031 { 1032 PCMachineState *pcms = PC_MACHINE(qdev_get_machine()); 1033 PCMachineClass *pcmc = PC_MACHINE_GET_CLASS(pcms); 1034 MachineState *ms = MACHINE(pcms); 1035 uint64_t hole64_start = 0; 1036 ram_addr_t size = 0; 1037 1038 if (pcms->cxl_devices_state.is_enabled) { 1039 hole64_start = pc_get_cxl_range_end(pcms); 1040 } else if (pcmc->has_reserved_memory && (ms->ram_size < ms->maxram_size)) { 1041 pc_get_device_memory_range(pcms, &hole64_start, &size); 1042 if (!pcmc->broken_reserved_end) { 1043 hole64_start += size; 1044 } 1045 } else { 1046 hole64_start = pc_above_4g_end(pcms); 1047 } 1048 1049 return ROUND_UP(hole64_start, 1 * GiB); 1050 } 1051 1052 DeviceState *pc_vga_init(ISABus *isa_bus, PCIBus *pci_bus) 1053 { 1054 DeviceState *dev = NULL; 1055 1056 rom_set_order_override(FW_CFG_ORDER_OVERRIDE_VGA); 1057 if (pci_bus) { 1058 PCIDevice *pcidev = pci_vga_init(pci_bus); 1059 dev = pcidev ? &pcidev->qdev : NULL; 1060 } else if (isa_bus) { 1061 ISADevice *isadev = isa_vga_init(isa_bus); 1062 dev = isadev ? DEVICE(isadev) : NULL; 1063 } 1064 rom_reset_order_override(); 1065 return dev; 1066 } 1067 1068 static const MemoryRegionOps ioport80_io_ops = { 1069 .write = ioport80_write, 1070 .read = ioport80_read, 1071 .endianness = DEVICE_LITTLE_ENDIAN, 1072 .impl = { 1073 .min_access_size = 1, 1074 .max_access_size = 1, 1075 }, 1076 }; 1077 1078 static const MemoryRegionOps ioportF0_io_ops = { 1079 .write = ioportF0_write, 1080 .read = ioportF0_read, 1081 .endianness = DEVICE_LITTLE_ENDIAN, 1082 .impl = { 1083 .min_access_size = 1, 1084 .max_access_size = 1, 1085 }, 1086 }; 1087 1088 static void pc_superio_init(ISABus *isa_bus, bool create_fdctrl, 1089 bool create_i8042, bool no_vmport, Error **errp) 1090 { 1091 int i; 1092 DriveInfo *fd[MAX_FD]; 1093 qemu_irq *a20_line; 1094 ISADevice *i8042, *port92, *vmmouse; 1095 1096 serial_hds_isa_init(isa_bus, 0, MAX_ISA_SERIAL_PORTS); 1097 parallel_hds_isa_init(isa_bus, MAX_PARALLEL_PORTS); 1098 1099 for (i = 0; i < MAX_FD; i++) { 1100 fd[i] = drive_get(IF_FLOPPY, 0, i); 1101 create_fdctrl |= !!fd[i]; 1102 } 1103 if (create_fdctrl) { 1104 #ifdef CONFIG_FDC_ISA 1105 ISADevice *fdc = isa_new(TYPE_ISA_FDC); 1106 if (fdc) { 1107 isa_realize_and_unref(fdc, isa_bus, &error_fatal); 1108 isa_fdc_init_drives(fdc, fd); 1109 } 1110 #endif 1111 } 1112 1113 if (!create_i8042) { 1114 if (!no_vmport) { 1115 error_setg(errp, 1116 "vmport requires the i8042 controller to be enabled"); 1117 } 1118 return; 1119 } 1120 1121 i8042 = isa_create_simple(isa_bus, TYPE_I8042); 1122 if (!no_vmport) { 1123 isa_create_simple(isa_bus, TYPE_VMPORT); 1124 vmmouse = isa_try_new("vmmouse"); 1125 } else { 1126 vmmouse = NULL; 1127 } 1128 if (vmmouse) { 1129 object_property_set_link(OBJECT(vmmouse), TYPE_I8042, OBJECT(i8042), 1130 &error_abort); 1131 isa_realize_and_unref(vmmouse, isa_bus, &error_fatal); 1132 } 1133 port92 = isa_create_simple(isa_bus, TYPE_PORT92); 1134 1135 a20_line = qemu_allocate_irqs(handle_a20_line_change, first_cpu, 2); 1136 qdev_connect_gpio_out_named(DEVICE(i8042), 1137 I8042_A20_LINE, 0, a20_line[0]); 1138 qdev_connect_gpio_out_named(DEVICE(port92), 1139 PORT92_A20_LINE, 0, a20_line[1]); 1140 g_free(a20_line); 1141 } 1142 1143 void pc_basic_device_init(struct PCMachineState *pcms, 1144 ISABus *isa_bus, qemu_irq *gsi, 1145 ISADevice *rtc_state, 1146 bool create_fdctrl, 1147 uint32_t hpet_irqs) 1148 { 1149 int i; 1150 DeviceState *hpet = NULL; 1151 int pit_isa_irq = 0; 1152 qemu_irq pit_alt_irq = NULL; 1153 ISADevice *pit = NULL; 1154 MemoryRegion *ioport80_io = g_new(MemoryRegion, 1); 1155 MemoryRegion *ioportF0_io = g_new(MemoryRegion, 1); 1156 X86MachineState *x86ms = X86_MACHINE(pcms); 1157 1158 memory_region_init_io(ioport80_io, NULL, &ioport80_io_ops, NULL, "ioport80", 1); 1159 memory_region_add_subregion(isa_bus->address_space_io, 0x80, ioport80_io); 1160 1161 memory_region_init_io(ioportF0_io, NULL, &ioportF0_io_ops, NULL, "ioportF0", 1); 1162 memory_region_add_subregion(isa_bus->address_space_io, 0xf0, ioportF0_io); 1163 1164 /* 1165 * Check if an HPET shall be created. 1166 */ 1167 if (pcms->hpet_enabled) { 1168 qemu_irq rtc_irq; 1169 1170 hpet = qdev_try_new(TYPE_HPET); 1171 if (!hpet) { 1172 error_report("couldn't create HPET device"); 1173 exit(1); 1174 } 1175 /* 1176 * For pc-piix-*, hpet's intcap is always IRQ2. For pc-q35-*, 1177 * use IRQ16~23, IRQ8 and IRQ2. If the user has already set 1178 * the property, use whatever mask they specified. 1179 */ 1180 uint8_t compat = object_property_get_uint(OBJECT(hpet), 1181 HPET_INTCAP, NULL); 1182 if (!compat) { 1183 qdev_prop_set_uint32(hpet, HPET_INTCAP, hpet_irqs); 1184 } 1185 sysbus_realize_and_unref(SYS_BUS_DEVICE(hpet), &error_fatal); 1186 sysbus_mmio_map(SYS_BUS_DEVICE(hpet), 0, HPET_BASE); 1187 1188 for (i = 0; i < IOAPIC_NUM_PINS; i++) { 1189 sysbus_connect_irq(SYS_BUS_DEVICE(hpet), i, gsi[i]); 1190 } 1191 pit_isa_irq = -1; 1192 pit_alt_irq = qdev_get_gpio_in(hpet, HPET_LEGACY_PIT_INT); 1193 rtc_irq = qdev_get_gpio_in(hpet, HPET_LEGACY_RTC_INT); 1194 1195 /* overwrite connection created by south bridge */ 1196 qdev_connect_gpio_out(DEVICE(rtc_state), 0, rtc_irq); 1197 } 1198 1199 object_property_add_alias(OBJECT(pcms), "rtc-time", OBJECT(rtc_state), 1200 "date"); 1201 1202 #ifdef CONFIG_XEN_EMU 1203 if (xen_mode == XEN_EMULATE) { 1204 xen_overlay_create(); 1205 xen_evtchn_create(IOAPIC_NUM_PINS, gsi); 1206 xen_gnttab_create(); 1207 xen_xenstore_create(); 1208 if (pcms->pcibus) { 1209 pci_create_simple(pcms->pcibus, -1, "xen-platform"); 1210 } 1211 xen_bus_init(); 1212 } 1213 #endif 1214 1215 qemu_register_boot_set(pc_boot_set, pcms); 1216 set_boot_dev(pcms, MC146818_RTC(rtc_state), 1217 MACHINE(pcms)->boot_config.order, &error_fatal); 1218 1219 if (!xen_enabled() && 1220 (x86ms->pit == ON_OFF_AUTO_AUTO || x86ms->pit == ON_OFF_AUTO_ON)) { 1221 if (kvm_pit_in_kernel()) { 1222 pit = kvm_pit_init(isa_bus, 0x40); 1223 } else { 1224 pit = i8254_pit_init(isa_bus, 0x40, pit_isa_irq, pit_alt_irq); 1225 } 1226 if (hpet) { 1227 /* connect PIT to output control line of the HPET */ 1228 qdev_connect_gpio_out(hpet, 0, qdev_get_gpio_in(DEVICE(pit), 0)); 1229 } 1230 object_property_set_link(OBJECT(pcms->pcspk), "pit", 1231 OBJECT(pit), &error_fatal); 1232 isa_realize_and_unref(pcms->pcspk, isa_bus, &error_fatal); 1233 } 1234 1235 if (pcms->vmport == ON_OFF_AUTO_AUTO) { 1236 pcms->vmport = (xen_enabled() || !pcms->i8042_enabled) 1237 ? ON_OFF_AUTO_OFF : ON_OFF_AUTO_ON; 1238 } 1239 1240 /* Super I/O */ 1241 pc_superio_init(isa_bus, create_fdctrl, pcms->i8042_enabled, 1242 pcms->vmport != ON_OFF_AUTO_ON, &error_fatal); 1243 } 1244 1245 void pc_nic_init(PCMachineClass *pcmc, ISABus *isa_bus, PCIBus *pci_bus) 1246 { 1247 MachineClass *mc = MACHINE_CLASS(pcmc); 1248 bool default_is_ne2k = g_str_equal(mc->default_nic, TYPE_ISA_NE2000); 1249 NICInfo *nd; 1250 1251 rom_set_order_override(FW_CFG_ORDER_OVERRIDE_NIC); 1252 1253 while ((nd = qemu_find_nic_info(TYPE_ISA_NE2000, default_is_ne2k, NULL))) { 1254 pc_init_ne2k_isa(isa_bus, nd, &error_fatal); 1255 } 1256 1257 /* Anything remaining should be a PCI NIC */ 1258 if (pci_bus) { 1259 pci_init_nic_devices(pci_bus, mc->default_nic); 1260 } 1261 1262 rom_reset_order_override(); 1263 } 1264 1265 void pc_i8259_create(ISABus *isa_bus, qemu_irq *i8259_irqs) 1266 { 1267 qemu_irq *i8259; 1268 1269 if (kvm_pic_in_kernel()) { 1270 i8259 = kvm_i8259_init(isa_bus); 1271 } else if (xen_enabled()) { 1272 i8259 = xen_interrupt_controller_init(); 1273 } else { 1274 i8259 = i8259_init(isa_bus, x86_allocate_cpu_irq()); 1275 } 1276 1277 for (size_t i = 0; i < ISA_NUM_IRQS; i++) { 1278 i8259_irqs[i] = i8259[i]; 1279 } 1280 1281 g_free(i8259); 1282 } 1283 1284 static void pc_memory_pre_plug(HotplugHandler *hotplug_dev, DeviceState *dev, 1285 Error **errp) 1286 { 1287 const X86MachineState *x86ms = X86_MACHINE(hotplug_dev); 1288 const MachineState *ms = MACHINE(hotplug_dev); 1289 const bool is_nvdimm = object_dynamic_cast(OBJECT(dev), TYPE_NVDIMM); 1290 Error *local_err = NULL; 1291 1292 /* 1293 * When "acpi=off" is used with the Q35 machine type, no ACPI is built, 1294 * but pcms->acpi_dev is still created. Check !acpi_enabled in 1295 * addition to cover this case. 1296 */ 1297 if (!x86ms->acpi_dev || !x86_machine_is_acpi_enabled(x86ms)) { 1298 error_setg(errp, 1299 "memory hotplug is not enabled: missing acpi device or acpi disabled"); 1300 return; 1301 } 1302 1303 if (is_nvdimm && !ms->nvdimms_state->is_enabled) { 1304 error_setg(errp, "nvdimm is not enabled: missing 'nvdimm' in '-M'"); 1305 return; 1306 } 1307 1308 hotplug_handler_pre_plug(x86ms->acpi_dev, dev, &local_err); 1309 if (local_err) { 1310 error_propagate(errp, local_err); 1311 return; 1312 } 1313 1314 pc_dimm_pre_plug(PC_DIMM(dev), MACHINE(hotplug_dev), errp); 1315 } 1316 1317 static void pc_memory_plug(HotplugHandler *hotplug_dev, 1318 DeviceState *dev, Error **errp) 1319 { 1320 PCMachineState *pcms = PC_MACHINE(hotplug_dev); 1321 X86MachineState *x86ms = X86_MACHINE(hotplug_dev); 1322 MachineState *ms = MACHINE(hotplug_dev); 1323 bool is_nvdimm = object_dynamic_cast(OBJECT(dev), TYPE_NVDIMM); 1324 1325 pc_dimm_plug(PC_DIMM(dev), MACHINE(pcms)); 1326 1327 if (is_nvdimm) { 1328 nvdimm_plug(ms->nvdimms_state); 1329 } 1330 1331 hotplug_handler_plug(x86ms->acpi_dev, dev, &error_abort); 1332 } 1333 1334 static void pc_memory_unplug_request(HotplugHandler *hotplug_dev, 1335 DeviceState *dev, Error **errp) 1336 { 1337 X86MachineState *x86ms = X86_MACHINE(hotplug_dev); 1338 1339 /* 1340 * When "acpi=off" is used with the Q35 machine type, no ACPI is built, 1341 * but pcms->acpi_dev is still created. Check !acpi_enabled in 1342 * addition to cover this case. 1343 */ 1344 if (!x86ms->acpi_dev || !x86_machine_is_acpi_enabled(x86ms)) { 1345 error_setg(errp, 1346 "memory hotplug is not enabled: missing acpi device or acpi disabled"); 1347 return; 1348 } 1349 1350 if (object_dynamic_cast(OBJECT(dev), TYPE_NVDIMM)) { 1351 error_setg(errp, "nvdimm device hot unplug is not supported yet."); 1352 return; 1353 } 1354 1355 hotplug_handler_unplug_request(x86ms->acpi_dev, dev, 1356 errp); 1357 } 1358 1359 static void pc_memory_unplug(HotplugHandler *hotplug_dev, 1360 DeviceState *dev, Error **errp) 1361 { 1362 PCMachineState *pcms = PC_MACHINE(hotplug_dev); 1363 X86MachineState *x86ms = X86_MACHINE(hotplug_dev); 1364 Error *local_err = NULL; 1365 1366 hotplug_handler_unplug(x86ms->acpi_dev, dev, &local_err); 1367 if (local_err) { 1368 goto out; 1369 } 1370 1371 pc_dimm_unplug(PC_DIMM(dev), MACHINE(pcms)); 1372 qdev_unrealize(dev); 1373 out: 1374 error_propagate(errp, local_err); 1375 } 1376 1377 static void pc_hv_balloon_pre_plug(HotplugHandler *hotplug_dev, 1378 DeviceState *dev, Error **errp) 1379 { 1380 /* The vmbus handler has no hotplug handler; we should never end up here. */ 1381 g_assert(!dev->hotplugged); 1382 memory_device_pre_plug(MEMORY_DEVICE(dev), MACHINE(hotplug_dev), errp); 1383 } 1384 1385 static void pc_hv_balloon_plug(HotplugHandler *hotplug_dev, 1386 DeviceState *dev, Error **errp) 1387 { 1388 memory_device_plug(MEMORY_DEVICE(dev), MACHINE(hotplug_dev)); 1389 } 1390 1391 static void pc_machine_device_pre_plug_cb(HotplugHandler *hotplug_dev, 1392 DeviceState *dev, Error **errp) 1393 { 1394 if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM)) { 1395 pc_memory_pre_plug(hotplug_dev, dev, errp); 1396 } else if (object_dynamic_cast(OBJECT(dev), TYPE_CPU)) { 1397 x86_cpu_pre_plug(hotplug_dev, dev, errp); 1398 } else if (object_dynamic_cast(OBJECT(dev), TYPE_VIRTIO_MD_PCI)) { 1399 virtio_md_pci_pre_plug(VIRTIO_MD_PCI(dev), MACHINE(hotplug_dev), errp); 1400 } else if (object_dynamic_cast(OBJECT(dev), TYPE_VIRTIO_IOMMU_PCI)) { 1401 /* Declare the APIC range as the reserved MSI region */ 1402 char *resv_prop_str = g_strdup_printf("0xfee00000:0xfeefffff:%d", 1403 VIRTIO_IOMMU_RESV_MEM_T_MSI); 1404 QList *reserved_regions = qlist_new(); 1405 1406 qlist_append_str(reserved_regions, resv_prop_str); 1407 qdev_prop_set_array(dev, "reserved-regions", reserved_regions); 1408 1409 g_free(resv_prop_str); 1410 } 1411 1412 if (object_dynamic_cast(OBJECT(dev), TYPE_X86_IOMMU_DEVICE) || 1413 object_dynamic_cast(OBJECT(dev), TYPE_VIRTIO_IOMMU_PCI)) { 1414 PCMachineState *pcms = PC_MACHINE(hotplug_dev); 1415 1416 if (pcms->iommu) { 1417 error_setg(errp, "QEMU does not support multiple vIOMMUs " 1418 "for x86 yet."); 1419 return; 1420 } 1421 pcms->iommu = dev; 1422 } else if (object_dynamic_cast(OBJECT(dev), TYPE_HV_BALLOON)) { 1423 pc_hv_balloon_pre_plug(hotplug_dev, dev, errp); 1424 } 1425 } 1426 1427 static void pc_machine_device_plug_cb(HotplugHandler *hotplug_dev, 1428 DeviceState *dev, Error **errp) 1429 { 1430 if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM)) { 1431 pc_memory_plug(hotplug_dev, dev, errp); 1432 } else if (object_dynamic_cast(OBJECT(dev), TYPE_CPU)) { 1433 x86_cpu_plug(hotplug_dev, dev, errp); 1434 } else if (object_dynamic_cast(OBJECT(dev), TYPE_VIRTIO_MD_PCI)) { 1435 virtio_md_pci_plug(VIRTIO_MD_PCI(dev), MACHINE(hotplug_dev), errp); 1436 } else if (object_dynamic_cast(OBJECT(dev), TYPE_HV_BALLOON)) { 1437 pc_hv_balloon_plug(hotplug_dev, dev, errp); 1438 } 1439 } 1440 1441 static void pc_machine_device_unplug_request_cb(HotplugHandler *hotplug_dev, 1442 DeviceState *dev, Error **errp) 1443 { 1444 if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM)) { 1445 pc_memory_unplug_request(hotplug_dev, dev, errp); 1446 } else if (object_dynamic_cast(OBJECT(dev), TYPE_CPU)) { 1447 x86_cpu_unplug_request_cb(hotplug_dev, dev, errp); 1448 } else if (object_dynamic_cast(OBJECT(dev), TYPE_VIRTIO_MD_PCI)) { 1449 virtio_md_pci_unplug_request(VIRTIO_MD_PCI(dev), MACHINE(hotplug_dev), 1450 errp); 1451 } else { 1452 error_setg(errp, "acpi: device unplug request for not supported device" 1453 " type: %s", object_get_typename(OBJECT(dev))); 1454 } 1455 } 1456 1457 static void pc_machine_device_unplug_cb(HotplugHandler *hotplug_dev, 1458 DeviceState *dev, Error **errp) 1459 { 1460 if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM)) { 1461 pc_memory_unplug(hotplug_dev, dev, errp); 1462 } else if (object_dynamic_cast(OBJECT(dev), TYPE_CPU)) { 1463 x86_cpu_unplug_cb(hotplug_dev, dev, errp); 1464 } else if (object_dynamic_cast(OBJECT(dev), TYPE_VIRTIO_MD_PCI)) { 1465 virtio_md_pci_unplug(VIRTIO_MD_PCI(dev), MACHINE(hotplug_dev), errp); 1466 } else { 1467 error_setg(errp, "acpi: device unplug for not supported device" 1468 " type: %s", object_get_typename(OBJECT(dev))); 1469 } 1470 } 1471 1472 static HotplugHandler *pc_get_hotplug_handler(MachineState *machine, 1473 DeviceState *dev) 1474 { 1475 if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM) || 1476 object_dynamic_cast(OBJECT(dev), TYPE_CPU) || 1477 object_dynamic_cast(OBJECT(dev), TYPE_VIRTIO_MD_PCI) || 1478 object_dynamic_cast(OBJECT(dev), TYPE_VIRTIO_IOMMU_PCI) || 1479 object_dynamic_cast(OBJECT(dev), TYPE_HV_BALLOON) || 1480 object_dynamic_cast(OBJECT(dev), TYPE_X86_IOMMU_DEVICE)) { 1481 return HOTPLUG_HANDLER(machine); 1482 } 1483 1484 return NULL; 1485 } 1486 1487 static void pc_machine_get_vmport(Object *obj, Visitor *v, const char *name, 1488 void *opaque, Error **errp) 1489 { 1490 PCMachineState *pcms = PC_MACHINE(obj); 1491 OnOffAuto vmport = pcms->vmport; 1492 1493 visit_type_OnOffAuto(v, name, &vmport, errp); 1494 } 1495 1496 static void pc_machine_set_vmport(Object *obj, Visitor *v, const char *name, 1497 void *opaque, Error **errp) 1498 { 1499 PCMachineState *pcms = PC_MACHINE(obj); 1500 1501 visit_type_OnOffAuto(v, name, &pcms->vmport, errp); 1502 } 1503 1504 static bool pc_machine_get_fd_bootchk(Object *obj, Error **errp) 1505 { 1506 PCMachineState *pcms = PC_MACHINE(obj); 1507 1508 return pcms->fd_bootchk; 1509 } 1510 1511 static void pc_machine_set_fd_bootchk(Object *obj, bool value, Error **errp) 1512 { 1513 PCMachineState *pcms = PC_MACHINE(obj); 1514 1515 pcms->fd_bootchk = value; 1516 } 1517 1518 static bool pc_machine_get_smbus(Object *obj, Error **errp) 1519 { 1520 PCMachineState *pcms = PC_MACHINE(obj); 1521 1522 return pcms->smbus_enabled; 1523 } 1524 1525 static void pc_machine_set_smbus(Object *obj, bool value, Error **errp) 1526 { 1527 PCMachineState *pcms = PC_MACHINE(obj); 1528 1529 pcms->smbus_enabled = value; 1530 } 1531 1532 static bool pc_machine_get_sata(Object *obj, Error **errp) 1533 { 1534 PCMachineState *pcms = PC_MACHINE(obj); 1535 1536 return pcms->sata_enabled; 1537 } 1538 1539 static void pc_machine_set_sata(Object *obj, bool value, Error **errp) 1540 { 1541 PCMachineState *pcms = PC_MACHINE(obj); 1542 1543 pcms->sata_enabled = value; 1544 } 1545 1546 static bool pc_machine_get_hpet(Object *obj, Error **errp) 1547 { 1548 PCMachineState *pcms = PC_MACHINE(obj); 1549 1550 return pcms->hpet_enabled; 1551 } 1552 1553 static void pc_machine_set_hpet(Object *obj, bool value, Error **errp) 1554 { 1555 PCMachineState *pcms = PC_MACHINE(obj); 1556 1557 pcms->hpet_enabled = value; 1558 } 1559 1560 static bool pc_machine_get_i8042(Object *obj, Error **errp) 1561 { 1562 PCMachineState *pcms = PC_MACHINE(obj); 1563 1564 return pcms->i8042_enabled; 1565 } 1566 1567 static void pc_machine_set_i8042(Object *obj, bool value, Error **errp) 1568 { 1569 PCMachineState *pcms = PC_MACHINE(obj); 1570 1571 pcms->i8042_enabled = value; 1572 } 1573 1574 static bool pc_machine_get_default_bus_bypass_iommu(Object *obj, Error **errp) 1575 { 1576 PCMachineState *pcms = PC_MACHINE(obj); 1577 1578 return pcms->default_bus_bypass_iommu; 1579 } 1580 1581 static void pc_machine_set_default_bus_bypass_iommu(Object *obj, bool value, 1582 Error **errp) 1583 { 1584 PCMachineState *pcms = PC_MACHINE(obj); 1585 1586 pcms->default_bus_bypass_iommu = value; 1587 } 1588 1589 static void pc_machine_get_smbios_ep(Object *obj, Visitor *v, const char *name, 1590 void *opaque, Error **errp) 1591 { 1592 PCMachineState *pcms = PC_MACHINE(obj); 1593 SmbiosEntryPointType smbios_entry_point_type = pcms->smbios_entry_point_type; 1594 1595 visit_type_SmbiosEntryPointType(v, name, &smbios_entry_point_type, errp); 1596 } 1597 1598 static void pc_machine_set_smbios_ep(Object *obj, Visitor *v, const char *name, 1599 void *opaque, Error **errp) 1600 { 1601 PCMachineState *pcms = PC_MACHINE(obj); 1602 1603 visit_type_SmbiosEntryPointType(v, name, &pcms->smbios_entry_point_type, errp); 1604 } 1605 1606 static void pc_machine_get_max_ram_below_4g(Object *obj, Visitor *v, 1607 const char *name, void *opaque, 1608 Error **errp) 1609 { 1610 PCMachineState *pcms = PC_MACHINE(obj); 1611 uint64_t value = pcms->max_ram_below_4g; 1612 1613 visit_type_size(v, name, &value, errp); 1614 } 1615 1616 static void pc_machine_set_max_ram_below_4g(Object *obj, Visitor *v, 1617 const char *name, void *opaque, 1618 Error **errp) 1619 { 1620 PCMachineState *pcms = PC_MACHINE(obj); 1621 uint64_t value; 1622 1623 if (!visit_type_size(v, name, &value, errp)) { 1624 return; 1625 } 1626 if (value > 4 * GiB) { 1627 error_setg(errp, 1628 "Machine option 'max-ram-below-4g=%"PRIu64 1629 "' expects size less than or equal to 4G", value); 1630 return; 1631 } 1632 1633 if (value < 1 * MiB) { 1634 warn_report("Only %" PRIu64 " bytes of RAM below the 4GiB boundary," 1635 "BIOS may not work with less than 1MiB", value); 1636 } 1637 1638 pcms->max_ram_below_4g = value; 1639 } 1640 1641 static void pc_machine_get_max_fw_size(Object *obj, Visitor *v, 1642 const char *name, void *opaque, 1643 Error **errp) 1644 { 1645 PCMachineState *pcms = PC_MACHINE(obj); 1646 uint64_t value = pcms->max_fw_size; 1647 1648 visit_type_size(v, name, &value, errp); 1649 } 1650 1651 static void pc_machine_set_max_fw_size(Object *obj, Visitor *v, 1652 const char *name, void *opaque, 1653 Error **errp) 1654 { 1655 PCMachineState *pcms = PC_MACHINE(obj); 1656 uint64_t value; 1657 1658 if (!visit_type_size(v, name, &value, errp)) { 1659 return; 1660 } 1661 1662 /* 1663 * We don't have a theoretically justifiable exact lower bound on the base 1664 * address of any flash mapping. In practice, the IO-APIC MMIO range is 1665 * [0xFEE00000..0xFEE01000] -- see IO_APIC_DEFAULT_ADDRESS --, leaving free 1666 * only 18MiB-4KiB below 4GiB. For now, restrict the cumulative mapping to 1667 * 16MiB in size. 1668 */ 1669 if (value > 16 * MiB) { 1670 error_setg(errp, 1671 "User specified max allowed firmware size %" PRIu64 " is " 1672 "greater than 16MiB. If combined firmware size exceeds " 1673 "16MiB the system may not boot, or experience intermittent" 1674 "stability issues.", 1675 value); 1676 return; 1677 } 1678 1679 pcms->max_fw_size = value; 1680 } 1681 1682 1683 static void pc_machine_initfn(Object *obj) 1684 { 1685 PCMachineState *pcms = PC_MACHINE(obj); 1686 PCMachineClass *pcmc = PC_MACHINE_GET_CLASS(pcms); 1687 1688 #ifdef CONFIG_VMPORT 1689 pcms->vmport = ON_OFF_AUTO_AUTO; 1690 #else 1691 pcms->vmport = ON_OFF_AUTO_OFF; 1692 #endif /* CONFIG_VMPORT */ 1693 pcms->max_ram_below_4g = 0; /* use default */ 1694 pcms->smbios_entry_point_type = pcmc->default_smbios_ep_type; 1695 pcms->south_bridge = pcmc->default_south_bridge; 1696 1697 /* acpi build is enabled by default if machine supports it */ 1698 pcms->acpi_build_enabled = pcmc->has_acpi_build; 1699 pcms->smbus_enabled = true; 1700 pcms->sata_enabled = true; 1701 pcms->i8042_enabled = true; 1702 pcms->max_fw_size = 8 * MiB; 1703 #ifdef CONFIG_HPET 1704 pcms->hpet_enabled = true; 1705 #endif 1706 pcms->fd_bootchk = true; 1707 pcms->default_bus_bypass_iommu = false; 1708 1709 pc_system_flash_create(pcms); 1710 pcms->pcspk = isa_new(TYPE_PC_SPEAKER); 1711 object_property_add_alias(OBJECT(pcms), "pcspk-audiodev", 1712 OBJECT(pcms->pcspk), "audiodev"); 1713 if (pcmc->pci_enabled) { 1714 cxl_machine_init(obj, &pcms->cxl_devices_state); 1715 } 1716 1717 pcms->machine_done.notify = pc_machine_done; 1718 qemu_add_machine_init_done_notifier(&pcms->machine_done); 1719 } 1720 1721 static void pc_machine_reset(MachineState *machine, ResetType type) 1722 { 1723 CPUState *cs; 1724 X86CPU *cpu; 1725 1726 qemu_devices_reset(type); 1727 1728 /* Reset APIC after devices have been reset to cancel 1729 * any changes that qemu_devices_reset() might have done. 1730 */ 1731 CPU_FOREACH(cs) { 1732 cpu = X86_CPU(cs); 1733 1734 x86_cpu_after_reset(cpu); 1735 } 1736 } 1737 1738 static void pc_machine_wakeup(MachineState *machine) 1739 { 1740 cpu_synchronize_all_states(); 1741 pc_machine_reset(machine, RESET_TYPE_WAKEUP); 1742 cpu_synchronize_all_post_reset(); 1743 } 1744 1745 static bool pc_hotplug_allowed(MachineState *ms, DeviceState *dev, Error **errp) 1746 { 1747 X86IOMMUState *iommu = x86_iommu_get_default(); 1748 IntelIOMMUState *intel_iommu; 1749 1750 if (iommu && 1751 object_dynamic_cast((Object *)iommu, TYPE_INTEL_IOMMU_DEVICE) && 1752 object_dynamic_cast((Object *)dev, "vfio-pci")) { 1753 intel_iommu = INTEL_IOMMU_DEVICE(iommu); 1754 if (!intel_iommu->caching_mode) { 1755 error_setg(errp, "Device assignment is not allowed without " 1756 "enabling caching-mode=on for Intel IOMMU."); 1757 return false; 1758 } 1759 } 1760 1761 return true; 1762 } 1763 1764 static void pc_machine_class_init(ObjectClass *oc, void *data) 1765 { 1766 MachineClass *mc = MACHINE_CLASS(oc); 1767 X86MachineClass *x86mc = X86_MACHINE_CLASS(oc); 1768 PCMachineClass *pcmc = PC_MACHINE_CLASS(oc); 1769 HotplugHandlerClass *hc = HOTPLUG_HANDLER_CLASS(oc); 1770 1771 pcmc->pci_enabled = true; 1772 pcmc->has_acpi_build = true; 1773 pcmc->smbios_defaults = true; 1774 pcmc->gigabyte_align = true; 1775 pcmc->has_reserved_memory = true; 1776 pcmc->enforce_amd_1tb_hole = true; 1777 pcmc->isa_bios_alias = true; 1778 pcmc->pvh_enabled = true; 1779 pcmc->kvmclock_create_always = true; 1780 x86mc->apic_xrupt_override = true; 1781 assert(!mc->get_hotplug_handler); 1782 mc->get_hotplug_handler = pc_get_hotplug_handler; 1783 mc->hotplug_allowed = pc_hotplug_allowed; 1784 mc->auto_enable_numa_with_memhp = true; 1785 mc->auto_enable_numa_with_memdev = true; 1786 mc->has_hotpluggable_cpus = true; 1787 mc->default_boot_order = "cad"; 1788 mc->block_default_type = IF_IDE; 1789 mc->max_cpus = 255; 1790 mc->reset = pc_machine_reset; 1791 mc->wakeup = pc_machine_wakeup; 1792 hc->pre_plug = pc_machine_device_pre_plug_cb; 1793 hc->plug = pc_machine_device_plug_cb; 1794 hc->unplug_request = pc_machine_device_unplug_request_cb; 1795 hc->unplug = pc_machine_device_unplug_cb; 1796 mc->default_cpu_type = TARGET_DEFAULT_CPU_TYPE; 1797 mc->nvdimm_supported = true; 1798 mc->smp_props.dies_supported = true; 1799 mc->smp_props.modules_supported = true; 1800 mc->default_ram_id = "pc.ram"; 1801 pcmc->default_smbios_ep_type = SMBIOS_ENTRY_POINT_TYPE_AUTO; 1802 1803 object_class_property_add(oc, PC_MACHINE_MAX_RAM_BELOW_4G, "size", 1804 pc_machine_get_max_ram_below_4g, pc_machine_set_max_ram_below_4g, 1805 NULL, NULL); 1806 object_class_property_set_description(oc, PC_MACHINE_MAX_RAM_BELOW_4G, 1807 "Maximum ram below the 4G boundary (32bit boundary)"); 1808 1809 object_class_property_add(oc, PC_MACHINE_VMPORT, "OnOffAuto", 1810 pc_machine_get_vmport, pc_machine_set_vmport, 1811 NULL, NULL); 1812 object_class_property_set_description(oc, PC_MACHINE_VMPORT, 1813 "Enable vmport (pc & q35)"); 1814 1815 object_class_property_add_bool(oc, PC_MACHINE_SMBUS, 1816 pc_machine_get_smbus, pc_machine_set_smbus); 1817 object_class_property_set_description(oc, PC_MACHINE_SMBUS, 1818 "Enable/disable system management bus"); 1819 1820 object_class_property_add_bool(oc, PC_MACHINE_SATA, 1821 pc_machine_get_sata, pc_machine_set_sata); 1822 object_class_property_set_description(oc, PC_MACHINE_SATA, 1823 "Enable/disable Serial ATA bus"); 1824 1825 object_class_property_add_bool(oc, "hpet", 1826 pc_machine_get_hpet, pc_machine_set_hpet); 1827 object_class_property_set_description(oc, "hpet", 1828 "Enable/disable high precision event timer emulation"); 1829 1830 object_class_property_add_bool(oc, PC_MACHINE_I8042, 1831 pc_machine_get_i8042, pc_machine_set_i8042); 1832 object_class_property_set_description(oc, PC_MACHINE_I8042, 1833 "Enable/disable Intel 8042 PS/2 controller emulation"); 1834 1835 object_class_property_add_bool(oc, "default-bus-bypass-iommu", 1836 pc_machine_get_default_bus_bypass_iommu, 1837 pc_machine_set_default_bus_bypass_iommu); 1838 1839 object_class_property_add(oc, PC_MACHINE_MAX_FW_SIZE, "size", 1840 pc_machine_get_max_fw_size, pc_machine_set_max_fw_size, 1841 NULL, NULL); 1842 object_class_property_set_description(oc, PC_MACHINE_MAX_FW_SIZE, 1843 "Maximum combined firmware size"); 1844 1845 object_class_property_add(oc, PC_MACHINE_SMBIOS_EP, "str", 1846 pc_machine_get_smbios_ep, pc_machine_set_smbios_ep, 1847 NULL, NULL); 1848 object_class_property_set_description(oc, PC_MACHINE_SMBIOS_EP, 1849 "SMBIOS Entry Point type [32, 64]"); 1850 1851 object_class_property_add_bool(oc, "fd-bootchk", 1852 pc_machine_get_fd_bootchk, 1853 pc_machine_set_fd_bootchk); 1854 } 1855 1856 static const TypeInfo pc_machine_info = { 1857 .name = TYPE_PC_MACHINE, 1858 .parent = TYPE_X86_MACHINE, 1859 .abstract = true, 1860 .instance_size = sizeof(PCMachineState), 1861 .instance_init = pc_machine_initfn, 1862 .class_size = sizeof(PCMachineClass), 1863 .class_init = pc_machine_class_init, 1864 .interfaces = (InterfaceInfo[]) { 1865 { TYPE_HOTPLUG_HANDLER }, 1866 { } 1867 }, 1868 }; 1869 1870 static void pc_machine_register_types(void) 1871 { 1872 type_register_static(&pc_machine_info); 1873 } 1874 1875 type_init(pc_machine_register_types) 1876