1 /* 2 * QEMU PC System Emulator 3 * 4 * Copyright (c) 2003-2004 Fabrice Bellard 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a copy 7 * of this software and associated documentation files (the "Software"), to deal 8 * in the Software without restriction, including without limitation the rights 9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 10 * copies of the Software, and to permit persons to whom the Software is 11 * furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice shall be included in 14 * all copies or substantial portions of the Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN 22 * THE SOFTWARE. 23 */ 24 25 #include "qemu/osdep.h" 26 #include "qemu/units.h" 27 #include "exec/target_page.h" 28 #include "hw/i386/pc.h" 29 #include "hw/char/serial-isa.h" 30 #include "hw/char/parallel.h" 31 #include "hw/hyperv/hv-balloon.h" 32 #include "hw/i386/fw_cfg.h" 33 #include "hw/i386/vmport.h" 34 #include "system/cpus.h" 35 #include "hw/ide/ide-bus.h" 36 #include "hw/timer/hpet.h" 37 #include "hw/loader.h" 38 #include "hw/rtc/mc146818rtc.h" 39 #include "hw/intc/i8259.h" 40 #include "hw/timer/i8254.h" 41 #include "hw/input/i8042.h" 42 #include "hw/audio/pcspk.h" 43 #include "system/system.h" 44 #include "system/xen.h" 45 #include "system/reset.h" 46 #include "kvm/kvm_i386.h" 47 #include "hw/xen/xen.h" 48 #include "qobject/qlist.h" 49 #include "qemu/error-report.h" 50 #include "hw/acpi/cpu_hotplug.h" 51 #include "acpi-build.h" 52 #include "hw/mem/nvdimm.h" 53 #include "hw/cxl/cxl_host.h" 54 #include "hw/usb.h" 55 #include "hw/i386/intel_iommu.h" 56 #include "hw/net/ne2000-isa.h" 57 #include "hw/virtio/virtio-iommu.h" 58 #include "hw/virtio/virtio-md-pci.h" 59 #include "hw/i386/kvm/xen_overlay.h" 60 #include "hw/i386/kvm/xen_evtchn.h" 61 #include "hw/i386/kvm/xen_gnttab.h" 62 #include "hw/i386/kvm/xen_xenstore.h" 63 #include "hw/mem/memory-device.h" 64 #include "e820_memory_layout.h" 65 #include "trace.h" 66 #include "sev.h" 67 #include CONFIG_DEVICES 68 69 #ifdef CONFIG_XEN_EMU 70 #include "hw/xen/xen-legacy-backend.h" 71 #include "hw/xen/xen-bus.h" 72 #endif 73 74 /* 75 * Helper for setting model-id for CPU models that changed model-id 76 * depending on QEMU versions up to QEMU 2.4. 77 */ 78 #define PC_CPU_MODEL_IDS(v) \ 79 { "qemu32-" TYPE_X86_CPU, "model-id", "QEMU Virtual CPU version " v, },\ 80 { "qemu64-" TYPE_X86_CPU, "model-id", "QEMU Virtual CPU version " v, },\ 81 { "athlon-" TYPE_X86_CPU, "model-id", "QEMU Virtual CPU version " v, }, 82 83 GlobalProperty pc_compat_10_0[] = {}; 84 const size_t pc_compat_10_0_len = G_N_ELEMENTS(pc_compat_10_0); 85 86 GlobalProperty pc_compat_9_2[] = {}; 87 const size_t pc_compat_9_2_len = G_N_ELEMENTS(pc_compat_9_2); 88 89 GlobalProperty pc_compat_9_1[] = { 90 { "ICH9-LPC", "x-smi-swsmi-timer", "off" }, 91 { "ICH9-LPC", "x-smi-periodic-timer", "off" }, 92 { TYPE_INTEL_IOMMU_DEVICE, "stale-tm", "on" }, 93 { TYPE_INTEL_IOMMU_DEVICE, "aw-bits", "39" }, 94 }; 95 const size_t pc_compat_9_1_len = G_N_ELEMENTS(pc_compat_9_1); 96 97 GlobalProperty pc_compat_9_0[] = { 98 { TYPE_X86_CPU, "x-amd-topoext-features-only", "false" }, 99 { TYPE_X86_CPU, "x-l1-cache-per-thread", "false" }, 100 { TYPE_X86_CPU, "guest-phys-bits", "0" }, 101 { "sev-guest", "legacy-vm-type", "on" }, 102 { TYPE_X86_CPU, "legacy-multi-node", "on" }, 103 }; 104 const size_t pc_compat_9_0_len = G_N_ELEMENTS(pc_compat_9_0); 105 106 GlobalProperty pc_compat_8_2[] = {}; 107 const size_t pc_compat_8_2_len = G_N_ELEMENTS(pc_compat_8_2); 108 109 GlobalProperty pc_compat_8_1[] = {}; 110 const size_t pc_compat_8_1_len = G_N_ELEMENTS(pc_compat_8_1); 111 112 GlobalProperty pc_compat_8_0[] = { 113 { "virtio-mem", "unplugged-inaccessible", "auto" }, 114 }; 115 const size_t pc_compat_8_0_len = G_N_ELEMENTS(pc_compat_8_0); 116 117 GlobalProperty pc_compat_7_2[] = { 118 { "ICH9-LPC", "noreboot", "true" }, 119 }; 120 const size_t pc_compat_7_2_len = G_N_ELEMENTS(pc_compat_7_2); 121 122 GlobalProperty pc_compat_7_1[] = {}; 123 const size_t pc_compat_7_1_len = G_N_ELEMENTS(pc_compat_7_1); 124 125 GlobalProperty pc_compat_7_0[] = {}; 126 const size_t pc_compat_7_0_len = G_N_ELEMENTS(pc_compat_7_0); 127 128 GlobalProperty pc_compat_6_2[] = { 129 { "virtio-mem", "unplugged-inaccessible", "off" }, 130 }; 131 const size_t pc_compat_6_2_len = G_N_ELEMENTS(pc_compat_6_2); 132 133 GlobalProperty pc_compat_6_1[] = { 134 { TYPE_X86_CPU, "hv-version-id-build", "0x1bbc" }, 135 { TYPE_X86_CPU, "hv-version-id-major", "0x0006" }, 136 { TYPE_X86_CPU, "hv-version-id-minor", "0x0001" }, 137 { "ICH9-LPC", "x-keep-pci-slot-hpc", "false" }, 138 }; 139 const size_t pc_compat_6_1_len = G_N_ELEMENTS(pc_compat_6_1); 140 141 GlobalProperty pc_compat_6_0[] = { 142 { "qemu64" "-" TYPE_X86_CPU, "family", "6" }, 143 { "qemu64" "-" TYPE_X86_CPU, "model", "6" }, 144 { "qemu64" "-" TYPE_X86_CPU, "stepping", "3" }, 145 { TYPE_X86_CPU, "x-vendor-cpuid-only", "off" }, 146 { "ICH9-LPC", ACPI_PM_PROP_ACPI_PCIHP_BRIDGE, "off" }, 147 { "ICH9-LPC", "x-keep-pci-slot-hpc", "true" }, 148 }; 149 const size_t pc_compat_6_0_len = G_N_ELEMENTS(pc_compat_6_0); 150 151 GlobalProperty pc_compat_5_2[] = { 152 { "ICH9-LPC", "x-smi-cpu-hotunplug", "off" }, 153 }; 154 const size_t pc_compat_5_2_len = G_N_ELEMENTS(pc_compat_5_2); 155 156 GlobalProperty pc_compat_5_1[] = { 157 { "ICH9-LPC", "x-smi-cpu-hotplug", "off" }, 158 { TYPE_X86_CPU, "kvm-msi-ext-dest-id", "off" }, 159 }; 160 const size_t pc_compat_5_1_len = G_N_ELEMENTS(pc_compat_5_1); 161 162 GlobalProperty pc_compat_5_0[] = { 163 }; 164 const size_t pc_compat_5_0_len = G_N_ELEMENTS(pc_compat_5_0); 165 166 GlobalProperty pc_compat_4_2[] = { 167 { "mch", "smbase-smram", "off" }, 168 }; 169 const size_t pc_compat_4_2_len = G_N_ELEMENTS(pc_compat_4_2); 170 171 GlobalProperty pc_compat_4_1[] = {}; 172 const size_t pc_compat_4_1_len = G_N_ELEMENTS(pc_compat_4_1); 173 174 GlobalProperty pc_compat_4_0[] = {}; 175 const size_t pc_compat_4_0_len = G_N_ELEMENTS(pc_compat_4_0); 176 177 GlobalProperty pc_compat_3_1[] = { 178 { "intel-iommu", "dma-drain", "off" }, 179 { "Opteron_G3" "-" TYPE_X86_CPU, "rdtscp", "off" }, 180 { "Opteron_G4" "-" TYPE_X86_CPU, "rdtscp", "off" }, 181 { "Opteron_G4" "-" TYPE_X86_CPU, "npt", "off" }, 182 { "Opteron_G4" "-" TYPE_X86_CPU, "nrip-save", "off" }, 183 { "Opteron_G5" "-" TYPE_X86_CPU, "rdtscp", "off" }, 184 { "Opteron_G5" "-" TYPE_X86_CPU, "npt", "off" }, 185 { "Opteron_G5" "-" TYPE_X86_CPU, "nrip-save", "off" }, 186 { "EPYC" "-" TYPE_X86_CPU, "npt", "off" }, 187 { "EPYC" "-" TYPE_X86_CPU, "nrip-save", "off" }, 188 { "EPYC-IBPB" "-" TYPE_X86_CPU, "npt", "off" }, 189 { "EPYC-IBPB" "-" TYPE_X86_CPU, "nrip-save", "off" }, 190 { "Skylake-Client" "-" TYPE_X86_CPU, "mpx", "on" }, 191 { "Skylake-Client-IBRS" "-" TYPE_X86_CPU, "mpx", "on" }, 192 { "Skylake-Server" "-" TYPE_X86_CPU, "mpx", "on" }, 193 { "Skylake-Server-IBRS" "-" TYPE_X86_CPU, "mpx", "on" }, 194 { "Cascadelake-Server" "-" TYPE_X86_CPU, "mpx", "on" }, 195 { "Icelake-Client" "-" TYPE_X86_CPU, "mpx", "on" }, 196 { "Icelake-Server" "-" TYPE_X86_CPU, "mpx", "on" }, 197 { "Cascadelake-Server" "-" TYPE_X86_CPU, "stepping", "5" }, 198 { TYPE_X86_CPU, "x-intel-pt-auto-level", "off" }, 199 }; 200 const size_t pc_compat_3_1_len = G_N_ELEMENTS(pc_compat_3_1); 201 202 GlobalProperty pc_compat_3_0[] = { 203 { TYPE_X86_CPU, "x-hv-synic-kvm-only", "on" }, 204 { "Skylake-Server" "-" TYPE_X86_CPU, "pku", "off" }, 205 { "Skylake-Server-IBRS" "-" TYPE_X86_CPU, "pku", "off" }, 206 }; 207 const size_t pc_compat_3_0_len = G_N_ELEMENTS(pc_compat_3_0); 208 209 GlobalProperty pc_compat_2_12[] = { 210 { TYPE_X86_CPU, "legacy-cache", "on" }, 211 { TYPE_X86_CPU, "topoext", "off" }, 212 { "EPYC-" TYPE_X86_CPU, "xlevel", "0x8000000a" }, 213 { "EPYC-IBPB-" TYPE_X86_CPU, "xlevel", "0x8000000a" }, 214 }; 215 const size_t pc_compat_2_12_len = G_N_ELEMENTS(pc_compat_2_12); 216 217 GlobalProperty pc_compat_2_11[] = { 218 { TYPE_X86_CPU, "x-migrate-smi-count", "off" }, 219 { "Skylake-Server" "-" TYPE_X86_CPU, "clflushopt", "off" }, 220 }; 221 const size_t pc_compat_2_11_len = G_N_ELEMENTS(pc_compat_2_11); 222 223 GlobalProperty pc_compat_2_10[] = { 224 { TYPE_X86_CPU, "x-hv-max-vps", "0x40" }, 225 { "i440FX-pcihost", "x-pci-hole64-fix", "off" }, 226 { "q35-pcihost", "x-pci-hole64-fix", "off" }, 227 }; 228 const size_t pc_compat_2_10_len = G_N_ELEMENTS(pc_compat_2_10); 229 230 GlobalProperty pc_compat_2_9[] = { 231 { "mch", "extended-tseg-mbytes", "0" }, 232 }; 233 const size_t pc_compat_2_9_len = G_N_ELEMENTS(pc_compat_2_9); 234 235 GlobalProperty pc_compat_2_8[] = { 236 { TYPE_X86_CPU, "tcg-cpuid", "off" }, 237 { "kvmclock", "x-mach-use-reliable-get-clock", "off" }, 238 { "ICH9-LPC", "x-smi-broadcast", "off" }, 239 { TYPE_X86_CPU, "vmware-cpuid-freq", "off" }, 240 { "Haswell-" TYPE_X86_CPU, "stepping", "1" }, 241 }; 242 const size_t pc_compat_2_8_len = G_N_ELEMENTS(pc_compat_2_8); 243 244 GlobalProperty pc_compat_2_7[] = { 245 { TYPE_X86_CPU, "l3-cache", "off" }, 246 { TYPE_X86_CPU, "full-cpuid-auto-level", "off" }, 247 { "Opteron_G3" "-" TYPE_X86_CPU, "family", "15" }, 248 { "Opteron_G3" "-" TYPE_X86_CPU, "model", "6" }, 249 { "Opteron_G3" "-" TYPE_X86_CPU, "stepping", "1" }, 250 { "isa-pcspk", "migrate", "off" }, 251 }; 252 const size_t pc_compat_2_7_len = G_N_ELEMENTS(pc_compat_2_7); 253 254 GlobalProperty pc_compat_2_6[] = { 255 { TYPE_X86_CPU, "cpuid-0xb", "off" }, 256 { "vmxnet3", "romfile", "" }, 257 { TYPE_X86_CPU, "fill-mtrr-mask", "off" }, 258 { "apic-common", "legacy-instance-id", "on", } 259 }; 260 const size_t pc_compat_2_6_len = G_N_ELEMENTS(pc_compat_2_6); 261 262 GlobalProperty pc_compat_2_5[] = {}; 263 const size_t pc_compat_2_5_len = G_N_ELEMENTS(pc_compat_2_5); 264 265 GlobalProperty pc_compat_2_4[] = { 266 PC_CPU_MODEL_IDS("2.4.0") 267 { "Haswell-" TYPE_X86_CPU, "abm", "off" }, 268 { "Haswell-noTSX-" TYPE_X86_CPU, "abm", "off" }, 269 { "Broadwell-" TYPE_X86_CPU, "abm", "off" }, 270 { "Broadwell-noTSX-" TYPE_X86_CPU, "abm", "off" }, 271 { "host" "-" TYPE_X86_CPU, "host-cache-info", "on" }, 272 { TYPE_X86_CPU, "check", "off" }, 273 { "qemu64" "-" TYPE_X86_CPU, "sse4a", "on" }, 274 { "qemu64" "-" TYPE_X86_CPU, "abm", "on" }, 275 { "qemu64" "-" TYPE_X86_CPU, "popcnt", "on" }, 276 { "qemu32" "-" TYPE_X86_CPU, "popcnt", "on" }, 277 { "Opteron_G2" "-" TYPE_X86_CPU, "rdtscp", "on" }, 278 { "Opteron_G3" "-" TYPE_X86_CPU, "rdtscp", "on" }, 279 { "Opteron_G4" "-" TYPE_X86_CPU, "rdtscp", "on" }, 280 { "Opteron_G5" "-" TYPE_X86_CPU, "rdtscp", "on", } 281 }; 282 const size_t pc_compat_2_4_len = G_N_ELEMENTS(pc_compat_2_4); 283 284 /* 285 * @PC_FW_DATA: 286 * Size of the chunk of memory at the top of RAM for the BIOS ACPI tables 287 * and other BIOS datastructures. 288 * 289 * BIOS ACPI tables: 128K. Other BIOS datastructures: less than 4K 290 * reported to be used at the moment, 32K should be enough for a while. 291 */ 292 #define PC_FW_DATA (0x20000 + 0x8000) 293 294 GSIState *pc_gsi_create(qemu_irq **irqs, bool pci_enabled) 295 { 296 GSIState *s; 297 298 s = g_new0(GSIState, 1); 299 if (kvm_ioapic_in_kernel()) { 300 kvm_pc_setup_irq_routing(pci_enabled); 301 } 302 *irqs = qemu_allocate_irqs(gsi_handler, s, IOAPIC_NUM_PINS); 303 304 return s; 305 } 306 307 static void ioport80_write(void *opaque, hwaddr addr, uint64_t data, 308 unsigned size) 309 { 310 } 311 312 static uint64_t ioport80_read(void *opaque, hwaddr addr, unsigned size) 313 { 314 return 0xffffffffffffffffULL; 315 } 316 317 /* MS-DOS compatibility mode FPU exception support */ 318 static void ioportF0_write(void *opaque, hwaddr addr, uint64_t data, 319 unsigned size) 320 { 321 if (tcg_enabled()) { 322 cpu_set_ignne(); 323 } 324 } 325 326 static uint64_t ioportF0_read(void *opaque, hwaddr addr, unsigned size) 327 { 328 return 0xffffffffffffffffULL; 329 } 330 331 /* PC cmos mappings */ 332 333 #define REG_EQUIPMENT_BYTE 0x14 334 335 static void cmos_init_hd(MC146818RtcState *s, int type_ofs, int info_ofs, 336 int16_t cylinders, int8_t heads, int8_t sectors) 337 { 338 mc146818rtc_set_cmos_data(s, type_ofs, 47); 339 mc146818rtc_set_cmos_data(s, info_ofs, cylinders); 340 mc146818rtc_set_cmos_data(s, info_ofs + 1, cylinders >> 8); 341 mc146818rtc_set_cmos_data(s, info_ofs + 2, heads); 342 mc146818rtc_set_cmos_data(s, info_ofs + 3, 0xff); 343 mc146818rtc_set_cmos_data(s, info_ofs + 4, 0xff); 344 mc146818rtc_set_cmos_data(s, info_ofs + 5, 0xc0 | ((heads > 8) << 3)); 345 mc146818rtc_set_cmos_data(s, info_ofs + 6, cylinders); 346 mc146818rtc_set_cmos_data(s, info_ofs + 7, cylinders >> 8); 347 mc146818rtc_set_cmos_data(s, info_ofs + 8, sectors); 348 } 349 350 /* convert boot_device letter to something recognizable by the bios */ 351 static int boot_device2nibble(char boot_device) 352 { 353 switch(boot_device) { 354 case 'a': 355 case 'b': 356 return 0x01; /* floppy boot */ 357 case 'c': 358 return 0x02; /* hard drive boot */ 359 case 'd': 360 return 0x03; /* CD-ROM boot */ 361 case 'n': 362 return 0x04; /* Network boot */ 363 } 364 return 0; 365 } 366 367 static void set_boot_dev(PCMachineState *pcms, MC146818RtcState *s, 368 const char *boot_device, Error **errp) 369 { 370 #define PC_MAX_BOOT_DEVICES 3 371 int nbds, bds[3] = { 0, }; 372 int i; 373 374 nbds = strlen(boot_device); 375 if (nbds > PC_MAX_BOOT_DEVICES) { 376 error_setg(errp, "Too many boot devices for PC"); 377 return; 378 } 379 for (i = 0; i < nbds; i++) { 380 bds[i] = boot_device2nibble(boot_device[i]); 381 if (bds[i] == 0) { 382 error_setg(errp, "Invalid boot device for PC: '%c'", 383 boot_device[i]); 384 return; 385 } 386 } 387 mc146818rtc_set_cmos_data(s, 0x3d, (bds[1] << 4) | bds[0]); 388 mc146818rtc_set_cmos_data(s, 0x38, (bds[2] << 4) | !pcms->fd_bootchk); 389 } 390 391 static void pc_boot_set(void *opaque, const char *boot_device, Error **errp) 392 { 393 PCMachineState *pcms = opaque; 394 X86MachineState *x86ms = X86_MACHINE(pcms); 395 396 set_boot_dev(pcms, MC146818_RTC(x86ms->rtc), boot_device, errp); 397 } 398 399 static void pc_cmos_init_floppy(MC146818RtcState *rtc_state, ISADevice *floppy) 400 { 401 int val, nb; 402 FloppyDriveType fd_type[2] = { FLOPPY_DRIVE_TYPE_NONE, 403 FLOPPY_DRIVE_TYPE_NONE }; 404 405 #ifdef CONFIG_FDC_ISA 406 /* floppy type */ 407 if (floppy) { 408 for (int i = 0; i < 2; i++) { 409 fd_type[i] = isa_fdc_get_drive_type(floppy, i); 410 } 411 } 412 #endif 413 414 val = (cmos_get_fd_drive_type(fd_type[0]) << 4) | 415 cmos_get_fd_drive_type(fd_type[1]); 416 mc146818rtc_set_cmos_data(rtc_state, 0x10, val); 417 418 val = mc146818rtc_get_cmos_data(rtc_state, REG_EQUIPMENT_BYTE); 419 nb = 0; 420 if (fd_type[0] != FLOPPY_DRIVE_TYPE_NONE) { 421 nb++; 422 } 423 if (fd_type[1] != FLOPPY_DRIVE_TYPE_NONE) { 424 nb++; 425 } 426 switch (nb) { 427 case 0: 428 break; 429 case 1: 430 val |= 0x01; /* 1 drive, ready for boot */ 431 break; 432 case 2: 433 val |= 0x41; /* 2 drives, ready for boot */ 434 break; 435 } 436 mc146818rtc_set_cmos_data(rtc_state, REG_EQUIPMENT_BYTE, val); 437 } 438 439 typedef struct check_fdc_state { 440 ISADevice *floppy; 441 bool multiple; 442 } CheckFdcState; 443 444 static int check_fdc(Object *obj, void *opaque) 445 { 446 CheckFdcState *state = opaque; 447 Object *fdc; 448 uint32_t iobase; 449 Error *local_err = NULL; 450 451 fdc = object_dynamic_cast(obj, TYPE_ISA_FDC); 452 if (!fdc) { 453 return 0; 454 } 455 456 iobase = object_property_get_uint(obj, "iobase", &local_err); 457 if (local_err || iobase != 0x3f0) { 458 error_free(local_err); 459 return 0; 460 } 461 462 if (state->floppy) { 463 state->multiple = true; 464 } else { 465 state->floppy = ISA_DEVICE(obj); 466 } 467 return 0; 468 } 469 470 static const char * const fdc_container_path[] = { 471 "unattached", "peripheral", "peripheral-anon" 472 }; 473 474 /* 475 * Locate the FDC at IO address 0x3f0, in order to configure the CMOS registers 476 * and ACPI objects. 477 */ 478 static ISADevice *pc_find_fdc0(void) 479 { 480 int i; 481 Object *container; 482 CheckFdcState state = { 0 }; 483 484 for (i = 0; i < ARRAY_SIZE(fdc_container_path); i++) { 485 container = machine_get_container(fdc_container_path[i]); 486 object_child_foreach(container, check_fdc, &state); 487 } 488 489 if (state.multiple) { 490 warn_report("multiple floppy disk controllers with " 491 "iobase=0x3f0 have been found"); 492 error_printf("the one being picked for CMOS setup might not reflect " 493 "your intent"); 494 } 495 496 return state.floppy; 497 } 498 499 static void pc_cmos_init_late(PCMachineState *pcms) 500 { 501 X86MachineState *x86ms = X86_MACHINE(pcms); 502 MC146818RtcState *s = MC146818_RTC(x86ms->rtc); 503 int16_t cylinders; 504 int8_t heads, sectors; 505 int val; 506 int i, trans; 507 508 val = 0; 509 if (pcms->idebus[0] && 510 ide_get_geometry(pcms->idebus[0], 0, 511 &cylinders, &heads, §ors) >= 0) { 512 cmos_init_hd(s, 0x19, 0x1b, cylinders, heads, sectors); 513 val |= 0xf0; 514 } 515 if (pcms->idebus[0] && 516 ide_get_geometry(pcms->idebus[0], 1, 517 &cylinders, &heads, §ors) >= 0) { 518 cmos_init_hd(s, 0x1a, 0x24, cylinders, heads, sectors); 519 val |= 0x0f; 520 } 521 mc146818rtc_set_cmos_data(s, 0x12, val); 522 523 val = 0; 524 for (i = 0; i < 4; i++) { 525 /* NOTE: ide_get_geometry() returns the physical 526 geometry. It is always such that: 1 <= sects <= 63, 1 527 <= heads <= 16, 1 <= cylinders <= 16383. The BIOS 528 geometry can be different if a translation is done. */ 529 BusState *idebus = pcms->idebus[i / 2]; 530 if (idebus && 531 ide_get_geometry(idebus, i % 2, 532 &cylinders, &heads, §ors) >= 0) { 533 trans = ide_get_bios_chs_trans(idebus, i % 2) - 1; 534 assert((trans & ~3) == 0); 535 val |= trans << (i * 2); 536 } 537 } 538 mc146818rtc_set_cmos_data(s, 0x39, val); 539 540 pc_cmos_init_floppy(s, pc_find_fdc0()); 541 542 /* various important CMOS locations needed by PC/Bochs bios */ 543 544 /* memory size */ 545 /* base memory (first MiB) */ 546 val = MIN(x86ms->below_4g_mem_size / KiB, 640); 547 mc146818rtc_set_cmos_data(s, 0x15, val); 548 mc146818rtc_set_cmos_data(s, 0x16, val >> 8); 549 /* extended memory (next 64MiB) */ 550 if (x86ms->below_4g_mem_size > 1 * MiB) { 551 val = (x86ms->below_4g_mem_size - 1 * MiB) / KiB; 552 } else { 553 val = 0; 554 } 555 if (val > 65535) 556 val = 65535; 557 mc146818rtc_set_cmos_data(s, 0x17, val); 558 mc146818rtc_set_cmos_data(s, 0x18, val >> 8); 559 mc146818rtc_set_cmos_data(s, 0x30, val); 560 mc146818rtc_set_cmos_data(s, 0x31, val >> 8); 561 /* memory between 16MiB and 4GiB */ 562 if (x86ms->below_4g_mem_size > 16 * MiB) { 563 val = (x86ms->below_4g_mem_size - 16 * MiB) / (64 * KiB); 564 } else { 565 val = 0; 566 } 567 if (val > 65535) 568 val = 65535; 569 mc146818rtc_set_cmos_data(s, 0x34, val); 570 mc146818rtc_set_cmos_data(s, 0x35, val >> 8); 571 /* memory above 4GiB */ 572 val = x86ms->above_4g_mem_size / 65536; 573 mc146818rtc_set_cmos_data(s, 0x5b, val); 574 mc146818rtc_set_cmos_data(s, 0x5c, val >> 8); 575 mc146818rtc_set_cmos_data(s, 0x5d, val >> 16); 576 577 val = 0; 578 val |= 0x02; /* FPU is there */ 579 val |= 0x04; /* PS/2 mouse installed */ 580 mc146818rtc_set_cmos_data(s, REG_EQUIPMENT_BYTE, val); 581 } 582 583 static void handle_a20_line_change(void *opaque, int irq, int level) 584 { 585 X86CPU *cpu = opaque; 586 587 /* XXX: send to all CPUs ? */ 588 /* XXX: add logic to handle multiple A20 line sources */ 589 x86_cpu_set_a20(cpu, level); 590 } 591 592 #define NE2000_NB_MAX 6 593 594 static const int ne2000_io[NE2000_NB_MAX] = { 0x300, 0x320, 0x340, 0x360, 595 0x280, 0x380 }; 596 static const int ne2000_irq[NE2000_NB_MAX] = { 9, 10, 11, 3, 4, 5 }; 597 598 static gboolean pc_init_ne2k_isa(ISABus *bus, NICInfo *nd, Error **errp) 599 { 600 static int nb_ne2k = 0; 601 602 if (nb_ne2k == NE2000_NB_MAX) { 603 error_setg(errp, 604 "maximum number of ISA NE2000 devices exceeded"); 605 return false; 606 } 607 isa_ne2000_init(bus, ne2000_io[nb_ne2k], 608 ne2000_irq[nb_ne2k], nd); 609 nb_ne2k++; 610 return true; 611 } 612 613 void pc_acpi_smi_interrupt(void *opaque, int irq, int level) 614 { 615 X86CPU *cpu = opaque; 616 617 if (level) { 618 cpu_interrupt(CPU(cpu), CPU_INTERRUPT_SMI); 619 } 620 } 621 622 static 623 void pc_machine_done(Notifier *notifier, void *data) 624 { 625 PCMachineState *pcms = container_of(notifier, 626 PCMachineState, machine_done); 627 X86MachineState *x86ms = X86_MACHINE(pcms); 628 629 cxl_hook_up_pxb_registers(pcms->pcibus, &pcms->cxl_devices_state, 630 &error_fatal); 631 632 if (pcms->cxl_devices_state.is_enabled) { 633 cxl_fmws_link_targets(&pcms->cxl_devices_state, &error_fatal); 634 } 635 636 /* set the number of CPUs */ 637 x86_rtc_set_cpus_count(x86ms->rtc, x86ms->boot_cpus); 638 639 pci_bus_add_fw_cfg_extra_pci_roots(x86ms->fw_cfg, pcms->pcibus, 640 &error_abort); 641 642 acpi_setup(); 643 if (x86ms->fw_cfg) { 644 fw_cfg_build_smbios(pcms, x86ms->fw_cfg, pcms->smbios_entry_point_type); 645 fw_cfg_add_e820(x86ms->fw_cfg); 646 fw_cfg_build_feature_control(MACHINE(pcms), x86ms->fw_cfg); 647 /* update FW_CFG_NB_CPUS to account for -device added CPUs */ 648 fw_cfg_modify_i16(x86ms->fw_cfg, FW_CFG_NB_CPUS, x86ms->boot_cpus); 649 } 650 651 pc_cmos_init_late(pcms); 652 } 653 654 /* setup pci memory address space mapping into system address space */ 655 void pc_pci_as_mapping_init(MemoryRegion *system_memory, 656 MemoryRegion *pci_address_space) 657 { 658 /* Set to lower priority than RAM */ 659 memory_region_add_subregion_overlap(system_memory, 0x0, 660 pci_address_space, -1); 661 } 662 663 void xen_load_linux(PCMachineState *pcms) 664 { 665 int i; 666 FWCfgState *fw_cfg; 667 PCMachineClass *pcmc = PC_MACHINE_GET_CLASS(pcms); 668 X86MachineState *x86ms = X86_MACHINE(pcms); 669 670 assert(MACHINE(pcms)->kernel_filename != NULL); 671 672 fw_cfg = fw_cfg_init_io_dma(FW_CFG_IO_BASE, FW_CFG_IO_BASE + 4, 673 &address_space_memory); 674 fw_cfg_add_i16(fw_cfg, FW_CFG_NB_CPUS, x86ms->boot_cpus); 675 rom_set_fw(fw_cfg); 676 677 x86_load_linux(x86ms, fw_cfg, PC_FW_DATA, pcmc->pvh_enabled); 678 for (i = 0; i < nb_option_roms; i++) { 679 assert(!strcmp(option_rom[i].name, "linuxboot.bin") || 680 !strcmp(option_rom[i].name, "linuxboot_dma.bin") || 681 !strcmp(option_rom[i].name, "pvh.bin") || 682 !strcmp(option_rom[i].name, "multiboot.bin") || 683 !strcmp(option_rom[i].name, "multiboot_dma.bin")); 684 rom_add_option(option_rom[i].name, option_rom[i].bootindex); 685 } 686 x86ms->fw_cfg = fw_cfg; 687 } 688 689 #define PC_ROM_MIN_VGA 0xc0000 690 #define PC_ROM_MIN_OPTION 0xc8000 691 #define PC_ROM_MAX 0xe0000 692 #define PC_ROM_ALIGN 0x800 693 #define PC_ROM_SIZE (PC_ROM_MAX - PC_ROM_MIN_VGA) 694 695 static hwaddr pc_above_4g_end(PCMachineState *pcms) 696 { 697 X86MachineState *x86ms = X86_MACHINE(pcms); 698 699 if (pcms->sgx_epc.size != 0) { 700 return sgx_epc_above_4g_end(&pcms->sgx_epc); 701 } 702 703 return x86ms->above_4g_mem_start + x86ms->above_4g_mem_size; 704 } 705 706 static void pc_get_device_memory_range(PCMachineState *pcms, 707 hwaddr *base, 708 ram_addr_t *device_mem_size) 709 { 710 MachineState *machine = MACHINE(pcms); 711 ram_addr_t size; 712 hwaddr addr; 713 714 size = machine->maxram_size - machine->ram_size; 715 addr = ROUND_UP(pc_above_4g_end(pcms), 1 * GiB); 716 717 /* size device region assuming 1G page max alignment per slot */ 718 size += (1 * GiB) * machine->ram_slots; 719 720 *base = addr; 721 *device_mem_size = size; 722 } 723 724 static uint64_t pc_get_cxl_range_start(PCMachineState *pcms) 725 { 726 PCMachineClass *pcmc = PC_MACHINE_GET_CLASS(pcms); 727 MachineState *ms = MACHINE(pcms); 728 hwaddr cxl_base; 729 ram_addr_t size; 730 731 if (pcmc->has_reserved_memory && 732 (ms->ram_size < ms->maxram_size)) { 733 pc_get_device_memory_range(pcms, &cxl_base, &size); 734 cxl_base += size; 735 } else { 736 cxl_base = pc_above_4g_end(pcms); 737 } 738 739 return cxl_base; 740 } 741 742 static uint64_t pc_get_cxl_range_end(PCMachineState *pcms) 743 { 744 uint64_t start = pc_get_cxl_range_start(pcms) + MiB; 745 746 if (pcms->cxl_devices_state.fixed_windows) { 747 GList *it; 748 749 start = ROUND_UP(start, 256 * MiB); 750 for (it = pcms->cxl_devices_state.fixed_windows; it; it = it->next) { 751 CXLFixedWindow *fw = it->data; 752 start += fw->size; 753 } 754 } 755 756 return start; 757 } 758 759 static hwaddr pc_max_used_gpa(PCMachineState *pcms, uint64_t pci_hole64_size) 760 { 761 X86CPU *cpu = X86_CPU(first_cpu); 762 PCMachineClass *pcmc = PC_MACHINE_GET_CLASS(pcms); 763 MachineState *ms = MACHINE(pcms); 764 765 if (cpu->env.features[FEAT_8000_0001_EDX] & CPUID_EXT2_LM) { 766 /* 64-bit systems */ 767 return pc_pci_hole64_start() + pci_hole64_size - 1; 768 } 769 770 /* 32-bit systems */ 771 if (pcmc->broken_32bit_mem_addr_check) { 772 /* old value for compatibility reasons */ 773 return ((hwaddr)1 << cpu->phys_bits) - 1; 774 } 775 776 /* 777 * 32-bit systems don't have hole64 but they might have a region for 778 * memory devices. Even if additional hotplugged memory devices might 779 * not be usable by most guest OSes, we need to still consider them for 780 * calculating the highest possible GPA so that we can properly report 781 * if someone configures them on a CPU that cannot possibly address them. 782 */ 783 if (pcmc->has_reserved_memory && 784 (ms->ram_size < ms->maxram_size)) { 785 hwaddr devmem_start; 786 ram_addr_t devmem_size; 787 788 pc_get_device_memory_range(pcms, &devmem_start, &devmem_size); 789 devmem_start += devmem_size; 790 return devmem_start - 1; 791 } 792 793 /* configuration without any memory hotplug */ 794 return pc_above_4g_end(pcms) - 1; 795 } 796 797 /* 798 * AMD systems with an IOMMU have an additional hole close to the 799 * 1Tb, which are special GPAs that cannot be DMA mapped. Depending 800 * on kernel version, VFIO may or may not let you DMA map those ranges. 801 * Starting Linux v5.4 we validate it, and can't create guests on AMD machines 802 * with certain memory sizes. It's also wrong to use those IOVA ranges 803 * in detriment of leading to IOMMU INVALID_DEVICE_REQUEST or worse. 804 * The ranges reserved for Hyper-Transport are: 805 * 806 * FD_0000_0000h - FF_FFFF_FFFFh 807 * 808 * The ranges represent the following: 809 * 810 * Base Address Top Address Use 811 * 812 * FD_0000_0000h FD_F7FF_FFFFh Reserved interrupt address space 813 * FD_F800_0000h FD_F8FF_FFFFh Interrupt/EOI IntCtl 814 * FD_F900_0000h FD_F90F_FFFFh Legacy PIC IACK 815 * FD_F910_0000h FD_F91F_FFFFh System Management 816 * FD_F920_0000h FD_FAFF_FFFFh Reserved Page Tables 817 * FD_FB00_0000h FD_FBFF_FFFFh Address Translation 818 * FD_FC00_0000h FD_FDFF_FFFFh I/O Space 819 * FD_FE00_0000h FD_FFFF_FFFFh Configuration 820 * FE_0000_0000h FE_1FFF_FFFFh Extended Configuration/Device Messages 821 * FE_2000_0000h FF_FFFF_FFFFh Reserved 822 * 823 * See AMD IOMMU spec, section 2.1.2 "IOMMU Logical Topology", 824 * Table 3: Special Address Controls (GPA) for more information. 825 */ 826 #define AMD_HT_START 0xfd00000000UL 827 #define AMD_HT_END 0xffffffffffUL 828 #define AMD_ABOVE_1TB_START (AMD_HT_END + 1) 829 #define AMD_HT_SIZE (AMD_ABOVE_1TB_START - AMD_HT_START) 830 831 void pc_memory_init(PCMachineState *pcms, 832 MemoryRegion *system_memory, 833 MemoryRegion *rom_memory, 834 uint64_t pci_hole64_size) 835 { 836 int linux_boot, i; 837 MemoryRegion *option_rom_mr; 838 MemoryRegion *ram_below_4g, *ram_above_4g; 839 FWCfgState *fw_cfg; 840 MachineState *machine = MACHINE(pcms); 841 MachineClass *mc = MACHINE_GET_CLASS(machine); 842 PCMachineClass *pcmc = PC_MACHINE_GET_CLASS(pcms); 843 X86MachineState *x86ms = X86_MACHINE(pcms); 844 hwaddr maxphysaddr, maxusedaddr; 845 hwaddr cxl_base, cxl_resv_end = 0; 846 X86CPU *cpu = X86_CPU(first_cpu); 847 848 assert(machine->ram_size == x86ms->below_4g_mem_size + 849 x86ms->above_4g_mem_size); 850 851 linux_boot = (machine->kernel_filename != NULL); 852 853 /* 854 * The HyperTransport range close to the 1T boundary is unique to AMD 855 * hosts with IOMMUs enabled. Restrict the ram-above-4g relocation 856 * to above 1T to AMD vCPUs only. @enforce_amd_1tb_hole is only false in 857 * older machine types (<= 7.0) for compatibility purposes. 858 */ 859 if (IS_AMD_CPU(&cpu->env) && pcmc->enforce_amd_1tb_hole) { 860 /* Bail out if max possible address does not cross HT range */ 861 if (pc_max_used_gpa(pcms, pci_hole64_size) >= AMD_HT_START) { 862 x86ms->above_4g_mem_start = AMD_ABOVE_1TB_START; 863 } 864 865 /* 866 * Advertise the HT region if address space covers the reserved 867 * region or if we relocate. 868 */ 869 if (cpu->phys_bits >= 40) { 870 e820_add_entry(AMD_HT_START, AMD_HT_SIZE, E820_RESERVED); 871 } 872 } 873 874 /* 875 * phys-bits is required to be appropriately configured 876 * to make sure max used GPA is reachable. 877 */ 878 maxusedaddr = pc_max_used_gpa(pcms, pci_hole64_size); 879 maxphysaddr = ((hwaddr)1 << cpu->phys_bits) - 1; 880 if (maxphysaddr < maxusedaddr) { 881 error_report("Address space limit 0x%"PRIx64" < 0x%"PRIx64 882 " phys-bits too low (%u)", 883 maxphysaddr, maxusedaddr, cpu->phys_bits); 884 exit(EXIT_FAILURE); 885 } 886 887 /* 888 * Split single memory region and use aliases to address portions of it, 889 * done for backwards compatibility with older qemus. 890 */ 891 ram_below_4g = g_malloc(sizeof(*ram_below_4g)); 892 memory_region_init_alias(ram_below_4g, NULL, "ram-below-4g", machine->ram, 893 0, x86ms->below_4g_mem_size); 894 memory_region_add_subregion(system_memory, 0, ram_below_4g); 895 e820_add_entry(0, x86ms->below_4g_mem_size, E820_RAM); 896 if (x86ms->above_4g_mem_size > 0) { 897 ram_above_4g = g_malloc(sizeof(*ram_above_4g)); 898 memory_region_init_alias(ram_above_4g, NULL, "ram-above-4g", 899 machine->ram, 900 x86ms->below_4g_mem_size, 901 x86ms->above_4g_mem_size); 902 memory_region_add_subregion(system_memory, x86ms->above_4g_mem_start, 903 ram_above_4g); 904 e820_add_entry(x86ms->above_4g_mem_start, x86ms->above_4g_mem_size, 905 E820_RAM); 906 } 907 908 if (pcms->sgx_epc.size != 0) { 909 e820_add_entry(pcms->sgx_epc.base, pcms->sgx_epc.size, E820_RESERVED); 910 } 911 912 if (!pcmc->has_reserved_memory && 913 (machine->ram_slots || 914 (machine->maxram_size > machine->ram_size))) { 915 916 error_report("\"-memory 'slots|maxmem'\" is not supported by: %s", 917 mc->name); 918 exit(EXIT_FAILURE); 919 } 920 921 /* initialize device memory address space */ 922 if (pcmc->has_reserved_memory && 923 (machine->ram_size < machine->maxram_size)) { 924 ram_addr_t device_mem_size; 925 hwaddr device_mem_base; 926 927 if (machine->ram_slots > ACPI_MAX_RAM_SLOTS) { 928 error_report("unsupported amount of memory slots: %"PRIu64, 929 machine->ram_slots); 930 exit(EXIT_FAILURE); 931 } 932 933 if (QEMU_ALIGN_UP(machine->maxram_size, 934 TARGET_PAGE_SIZE) != machine->maxram_size) { 935 error_report("maximum memory size must by aligned to multiple of " 936 "%d bytes", TARGET_PAGE_SIZE); 937 exit(EXIT_FAILURE); 938 } 939 940 pc_get_device_memory_range(pcms, &device_mem_base, &device_mem_size); 941 942 if (device_mem_base + device_mem_size < device_mem_size) { 943 error_report("unsupported amount of maximum memory: " RAM_ADDR_FMT, 944 machine->maxram_size); 945 exit(EXIT_FAILURE); 946 } 947 machine_memory_devices_init(machine, device_mem_base, device_mem_size); 948 } 949 950 if (pcms->cxl_devices_state.is_enabled) { 951 MemoryRegion *mr = &pcms->cxl_devices_state.host_mr; 952 hwaddr cxl_size = MiB; 953 954 cxl_base = pc_get_cxl_range_start(pcms); 955 memory_region_init(mr, OBJECT(machine), "cxl_host_reg", cxl_size); 956 memory_region_add_subregion(system_memory, cxl_base, mr); 957 cxl_resv_end = cxl_base + cxl_size; 958 if (pcms->cxl_devices_state.fixed_windows) { 959 hwaddr cxl_fmw_base; 960 GList *it; 961 962 cxl_fmw_base = ROUND_UP(cxl_base + cxl_size, 256 * MiB); 963 for (it = pcms->cxl_devices_state.fixed_windows; it; it = it->next) { 964 CXLFixedWindow *fw = it->data; 965 966 fw->base = cxl_fmw_base; 967 memory_region_init_io(&fw->mr, OBJECT(machine), &cfmws_ops, fw, 968 "cxl-fixed-memory-region", fw->size); 969 memory_region_add_subregion(system_memory, fw->base, &fw->mr); 970 cxl_fmw_base += fw->size; 971 cxl_resv_end = cxl_fmw_base; 972 } 973 } 974 } 975 976 /* Initialize PC system firmware */ 977 pc_system_firmware_init(pcms, rom_memory); 978 979 option_rom_mr = g_malloc(sizeof(*option_rom_mr)); 980 if (machine_require_guest_memfd(machine)) { 981 memory_region_init_ram_guest_memfd(option_rom_mr, NULL, "pc.rom", 982 PC_ROM_SIZE, &error_fatal); 983 } else { 984 memory_region_init_ram(option_rom_mr, NULL, "pc.rom", PC_ROM_SIZE, 985 &error_fatal); 986 if (pcmc->pci_enabled) { 987 memory_region_set_readonly(option_rom_mr, true); 988 } 989 } 990 memory_region_add_subregion_overlap(rom_memory, 991 PC_ROM_MIN_VGA, 992 option_rom_mr, 993 1); 994 995 fw_cfg = fw_cfg_arch_create(machine, 996 x86ms->boot_cpus, x86ms->apic_id_limit); 997 998 rom_set_fw(fw_cfg); 999 1000 if (machine->device_memory) { 1001 uint64_t *val = g_malloc(sizeof(*val)); 1002 uint64_t res_mem_end = machine->device_memory->base; 1003 1004 if (!pcmc->broken_reserved_end) { 1005 res_mem_end += memory_region_size(&machine->device_memory->mr); 1006 } 1007 1008 if (pcms->cxl_devices_state.is_enabled) { 1009 res_mem_end = cxl_resv_end; 1010 } 1011 *val = cpu_to_le64(ROUND_UP(res_mem_end, 1 * GiB)); 1012 fw_cfg_add_file(fw_cfg, "etc/reserved-memory-end", val, sizeof(*val)); 1013 } 1014 1015 if (linux_boot) { 1016 x86_load_linux(x86ms, fw_cfg, PC_FW_DATA, pcmc->pvh_enabled); 1017 } 1018 1019 for (i = 0; i < nb_option_roms; i++) { 1020 rom_add_option(option_rom[i].name, option_rom[i].bootindex); 1021 } 1022 x86ms->fw_cfg = fw_cfg; 1023 1024 /* Init default IOAPIC address space */ 1025 x86ms->ioapic_as = &address_space_memory; 1026 1027 /* Init ACPI memory hotplug IO base address */ 1028 pcms->memhp_io_base = ACPI_MEMORY_HOTPLUG_BASE; 1029 } 1030 1031 /* 1032 * The 64bit pci hole starts after "above 4G RAM" and 1033 * potentially the space reserved for memory hotplug. 1034 */ 1035 uint64_t pc_pci_hole64_start(void) 1036 { 1037 PCMachineState *pcms = PC_MACHINE(qdev_get_machine()); 1038 PCMachineClass *pcmc = PC_MACHINE_GET_CLASS(pcms); 1039 MachineState *ms = MACHINE(pcms); 1040 uint64_t hole64_start = 0; 1041 ram_addr_t size = 0; 1042 1043 if (pcms->cxl_devices_state.is_enabled) { 1044 hole64_start = pc_get_cxl_range_end(pcms); 1045 } else if (pcmc->has_reserved_memory && (ms->ram_size < ms->maxram_size)) { 1046 pc_get_device_memory_range(pcms, &hole64_start, &size); 1047 if (!pcmc->broken_reserved_end) { 1048 hole64_start += size; 1049 } 1050 } else { 1051 hole64_start = pc_above_4g_end(pcms); 1052 } 1053 1054 return ROUND_UP(hole64_start, 1 * GiB); 1055 } 1056 1057 DeviceState *pc_vga_init(ISABus *isa_bus, PCIBus *pci_bus) 1058 { 1059 DeviceState *dev = NULL; 1060 1061 rom_set_order_override(FW_CFG_ORDER_OVERRIDE_VGA); 1062 if (pci_bus) { 1063 PCIDevice *pcidev = pci_vga_init(pci_bus); 1064 dev = pcidev ? &pcidev->qdev : NULL; 1065 } else if (isa_bus) { 1066 ISADevice *isadev = isa_vga_init(isa_bus); 1067 dev = isadev ? DEVICE(isadev) : NULL; 1068 } 1069 rom_reset_order_override(); 1070 return dev; 1071 } 1072 1073 static const MemoryRegionOps ioport80_io_ops = { 1074 .write = ioport80_write, 1075 .read = ioport80_read, 1076 .endianness = DEVICE_LITTLE_ENDIAN, 1077 .impl = { 1078 .min_access_size = 1, 1079 .max_access_size = 1, 1080 }, 1081 }; 1082 1083 static const MemoryRegionOps ioportF0_io_ops = { 1084 .write = ioportF0_write, 1085 .read = ioportF0_read, 1086 .endianness = DEVICE_LITTLE_ENDIAN, 1087 .impl = { 1088 .min_access_size = 1, 1089 .max_access_size = 1, 1090 }, 1091 }; 1092 1093 static void pc_superio_init(ISABus *isa_bus, bool create_fdctrl, 1094 bool create_i8042, bool no_vmport, Error **errp) 1095 { 1096 int i; 1097 DriveInfo *fd[MAX_FD]; 1098 qemu_irq *a20_line; 1099 ISADevice *i8042, *port92, *vmmouse; 1100 1101 serial_hds_isa_init(isa_bus, 0, MAX_ISA_SERIAL_PORTS); 1102 parallel_hds_isa_init(isa_bus, MAX_PARALLEL_PORTS); 1103 1104 for (i = 0; i < MAX_FD; i++) { 1105 fd[i] = drive_get(IF_FLOPPY, 0, i); 1106 create_fdctrl |= !!fd[i]; 1107 } 1108 if (create_fdctrl) { 1109 #ifdef CONFIG_FDC_ISA 1110 ISADevice *fdc = isa_new(TYPE_ISA_FDC); 1111 if (fdc) { 1112 isa_realize_and_unref(fdc, isa_bus, &error_fatal); 1113 isa_fdc_init_drives(fdc, fd); 1114 } 1115 #endif 1116 } 1117 1118 if (!create_i8042) { 1119 if (!no_vmport) { 1120 error_setg(errp, 1121 "vmport requires the i8042 controller to be enabled"); 1122 } 1123 return; 1124 } 1125 1126 i8042 = isa_create_simple(isa_bus, TYPE_I8042); 1127 if (!no_vmport) { 1128 isa_create_simple(isa_bus, TYPE_VMPORT); 1129 vmmouse = isa_try_new("vmmouse"); 1130 } else { 1131 vmmouse = NULL; 1132 } 1133 if (vmmouse) { 1134 object_property_set_link(OBJECT(vmmouse), TYPE_I8042, OBJECT(i8042), 1135 &error_abort); 1136 isa_realize_and_unref(vmmouse, isa_bus, &error_fatal); 1137 } 1138 port92 = isa_create_simple(isa_bus, TYPE_PORT92); 1139 1140 a20_line = qemu_allocate_irqs(handle_a20_line_change, first_cpu, 2); 1141 qdev_connect_gpio_out_named(DEVICE(i8042), 1142 I8042_A20_LINE, 0, a20_line[0]); 1143 qdev_connect_gpio_out_named(DEVICE(port92), 1144 PORT92_A20_LINE, 0, a20_line[1]); 1145 g_free(a20_line); 1146 } 1147 1148 void pc_basic_device_init(struct PCMachineState *pcms, 1149 ISABus *isa_bus, qemu_irq *gsi, 1150 ISADevice *rtc_state, 1151 bool create_fdctrl, 1152 uint32_t hpet_irqs) 1153 { 1154 int i; 1155 DeviceState *hpet = NULL; 1156 int pit_isa_irq = 0; 1157 qemu_irq pit_alt_irq = NULL; 1158 ISADevice *pit = NULL; 1159 MemoryRegion *ioport80_io = g_new(MemoryRegion, 1); 1160 MemoryRegion *ioportF0_io = g_new(MemoryRegion, 1); 1161 X86MachineState *x86ms = X86_MACHINE(pcms); 1162 1163 memory_region_init_io(ioport80_io, NULL, &ioport80_io_ops, NULL, "ioport80", 1); 1164 memory_region_add_subregion(isa_bus->address_space_io, 0x80, ioport80_io); 1165 1166 memory_region_init_io(ioportF0_io, NULL, &ioportF0_io_ops, NULL, "ioportF0", 1); 1167 memory_region_add_subregion(isa_bus->address_space_io, 0xf0, ioportF0_io); 1168 1169 /* 1170 * Check if an HPET shall be created. 1171 */ 1172 if (pcms->hpet_enabled) { 1173 qemu_irq rtc_irq; 1174 1175 hpet = qdev_try_new(TYPE_HPET); 1176 if (!hpet) { 1177 error_report("couldn't create HPET device"); 1178 exit(1); 1179 } 1180 /* 1181 * For pc-piix-*, hpet's intcap is always IRQ2. For pc-q35-*, 1182 * use IRQ16~23, IRQ8 and IRQ2. If the user has already set 1183 * the property, use whatever mask they specified. 1184 */ 1185 uint8_t compat = object_property_get_uint(OBJECT(hpet), 1186 HPET_INTCAP, NULL); 1187 if (!compat) { 1188 qdev_prop_set_uint32(hpet, HPET_INTCAP, hpet_irqs); 1189 } 1190 sysbus_realize_and_unref(SYS_BUS_DEVICE(hpet), &error_fatal); 1191 sysbus_mmio_map(SYS_BUS_DEVICE(hpet), 0, HPET_BASE); 1192 1193 for (i = 0; i < IOAPIC_NUM_PINS; i++) { 1194 sysbus_connect_irq(SYS_BUS_DEVICE(hpet), i, gsi[i]); 1195 } 1196 pit_isa_irq = -1; 1197 pit_alt_irq = qdev_get_gpio_in(hpet, HPET_LEGACY_PIT_INT); 1198 rtc_irq = qdev_get_gpio_in(hpet, HPET_LEGACY_RTC_INT); 1199 1200 /* overwrite connection created by south bridge */ 1201 qdev_connect_gpio_out(DEVICE(rtc_state), 0, rtc_irq); 1202 } 1203 1204 object_property_add_alias(OBJECT(pcms), "rtc-time", OBJECT(rtc_state), 1205 "date"); 1206 1207 #ifdef CONFIG_XEN_EMU 1208 if (xen_mode == XEN_EMULATE) { 1209 xen_overlay_create(); 1210 xen_evtchn_create(IOAPIC_NUM_PINS, gsi); 1211 xen_gnttab_create(); 1212 xen_xenstore_create(); 1213 if (pcms->pcibus) { 1214 pci_create_simple(pcms->pcibus, -1, "xen-platform"); 1215 } 1216 xen_bus_init(); 1217 } 1218 #endif 1219 1220 qemu_register_boot_set(pc_boot_set, pcms); 1221 set_boot_dev(pcms, MC146818_RTC(rtc_state), 1222 MACHINE(pcms)->boot_config.order, &error_fatal); 1223 1224 if (!xen_enabled() && 1225 (x86ms->pit == ON_OFF_AUTO_AUTO || x86ms->pit == ON_OFF_AUTO_ON)) { 1226 if (kvm_pit_in_kernel()) { 1227 pit = kvm_pit_init(isa_bus, 0x40); 1228 } else { 1229 pit = i8254_pit_init(isa_bus, 0x40, pit_isa_irq, pit_alt_irq); 1230 } 1231 if (hpet) { 1232 /* connect PIT to output control line of the HPET */ 1233 qdev_connect_gpio_out(hpet, 0, qdev_get_gpio_in(DEVICE(pit), 0)); 1234 } 1235 object_property_set_link(OBJECT(pcms->pcspk), "pit", 1236 OBJECT(pit), &error_fatal); 1237 isa_realize_and_unref(pcms->pcspk, isa_bus, &error_fatal); 1238 } 1239 1240 if (pcms->vmport == ON_OFF_AUTO_AUTO) { 1241 pcms->vmport = (xen_enabled() || !pcms->i8042_enabled) 1242 ? ON_OFF_AUTO_OFF : ON_OFF_AUTO_ON; 1243 } 1244 1245 /* Super I/O */ 1246 pc_superio_init(isa_bus, create_fdctrl, pcms->i8042_enabled, 1247 pcms->vmport != ON_OFF_AUTO_ON, &error_fatal); 1248 1249 pcms->machine_done.notify = pc_machine_done; 1250 qemu_add_machine_init_done_notifier(&pcms->machine_done); 1251 } 1252 1253 void pc_nic_init(PCMachineClass *pcmc, ISABus *isa_bus, PCIBus *pci_bus) 1254 { 1255 MachineClass *mc = MACHINE_CLASS(pcmc); 1256 bool default_is_ne2k = g_str_equal(mc->default_nic, TYPE_ISA_NE2000); 1257 NICInfo *nd; 1258 1259 rom_set_order_override(FW_CFG_ORDER_OVERRIDE_NIC); 1260 1261 while ((nd = qemu_find_nic_info(TYPE_ISA_NE2000, default_is_ne2k, NULL))) { 1262 pc_init_ne2k_isa(isa_bus, nd, &error_fatal); 1263 } 1264 1265 /* Anything remaining should be a PCI NIC */ 1266 if (pci_bus) { 1267 pci_init_nic_devices(pci_bus, mc->default_nic); 1268 } 1269 1270 rom_reset_order_override(); 1271 } 1272 1273 void pc_i8259_create(ISABus *isa_bus, qemu_irq *i8259_irqs) 1274 { 1275 qemu_irq *i8259; 1276 1277 if (kvm_pic_in_kernel()) { 1278 i8259 = kvm_i8259_init(isa_bus); 1279 } else if (xen_enabled()) { 1280 i8259 = xen_interrupt_controller_init(); 1281 } else { 1282 i8259 = i8259_init(isa_bus, x86_allocate_cpu_irq()); 1283 } 1284 1285 for (size_t i = 0; i < ISA_NUM_IRQS; i++) { 1286 i8259_irqs[i] = i8259[i]; 1287 } 1288 1289 g_free(i8259); 1290 } 1291 1292 static void pc_memory_pre_plug(HotplugHandler *hotplug_dev, DeviceState *dev, 1293 Error **errp) 1294 { 1295 const X86MachineState *x86ms = X86_MACHINE(hotplug_dev); 1296 const MachineState *ms = MACHINE(hotplug_dev); 1297 const bool is_nvdimm = object_dynamic_cast(OBJECT(dev), TYPE_NVDIMM); 1298 Error *local_err = NULL; 1299 1300 /* 1301 * When "acpi=off" is used with the Q35 machine type, no ACPI is built, 1302 * but pcms->acpi_dev is still created. Check !acpi_enabled in 1303 * addition to cover this case. 1304 */ 1305 if (!x86ms->acpi_dev || !x86_machine_is_acpi_enabled(x86ms)) { 1306 error_setg(errp, 1307 "memory hotplug is not enabled: missing acpi device or acpi disabled"); 1308 return; 1309 } 1310 1311 if (is_nvdimm && !ms->nvdimms_state->is_enabled) { 1312 error_setg(errp, "nvdimm is not enabled: missing 'nvdimm' in '-M'"); 1313 return; 1314 } 1315 1316 hotplug_handler_pre_plug(x86ms->acpi_dev, dev, &local_err); 1317 if (local_err) { 1318 error_propagate(errp, local_err); 1319 return; 1320 } 1321 1322 pc_dimm_pre_plug(PC_DIMM(dev), MACHINE(hotplug_dev), errp); 1323 } 1324 1325 static void pc_memory_plug(HotplugHandler *hotplug_dev, 1326 DeviceState *dev, Error **errp) 1327 { 1328 PCMachineState *pcms = PC_MACHINE(hotplug_dev); 1329 X86MachineState *x86ms = X86_MACHINE(hotplug_dev); 1330 MachineState *ms = MACHINE(hotplug_dev); 1331 bool is_nvdimm = object_dynamic_cast(OBJECT(dev), TYPE_NVDIMM); 1332 1333 pc_dimm_plug(PC_DIMM(dev), MACHINE(pcms)); 1334 1335 if (is_nvdimm) { 1336 nvdimm_plug(ms->nvdimms_state); 1337 } 1338 1339 hotplug_handler_plug(x86ms->acpi_dev, dev, &error_abort); 1340 } 1341 1342 static void pc_memory_unplug_request(HotplugHandler *hotplug_dev, 1343 DeviceState *dev, Error **errp) 1344 { 1345 X86MachineState *x86ms = X86_MACHINE(hotplug_dev); 1346 1347 /* 1348 * When "acpi=off" is used with the Q35 machine type, no ACPI is built, 1349 * but pcms->acpi_dev is still created. Check !acpi_enabled in 1350 * addition to cover this case. 1351 */ 1352 if (!x86ms->acpi_dev || !x86_machine_is_acpi_enabled(x86ms)) { 1353 error_setg(errp, 1354 "memory hotplug is not enabled: missing acpi device or acpi disabled"); 1355 return; 1356 } 1357 1358 if (object_dynamic_cast(OBJECT(dev), TYPE_NVDIMM)) { 1359 error_setg(errp, "nvdimm device hot unplug is not supported yet."); 1360 return; 1361 } 1362 1363 hotplug_handler_unplug_request(x86ms->acpi_dev, dev, 1364 errp); 1365 } 1366 1367 static void pc_memory_unplug(HotplugHandler *hotplug_dev, 1368 DeviceState *dev, Error **errp) 1369 { 1370 PCMachineState *pcms = PC_MACHINE(hotplug_dev); 1371 X86MachineState *x86ms = X86_MACHINE(hotplug_dev); 1372 Error *local_err = NULL; 1373 1374 hotplug_handler_unplug(x86ms->acpi_dev, dev, &local_err); 1375 if (local_err) { 1376 goto out; 1377 } 1378 1379 pc_dimm_unplug(PC_DIMM(dev), MACHINE(pcms)); 1380 qdev_unrealize(dev); 1381 out: 1382 error_propagate(errp, local_err); 1383 } 1384 1385 static void pc_hv_balloon_pre_plug(HotplugHandler *hotplug_dev, 1386 DeviceState *dev, Error **errp) 1387 { 1388 /* The vmbus handler has no hotplug handler; we should never end up here. */ 1389 g_assert(!dev->hotplugged); 1390 memory_device_pre_plug(MEMORY_DEVICE(dev), MACHINE(hotplug_dev), errp); 1391 } 1392 1393 static void pc_hv_balloon_plug(HotplugHandler *hotplug_dev, 1394 DeviceState *dev, Error **errp) 1395 { 1396 memory_device_plug(MEMORY_DEVICE(dev), MACHINE(hotplug_dev)); 1397 } 1398 1399 static void pc_machine_device_pre_plug_cb(HotplugHandler *hotplug_dev, 1400 DeviceState *dev, Error **errp) 1401 { 1402 if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM)) { 1403 pc_memory_pre_plug(hotplug_dev, dev, errp); 1404 } else if (object_dynamic_cast(OBJECT(dev), TYPE_CPU)) { 1405 x86_cpu_pre_plug(hotplug_dev, dev, errp); 1406 } else if (object_dynamic_cast(OBJECT(dev), TYPE_VIRTIO_MD_PCI)) { 1407 virtio_md_pci_pre_plug(VIRTIO_MD_PCI(dev), MACHINE(hotplug_dev), errp); 1408 } else if (object_dynamic_cast(OBJECT(dev), TYPE_VIRTIO_IOMMU_PCI)) { 1409 /* Declare the APIC range as the reserved MSI region */ 1410 char *resv_prop_str = g_strdup_printf("0xfee00000:0xfeefffff:%d", 1411 VIRTIO_IOMMU_RESV_MEM_T_MSI); 1412 QList *reserved_regions = qlist_new(); 1413 1414 qlist_append_str(reserved_regions, resv_prop_str); 1415 qdev_prop_set_array(dev, "reserved-regions", reserved_regions); 1416 1417 g_free(resv_prop_str); 1418 } 1419 1420 if (object_dynamic_cast(OBJECT(dev), TYPE_X86_IOMMU_DEVICE) || 1421 object_dynamic_cast(OBJECT(dev), TYPE_VIRTIO_IOMMU_PCI)) { 1422 PCMachineState *pcms = PC_MACHINE(hotplug_dev); 1423 1424 if (pcms->iommu) { 1425 error_setg(errp, "QEMU does not support multiple vIOMMUs " 1426 "for x86 yet."); 1427 return; 1428 } 1429 pcms->iommu = dev; 1430 } else if (object_dynamic_cast(OBJECT(dev), TYPE_HV_BALLOON)) { 1431 pc_hv_balloon_pre_plug(hotplug_dev, dev, errp); 1432 } 1433 } 1434 1435 static void pc_machine_device_plug_cb(HotplugHandler *hotplug_dev, 1436 DeviceState *dev, Error **errp) 1437 { 1438 if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM)) { 1439 pc_memory_plug(hotplug_dev, dev, errp); 1440 } else if (object_dynamic_cast(OBJECT(dev), TYPE_CPU)) { 1441 x86_cpu_plug(hotplug_dev, dev, errp); 1442 } else if (object_dynamic_cast(OBJECT(dev), TYPE_VIRTIO_MD_PCI)) { 1443 virtio_md_pci_plug(VIRTIO_MD_PCI(dev), MACHINE(hotplug_dev), errp); 1444 } else if (object_dynamic_cast(OBJECT(dev), TYPE_HV_BALLOON)) { 1445 pc_hv_balloon_plug(hotplug_dev, dev, errp); 1446 } 1447 } 1448 1449 static void pc_machine_device_unplug_request_cb(HotplugHandler *hotplug_dev, 1450 DeviceState *dev, Error **errp) 1451 { 1452 if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM)) { 1453 pc_memory_unplug_request(hotplug_dev, dev, errp); 1454 } else if (object_dynamic_cast(OBJECT(dev), TYPE_CPU)) { 1455 x86_cpu_unplug_request_cb(hotplug_dev, dev, errp); 1456 } else if (object_dynamic_cast(OBJECT(dev), TYPE_VIRTIO_MD_PCI)) { 1457 virtio_md_pci_unplug_request(VIRTIO_MD_PCI(dev), MACHINE(hotplug_dev), 1458 errp); 1459 } else { 1460 error_setg(errp, "acpi: device unplug request for not supported device" 1461 " type: %s", object_get_typename(OBJECT(dev))); 1462 } 1463 } 1464 1465 static void pc_machine_device_unplug_cb(HotplugHandler *hotplug_dev, 1466 DeviceState *dev, Error **errp) 1467 { 1468 if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM)) { 1469 pc_memory_unplug(hotplug_dev, dev, errp); 1470 } else if (object_dynamic_cast(OBJECT(dev), TYPE_CPU)) { 1471 x86_cpu_unplug_cb(hotplug_dev, dev, errp); 1472 } else if (object_dynamic_cast(OBJECT(dev), TYPE_VIRTIO_MD_PCI)) { 1473 virtio_md_pci_unplug(VIRTIO_MD_PCI(dev), MACHINE(hotplug_dev), errp); 1474 } else { 1475 error_setg(errp, "acpi: device unplug for not supported device" 1476 " type: %s", object_get_typename(OBJECT(dev))); 1477 } 1478 } 1479 1480 static HotplugHandler *pc_get_hotplug_handler(MachineState *machine, 1481 DeviceState *dev) 1482 { 1483 if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM) || 1484 object_dynamic_cast(OBJECT(dev), TYPE_CPU) || 1485 object_dynamic_cast(OBJECT(dev), TYPE_VIRTIO_MD_PCI) || 1486 object_dynamic_cast(OBJECT(dev), TYPE_VIRTIO_IOMMU_PCI) || 1487 object_dynamic_cast(OBJECT(dev), TYPE_HV_BALLOON) || 1488 object_dynamic_cast(OBJECT(dev), TYPE_X86_IOMMU_DEVICE)) { 1489 return HOTPLUG_HANDLER(machine); 1490 } 1491 1492 return NULL; 1493 } 1494 1495 static void pc_machine_get_vmport(Object *obj, Visitor *v, const char *name, 1496 void *opaque, Error **errp) 1497 { 1498 PCMachineState *pcms = PC_MACHINE(obj); 1499 OnOffAuto vmport = pcms->vmport; 1500 1501 visit_type_OnOffAuto(v, name, &vmport, errp); 1502 } 1503 1504 static void pc_machine_set_vmport(Object *obj, Visitor *v, const char *name, 1505 void *opaque, Error **errp) 1506 { 1507 PCMachineState *pcms = PC_MACHINE(obj); 1508 1509 visit_type_OnOffAuto(v, name, &pcms->vmport, errp); 1510 } 1511 1512 static bool pc_machine_get_fd_bootchk(Object *obj, Error **errp) 1513 { 1514 PCMachineState *pcms = PC_MACHINE(obj); 1515 1516 return pcms->fd_bootchk; 1517 } 1518 1519 static void pc_machine_set_fd_bootchk(Object *obj, bool value, Error **errp) 1520 { 1521 PCMachineState *pcms = PC_MACHINE(obj); 1522 1523 pcms->fd_bootchk = value; 1524 } 1525 1526 static bool pc_machine_get_smbus(Object *obj, Error **errp) 1527 { 1528 PCMachineState *pcms = PC_MACHINE(obj); 1529 1530 return pcms->smbus_enabled; 1531 } 1532 1533 static void pc_machine_set_smbus(Object *obj, bool value, Error **errp) 1534 { 1535 PCMachineState *pcms = PC_MACHINE(obj); 1536 1537 pcms->smbus_enabled = value; 1538 } 1539 1540 static bool pc_machine_get_sata(Object *obj, Error **errp) 1541 { 1542 PCMachineState *pcms = PC_MACHINE(obj); 1543 1544 return pcms->sata_enabled; 1545 } 1546 1547 static void pc_machine_set_sata(Object *obj, bool value, Error **errp) 1548 { 1549 PCMachineState *pcms = PC_MACHINE(obj); 1550 1551 pcms->sata_enabled = value; 1552 } 1553 1554 static bool pc_machine_get_hpet(Object *obj, Error **errp) 1555 { 1556 PCMachineState *pcms = PC_MACHINE(obj); 1557 1558 return pcms->hpet_enabled; 1559 } 1560 1561 static void pc_machine_set_hpet(Object *obj, bool value, Error **errp) 1562 { 1563 PCMachineState *pcms = PC_MACHINE(obj); 1564 1565 pcms->hpet_enabled = value; 1566 } 1567 1568 static bool pc_machine_get_i8042(Object *obj, Error **errp) 1569 { 1570 PCMachineState *pcms = PC_MACHINE(obj); 1571 1572 return pcms->i8042_enabled; 1573 } 1574 1575 static void pc_machine_set_i8042(Object *obj, bool value, Error **errp) 1576 { 1577 PCMachineState *pcms = PC_MACHINE(obj); 1578 1579 pcms->i8042_enabled = value; 1580 } 1581 1582 static bool pc_machine_get_default_bus_bypass_iommu(Object *obj, Error **errp) 1583 { 1584 PCMachineState *pcms = PC_MACHINE(obj); 1585 1586 return pcms->default_bus_bypass_iommu; 1587 } 1588 1589 static void pc_machine_set_default_bus_bypass_iommu(Object *obj, bool value, 1590 Error **errp) 1591 { 1592 PCMachineState *pcms = PC_MACHINE(obj); 1593 1594 pcms->default_bus_bypass_iommu = value; 1595 } 1596 1597 static void pc_machine_get_smbios_ep(Object *obj, Visitor *v, const char *name, 1598 void *opaque, Error **errp) 1599 { 1600 PCMachineState *pcms = PC_MACHINE(obj); 1601 SmbiosEntryPointType smbios_entry_point_type = pcms->smbios_entry_point_type; 1602 1603 visit_type_SmbiosEntryPointType(v, name, &smbios_entry_point_type, errp); 1604 } 1605 1606 static void pc_machine_set_smbios_ep(Object *obj, Visitor *v, const char *name, 1607 void *opaque, Error **errp) 1608 { 1609 PCMachineState *pcms = PC_MACHINE(obj); 1610 1611 visit_type_SmbiosEntryPointType(v, name, &pcms->smbios_entry_point_type, errp); 1612 } 1613 1614 static void pc_machine_get_max_ram_below_4g(Object *obj, Visitor *v, 1615 const char *name, void *opaque, 1616 Error **errp) 1617 { 1618 PCMachineState *pcms = PC_MACHINE(obj); 1619 uint64_t value = pcms->max_ram_below_4g; 1620 1621 visit_type_size(v, name, &value, errp); 1622 } 1623 1624 static void pc_machine_set_max_ram_below_4g(Object *obj, Visitor *v, 1625 const char *name, void *opaque, 1626 Error **errp) 1627 { 1628 PCMachineState *pcms = PC_MACHINE(obj); 1629 uint64_t value; 1630 1631 if (!visit_type_size(v, name, &value, errp)) { 1632 return; 1633 } 1634 if (value > 4 * GiB) { 1635 error_setg(errp, 1636 "Machine option 'max-ram-below-4g=%"PRIu64 1637 "' expects size less than or equal to 4G", value); 1638 return; 1639 } 1640 1641 if (value < 1 * MiB) { 1642 warn_report("Only %" PRIu64 " bytes of RAM below the 4GiB boundary," 1643 "BIOS may not work with less than 1MiB", value); 1644 } 1645 1646 pcms->max_ram_below_4g = value; 1647 } 1648 1649 static void pc_machine_get_max_fw_size(Object *obj, Visitor *v, 1650 const char *name, void *opaque, 1651 Error **errp) 1652 { 1653 PCMachineState *pcms = PC_MACHINE(obj); 1654 uint64_t value = pcms->max_fw_size; 1655 1656 visit_type_size(v, name, &value, errp); 1657 } 1658 1659 static void pc_machine_set_max_fw_size(Object *obj, Visitor *v, 1660 const char *name, void *opaque, 1661 Error **errp) 1662 { 1663 PCMachineState *pcms = PC_MACHINE(obj); 1664 uint64_t value; 1665 1666 if (!visit_type_size(v, name, &value, errp)) { 1667 return; 1668 } 1669 1670 /* 1671 * We don't have a theoretically justifiable exact lower bound on the base 1672 * address of any flash mapping. In practice, the IO-APIC MMIO range is 1673 * [0xFEE00000..0xFEE01000] -- see IO_APIC_DEFAULT_ADDRESS --, leaving free 1674 * only 18MiB-4KiB below 4GiB. For now, restrict the cumulative mapping to 1675 * 16MiB in size. 1676 */ 1677 if (value > 16 * MiB) { 1678 error_setg(errp, 1679 "User specified max allowed firmware size %" PRIu64 " is " 1680 "greater than 16MiB. If combined firmware size exceeds " 1681 "16MiB the system may not boot, or experience intermittent" 1682 "stability issues.", 1683 value); 1684 return; 1685 } 1686 1687 pcms->max_fw_size = value; 1688 } 1689 1690 1691 static void pc_machine_initfn(Object *obj) 1692 { 1693 PCMachineState *pcms = PC_MACHINE(obj); 1694 PCMachineClass *pcmc = PC_MACHINE_GET_CLASS(pcms); 1695 1696 #ifdef CONFIG_VMPORT 1697 pcms->vmport = ON_OFF_AUTO_AUTO; 1698 #else 1699 pcms->vmport = ON_OFF_AUTO_OFF; 1700 #endif /* CONFIG_VMPORT */ 1701 pcms->max_ram_below_4g = 0; /* use default */ 1702 pcms->smbios_entry_point_type = pcmc->default_smbios_ep_type; 1703 pcms->south_bridge = pcmc->default_south_bridge; 1704 1705 /* acpi build is enabled by default if machine supports it */ 1706 pcms->acpi_build_enabled = pcmc->has_acpi_build; 1707 pcms->smbus_enabled = true; 1708 pcms->sata_enabled = true; 1709 pcms->i8042_enabled = true; 1710 pcms->max_fw_size = 8 * MiB; 1711 #if defined(CONFIG_HPET) 1712 pcms->hpet_enabled = true; 1713 #endif 1714 pcms->fd_bootchk = true; 1715 pcms->default_bus_bypass_iommu = false; 1716 1717 pc_system_flash_create(pcms); 1718 pcms->pcspk = isa_new(TYPE_PC_SPEAKER); 1719 object_property_add_alias(OBJECT(pcms), "pcspk-audiodev", 1720 OBJECT(pcms->pcspk), "audiodev"); 1721 if (pcmc->pci_enabled) { 1722 cxl_machine_init(obj, &pcms->cxl_devices_state); 1723 } 1724 } 1725 1726 static void pc_machine_reset(MachineState *machine, ResetType type) 1727 { 1728 CPUState *cs; 1729 X86CPU *cpu; 1730 1731 qemu_devices_reset(type); 1732 1733 /* Reset APIC after devices have been reset to cancel 1734 * any changes that qemu_devices_reset() might have done. 1735 */ 1736 CPU_FOREACH(cs) { 1737 cpu = X86_CPU(cs); 1738 1739 x86_cpu_after_reset(cpu); 1740 } 1741 } 1742 1743 static void pc_machine_wakeup(MachineState *machine) 1744 { 1745 cpu_synchronize_all_states(); 1746 pc_machine_reset(machine, RESET_TYPE_WAKEUP); 1747 cpu_synchronize_all_post_reset(); 1748 } 1749 1750 static bool pc_hotplug_allowed(MachineState *ms, DeviceState *dev, Error **errp) 1751 { 1752 X86IOMMUState *iommu = x86_iommu_get_default(); 1753 IntelIOMMUState *intel_iommu; 1754 1755 if (iommu && 1756 object_dynamic_cast((Object *)iommu, TYPE_INTEL_IOMMU_DEVICE) && 1757 object_dynamic_cast((Object *)dev, "vfio-pci")) { 1758 intel_iommu = INTEL_IOMMU_DEVICE(iommu); 1759 if (!intel_iommu->caching_mode) { 1760 error_setg(errp, "Device assignment is not allowed without " 1761 "enabling caching-mode=on for Intel IOMMU."); 1762 return false; 1763 } 1764 } 1765 1766 return true; 1767 } 1768 1769 static void pc_machine_class_init(ObjectClass *oc, const void *data) 1770 { 1771 MachineClass *mc = MACHINE_CLASS(oc); 1772 X86MachineClass *x86mc = X86_MACHINE_CLASS(oc); 1773 PCMachineClass *pcmc = PC_MACHINE_CLASS(oc); 1774 HotplugHandlerClass *hc = HOTPLUG_HANDLER_CLASS(oc); 1775 1776 pcmc->pci_enabled = true; 1777 pcmc->has_acpi_build = true; 1778 pcmc->smbios_defaults = true; 1779 pcmc->gigabyte_align = true; 1780 pcmc->has_reserved_memory = true; 1781 pcmc->enforce_amd_1tb_hole = true; 1782 pcmc->isa_bios_alias = true; 1783 pcmc->pvh_enabled = true; 1784 pcmc->kvmclock_create_always = true; 1785 x86mc->apic_xrupt_override = true; 1786 assert(!mc->get_hotplug_handler); 1787 mc->get_hotplug_handler = pc_get_hotplug_handler; 1788 mc->hotplug_allowed = pc_hotplug_allowed; 1789 mc->auto_enable_numa_with_memhp = true; 1790 mc->auto_enable_numa_with_memdev = true; 1791 mc->has_hotpluggable_cpus = true; 1792 mc->default_boot_order = "cad"; 1793 mc->block_default_type = IF_IDE; 1794 mc->max_cpus = 255; 1795 mc->reset = pc_machine_reset; 1796 mc->wakeup = pc_machine_wakeup; 1797 hc->pre_plug = pc_machine_device_pre_plug_cb; 1798 hc->plug = pc_machine_device_plug_cb; 1799 hc->unplug_request = pc_machine_device_unplug_request_cb; 1800 hc->unplug = pc_machine_device_unplug_cb; 1801 mc->default_cpu_type = TARGET_DEFAULT_CPU_TYPE; 1802 mc->nvdimm_supported = true; 1803 mc->smp_props.dies_supported = true; 1804 mc->smp_props.modules_supported = true; 1805 mc->smp_props.cache_supported[CACHE_LEVEL_AND_TYPE_L1D] = true; 1806 mc->smp_props.cache_supported[CACHE_LEVEL_AND_TYPE_L1I] = true; 1807 mc->smp_props.cache_supported[CACHE_LEVEL_AND_TYPE_L2] = true; 1808 mc->smp_props.cache_supported[CACHE_LEVEL_AND_TYPE_L3] = true; 1809 mc->default_ram_id = "pc.ram"; 1810 pcmc->default_smbios_ep_type = SMBIOS_ENTRY_POINT_TYPE_AUTO; 1811 1812 object_class_property_add(oc, PC_MACHINE_MAX_RAM_BELOW_4G, "size", 1813 pc_machine_get_max_ram_below_4g, pc_machine_set_max_ram_below_4g, 1814 NULL, NULL); 1815 object_class_property_set_description(oc, PC_MACHINE_MAX_RAM_BELOW_4G, 1816 "Maximum ram below the 4G boundary (32bit boundary)"); 1817 1818 object_class_property_add(oc, PC_MACHINE_VMPORT, "OnOffAuto", 1819 pc_machine_get_vmport, pc_machine_set_vmport, 1820 NULL, NULL); 1821 object_class_property_set_description(oc, PC_MACHINE_VMPORT, 1822 "Enable vmport (pc & q35)"); 1823 1824 object_class_property_add_bool(oc, PC_MACHINE_SMBUS, 1825 pc_machine_get_smbus, pc_machine_set_smbus); 1826 object_class_property_set_description(oc, PC_MACHINE_SMBUS, 1827 "Enable/disable system management bus"); 1828 1829 object_class_property_add_bool(oc, PC_MACHINE_SATA, 1830 pc_machine_get_sata, pc_machine_set_sata); 1831 object_class_property_set_description(oc, PC_MACHINE_SATA, 1832 "Enable/disable Serial ATA bus"); 1833 1834 object_class_property_add_bool(oc, "hpet", 1835 pc_machine_get_hpet, pc_machine_set_hpet); 1836 object_class_property_set_description(oc, "hpet", 1837 "Enable/disable high precision event timer emulation"); 1838 1839 object_class_property_add_bool(oc, PC_MACHINE_I8042, 1840 pc_machine_get_i8042, pc_machine_set_i8042); 1841 object_class_property_set_description(oc, PC_MACHINE_I8042, 1842 "Enable/disable Intel 8042 PS/2 controller emulation"); 1843 1844 object_class_property_add_bool(oc, "default-bus-bypass-iommu", 1845 pc_machine_get_default_bus_bypass_iommu, 1846 pc_machine_set_default_bus_bypass_iommu); 1847 1848 object_class_property_add(oc, PC_MACHINE_MAX_FW_SIZE, "size", 1849 pc_machine_get_max_fw_size, pc_machine_set_max_fw_size, 1850 NULL, NULL); 1851 object_class_property_set_description(oc, PC_MACHINE_MAX_FW_SIZE, 1852 "Maximum combined firmware size"); 1853 1854 object_class_property_add(oc, PC_MACHINE_SMBIOS_EP, "str", 1855 pc_machine_get_smbios_ep, pc_machine_set_smbios_ep, 1856 NULL, NULL); 1857 object_class_property_set_description(oc, PC_MACHINE_SMBIOS_EP, 1858 "SMBIOS Entry Point type [32, 64]"); 1859 1860 object_class_property_add_bool(oc, "fd-bootchk", 1861 pc_machine_get_fd_bootchk, 1862 pc_machine_set_fd_bootchk); 1863 } 1864 1865 static const TypeInfo pc_machine_info = { 1866 .name = TYPE_PC_MACHINE, 1867 .parent = TYPE_X86_MACHINE, 1868 .abstract = true, 1869 .instance_size = sizeof(PCMachineState), 1870 .instance_init = pc_machine_initfn, 1871 .class_size = sizeof(PCMachineClass), 1872 .class_init = pc_machine_class_init, 1873 .interfaces = (const InterfaceInfo[]) { 1874 { TYPE_HOTPLUG_HANDLER }, 1875 { } 1876 }, 1877 }; 1878 1879 static void pc_machine_register_types(void) 1880 { 1881 type_register_static(&pc_machine_info); 1882 } 1883 1884 type_init(pc_machine_register_types) 1885