1 /* 2 * QEMU PC System Emulator 3 * 4 * Copyright (c) 2003-2004 Fabrice Bellard 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a copy 7 * of this software and associated documentation files (the "Software"), to deal 8 * in the Software without restriction, including without limitation the rights 9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 10 * copies of the Software, and to permit persons to whom the Software is 11 * furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice shall be included in 14 * all copies or substantial portions of the Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN 22 * THE SOFTWARE. 23 */ 24 25 #include "qemu/osdep.h" 26 #include "qemu/units.h" 27 #include "exec/target_page.h" 28 #include "hw/i386/pc.h" 29 #include "hw/char/serial-isa.h" 30 #include "hw/char/parallel.h" 31 #include "hw/hyperv/hv-balloon.h" 32 #include "hw/i386/fw_cfg.h" 33 #include "hw/i386/vmport.h" 34 #include "system/cpus.h" 35 #include "hw/ide/ide-bus.h" 36 #include "hw/timer/hpet.h" 37 #include "hw/loader.h" 38 #include "hw/rtc/mc146818rtc.h" 39 #include "hw/intc/i8259.h" 40 #include "hw/timer/i8254.h" 41 #include "hw/input/i8042.h" 42 #include "hw/audio/pcspk.h" 43 #include "system/system.h" 44 #include "system/xen.h" 45 #include "system/reset.h" 46 #include "kvm/kvm_i386.h" 47 #include "kvm/tdx.h" 48 #include "hw/xen/xen.h" 49 #include "qobject/qlist.h" 50 #include "qemu/error-report.h" 51 #include "hw/acpi/cpu_hotplug.h" 52 #include "acpi-build.h" 53 #include "hw/mem/nvdimm.h" 54 #include "hw/cxl/cxl_host.h" 55 #include "hw/usb.h" 56 #include "hw/i386/intel_iommu.h" 57 #include "hw/net/ne2000-isa.h" 58 #include "hw/virtio/virtio-iommu.h" 59 #include "hw/virtio/virtio-md-pci.h" 60 #include "hw/i386/kvm/xen_overlay.h" 61 #include "hw/i386/kvm/xen_evtchn.h" 62 #include "hw/i386/kvm/xen_gnttab.h" 63 #include "hw/i386/kvm/xen_xenstore.h" 64 #include "hw/mem/memory-device.h" 65 #include "e820_memory_layout.h" 66 #include "trace.h" 67 #include "sev.h" 68 #include CONFIG_DEVICES 69 70 #ifdef CONFIG_XEN_EMU 71 #include "hw/xen/xen-legacy-backend.h" 72 #include "hw/xen/xen-bus.h" 73 #endif 74 75 /* 76 * Helper for setting model-id for CPU models that changed model-id 77 * depending on QEMU versions up to QEMU 2.4. 78 */ 79 #define PC_CPU_MODEL_IDS(v) \ 80 { "qemu32-" TYPE_X86_CPU, "model-id", "QEMU Virtual CPU version " v, },\ 81 { "qemu64-" TYPE_X86_CPU, "model-id", "QEMU Virtual CPU version " v, },\ 82 { "athlon-" TYPE_X86_CPU, "model-id", "QEMU Virtual CPU version " v, }, 83 84 GlobalProperty pc_compat_10_0[] = {}; 85 const size_t pc_compat_10_0_len = G_N_ELEMENTS(pc_compat_10_0); 86 87 GlobalProperty pc_compat_9_2[] = {}; 88 const size_t pc_compat_9_2_len = G_N_ELEMENTS(pc_compat_9_2); 89 90 GlobalProperty pc_compat_9_1[] = { 91 { "ICH9-LPC", "x-smi-swsmi-timer", "off" }, 92 { "ICH9-LPC", "x-smi-periodic-timer", "off" }, 93 { TYPE_INTEL_IOMMU_DEVICE, "stale-tm", "on" }, 94 { TYPE_INTEL_IOMMU_DEVICE, "aw-bits", "39" }, 95 }; 96 const size_t pc_compat_9_1_len = G_N_ELEMENTS(pc_compat_9_1); 97 98 GlobalProperty pc_compat_9_0[] = { 99 { TYPE_X86_CPU, "x-amd-topoext-features-only", "false" }, 100 { TYPE_X86_CPU, "x-l1-cache-per-thread", "false" }, 101 { TYPE_X86_CPU, "guest-phys-bits", "0" }, 102 { "sev-guest", "legacy-vm-type", "on" }, 103 { TYPE_X86_CPU, "legacy-multi-node", "on" }, 104 }; 105 const size_t pc_compat_9_0_len = G_N_ELEMENTS(pc_compat_9_0); 106 107 GlobalProperty pc_compat_8_2[] = {}; 108 const size_t pc_compat_8_2_len = G_N_ELEMENTS(pc_compat_8_2); 109 110 GlobalProperty pc_compat_8_1[] = {}; 111 const size_t pc_compat_8_1_len = G_N_ELEMENTS(pc_compat_8_1); 112 113 GlobalProperty pc_compat_8_0[] = { 114 { "virtio-mem", "unplugged-inaccessible", "auto" }, 115 }; 116 const size_t pc_compat_8_0_len = G_N_ELEMENTS(pc_compat_8_0); 117 118 GlobalProperty pc_compat_7_2[] = { 119 { "ICH9-LPC", "noreboot", "true" }, 120 }; 121 const size_t pc_compat_7_2_len = G_N_ELEMENTS(pc_compat_7_2); 122 123 GlobalProperty pc_compat_7_1[] = {}; 124 const size_t pc_compat_7_1_len = G_N_ELEMENTS(pc_compat_7_1); 125 126 GlobalProperty pc_compat_7_0[] = {}; 127 const size_t pc_compat_7_0_len = G_N_ELEMENTS(pc_compat_7_0); 128 129 GlobalProperty pc_compat_6_2[] = { 130 { "virtio-mem", "unplugged-inaccessible", "off" }, 131 }; 132 const size_t pc_compat_6_2_len = G_N_ELEMENTS(pc_compat_6_2); 133 134 GlobalProperty pc_compat_6_1[] = { 135 { TYPE_X86_CPU, "hv-version-id-build", "0x1bbc" }, 136 { TYPE_X86_CPU, "hv-version-id-major", "0x0006" }, 137 { TYPE_X86_CPU, "hv-version-id-minor", "0x0001" }, 138 { "ICH9-LPC", "x-keep-pci-slot-hpc", "false" }, 139 }; 140 const size_t pc_compat_6_1_len = G_N_ELEMENTS(pc_compat_6_1); 141 142 GlobalProperty pc_compat_6_0[] = { 143 { "qemu64" "-" TYPE_X86_CPU, "family", "6" }, 144 { "qemu64" "-" TYPE_X86_CPU, "model", "6" }, 145 { "qemu64" "-" TYPE_X86_CPU, "stepping", "3" }, 146 { TYPE_X86_CPU, "x-vendor-cpuid-only", "off" }, 147 { "ICH9-LPC", ACPI_PM_PROP_ACPI_PCIHP_BRIDGE, "off" }, 148 { "ICH9-LPC", "x-keep-pci-slot-hpc", "true" }, 149 }; 150 const size_t pc_compat_6_0_len = G_N_ELEMENTS(pc_compat_6_0); 151 152 GlobalProperty pc_compat_5_2[] = { 153 { "ICH9-LPC", "x-smi-cpu-hotunplug", "off" }, 154 }; 155 const size_t pc_compat_5_2_len = G_N_ELEMENTS(pc_compat_5_2); 156 157 GlobalProperty pc_compat_5_1[] = { 158 { "ICH9-LPC", "x-smi-cpu-hotplug", "off" }, 159 { TYPE_X86_CPU, "kvm-msi-ext-dest-id", "off" }, 160 }; 161 const size_t pc_compat_5_1_len = G_N_ELEMENTS(pc_compat_5_1); 162 163 GlobalProperty pc_compat_5_0[] = { 164 }; 165 const size_t pc_compat_5_0_len = G_N_ELEMENTS(pc_compat_5_0); 166 167 GlobalProperty pc_compat_4_2[] = { 168 { "mch", "smbase-smram", "off" }, 169 }; 170 const size_t pc_compat_4_2_len = G_N_ELEMENTS(pc_compat_4_2); 171 172 GlobalProperty pc_compat_4_1[] = {}; 173 const size_t pc_compat_4_1_len = G_N_ELEMENTS(pc_compat_4_1); 174 175 GlobalProperty pc_compat_4_0[] = {}; 176 const size_t pc_compat_4_0_len = G_N_ELEMENTS(pc_compat_4_0); 177 178 GlobalProperty pc_compat_3_1[] = { 179 { "intel-iommu", "dma-drain", "off" }, 180 { "Opteron_G3" "-" TYPE_X86_CPU, "rdtscp", "off" }, 181 { "Opteron_G4" "-" TYPE_X86_CPU, "rdtscp", "off" }, 182 { "Opteron_G4" "-" TYPE_X86_CPU, "npt", "off" }, 183 { "Opteron_G4" "-" TYPE_X86_CPU, "nrip-save", "off" }, 184 { "Opteron_G5" "-" TYPE_X86_CPU, "rdtscp", "off" }, 185 { "Opteron_G5" "-" TYPE_X86_CPU, "npt", "off" }, 186 { "Opteron_G5" "-" TYPE_X86_CPU, "nrip-save", "off" }, 187 { "EPYC" "-" TYPE_X86_CPU, "npt", "off" }, 188 { "EPYC" "-" TYPE_X86_CPU, "nrip-save", "off" }, 189 { "EPYC-IBPB" "-" TYPE_X86_CPU, "npt", "off" }, 190 { "EPYC-IBPB" "-" TYPE_X86_CPU, "nrip-save", "off" }, 191 { "Skylake-Client" "-" TYPE_X86_CPU, "mpx", "on" }, 192 { "Skylake-Client-IBRS" "-" TYPE_X86_CPU, "mpx", "on" }, 193 { "Skylake-Server" "-" TYPE_X86_CPU, "mpx", "on" }, 194 { "Skylake-Server-IBRS" "-" TYPE_X86_CPU, "mpx", "on" }, 195 { "Cascadelake-Server" "-" TYPE_X86_CPU, "mpx", "on" }, 196 { "Icelake-Client" "-" TYPE_X86_CPU, "mpx", "on" }, 197 { "Icelake-Server" "-" TYPE_X86_CPU, "mpx", "on" }, 198 { "Cascadelake-Server" "-" TYPE_X86_CPU, "stepping", "5" }, 199 { TYPE_X86_CPU, "x-intel-pt-auto-level", "off" }, 200 }; 201 const size_t pc_compat_3_1_len = G_N_ELEMENTS(pc_compat_3_1); 202 203 GlobalProperty pc_compat_3_0[] = { 204 { TYPE_X86_CPU, "x-hv-synic-kvm-only", "on" }, 205 { "Skylake-Server" "-" TYPE_X86_CPU, "pku", "off" }, 206 { "Skylake-Server-IBRS" "-" TYPE_X86_CPU, "pku", "off" }, 207 }; 208 const size_t pc_compat_3_0_len = G_N_ELEMENTS(pc_compat_3_0); 209 210 GlobalProperty pc_compat_2_12[] = { 211 { TYPE_X86_CPU, "legacy-cache", "on" }, 212 { TYPE_X86_CPU, "topoext", "off" }, 213 { "EPYC-" TYPE_X86_CPU, "xlevel", "0x8000000a" }, 214 { "EPYC-IBPB-" TYPE_X86_CPU, "xlevel", "0x8000000a" }, 215 }; 216 const size_t pc_compat_2_12_len = G_N_ELEMENTS(pc_compat_2_12); 217 218 GlobalProperty pc_compat_2_11[] = { 219 { TYPE_X86_CPU, "x-migrate-smi-count", "off" }, 220 { "Skylake-Server" "-" TYPE_X86_CPU, "clflushopt", "off" }, 221 }; 222 const size_t pc_compat_2_11_len = G_N_ELEMENTS(pc_compat_2_11); 223 224 GlobalProperty pc_compat_2_10[] = { 225 { TYPE_X86_CPU, "x-hv-max-vps", "0x40" }, 226 { "i440FX-pcihost", "x-pci-hole64-fix", "off" }, 227 { "q35-pcihost", "x-pci-hole64-fix", "off" }, 228 }; 229 const size_t pc_compat_2_10_len = G_N_ELEMENTS(pc_compat_2_10); 230 231 GlobalProperty pc_compat_2_9[] = { 232 { "mch", "extended-tseg-mbytes", "0" }, 233 }; 234 const size_t pc_compat_2_9_len = G_N_ELEMENTS(pc_compat_2_9); 235 236 GlobalProperty pc_compat_2_8[] = { 237 { TYPE_X86_CPU, "tcg-cpuid", "off" }, 238 { "kvmclock", "x-mach-use-reliable-get-clock", "off" }, 239 { "ICH9-LPC", "x-smi-broadcast", "off" }, 240 { TYPE_X86_CPU, "vmware-cpuid-freq", "off" }, 241 { "Haswell-" TYPE_X86_CPU, "stepping", "1" }, 242 }; 243 const size_t pc_compat_2_8_len = G_N_ELEMENTS(pc_compat_2_8); 244 245 GlobalProperty pc_compat_2_7[] = { 246 { TYPE_X86_CPU, "l3-cache", "off" }, 247 { TYPE_X86_CPU, "full-cpuid-auto-level", "off" }, 248 { "Opteron_G3" "-" TYPE_X86_CPU, "family", "15" }, 249 { "Opteron_G3" "-" TYPE_X86_CPU, "model", "6" }, 250 { "Opteron_G3" "-" TYPE_X86_CPU, "stepping", "1" }, 251 { "isa-pcspk", "migrate", "off" }, 252 }; 253 const size_t pc_compat_2_7_len = G_N_ELEMENTS(pc_compat_2_7); 254 255 GlobalProperty pc_compat_2_6[] = { 256 { TYPE_X86_CPU, "cpuid-0xb", "off" }, 257 { "vmxnet3", "romfile", "" }, 258 { TYPE_X86_CPU, "fill-mtrr-mask", "off" }, 259 { "apic-common", "legacy-instance-id", "on", } 260 }; 261 const size_t pc_compat_2_6_len = G_N_ELEMENTS(pc_compat_2_6); 262 263 /* 264 * @PC_FW_DATA: 265 * Size of the chunk of memory at the top of RAM for the BIOS ACPI tables 266 * and other BIOS datastructures. 267 * 268 * BIOS ACPI tables: 128K. Other BIOS datastructures: less than 4K 269 * reported to be used at the moment, 32K should be enough for a while. 270 */ 271 #define PC_FW_DATA (0x20000 + 0x8000) 272 273 GSIState *pc_gsi_create(qemu_irq **irqs, bool pci_enabled) 274 { 275 GSIState *s; 276 277 s = g_new0(GSIState, 1); 278 if (kvm_ioapic_in_kernel()) { 279 kvm_pc_setup_irq_routing(pci_enabled); 280 } 281 *irqs = qemu_allocate_irqs(gsi_handler, s, IOAPIC_NUM_PINS); 282 283 return s; 284 } 285 286 static void ioport80_write(void *opaque, hwaddr addr, uint64_t data, 287 unsigned size) 288 { 289 } 290 291 static uint64_t ioport80_read(void *opaque, hwaddr addr, unsigned size) 292 { 293 return 0xffffffffffffffffULL; 294 } 295 296 /* MS-DOS compatibility mode FPU exception support */ 297 static void ioportF0_write(void *opaque, hwaddr addr, uint64_t data, 298 unsigned size) 299 { 300 if (tcg_enabled()) { 301 cpu_set_ignne(); 302 } 303 } 304 305 static uint64_t ioportF0_read(void *opaque, hwaddr addr, unsigned size) 306 { 307 return 0xffffffffffffffffULL; 308 } 309 310 /* PC cmos mappings */ 311 312 #define REG_EQUIPMENT_BYTE 0x14 313 314 static void cmos_init_hd(MC146818RtcState *s, int type_ofs, int info_ofs, 315 int16_t cylinders, int8_t heads, int8_t sectors) 316 { 317 mc146818rtc_set_cmos_data(s, type_ofs, 47); 318 mc146818rtc_set_cmos_data(s, info_ofs, cylinders); 319 mc146818rtc_set_cmos_data(s, info_ofs + 1, cylinders >> 8); 320 mc146818rtc_set_cmos_data(s, info_ofs + 2, heads); 321 mc146818rtc_set_cmos_data(s, info_ofs + 3, 0xff); 322 mc146818rtc_set_cmos_data(s, info_ofs + 4, 0xff); 323 mc146818rtc_set_cmos_data(s, info_ofs + 5, 0xc0 | ((heads > 8) << 3)); 324 mc146818rtc_set_cmos_data(s, info_ofs + 6, cylinders); 325 mc146818rtc_set_cmos_data(s, info_ofs + 7, cylinders >> 8); 326 mc146818rtc_set_cmos_data(s, info_ofs + 8, sectors); 327 } 328 329 /* convert boot_device letter to something recognizable by the bios */ 330 static int boot_device2nibble(char boot_device) 331 { 332 switch(boot_device) { 333 case 'a': 334 case 'b': 335 return 0x01; /* floppy boot */ 336 case 'c': 337 return 0x02; /* hard drive boot */ 338 case 'd': 339 return 0x03; /* CD-ROM boot */ 340 case 'n': 341 return 0x04; /* Network boot */ 342 } 343 return 0; 344 } 345 346 static void set_boot_dev(PCMachineState *pcms, MC146818RtcState *s, 347 const char *boot_device, Error **errp) 348 { 349 #define PC_MAX_BOOT_DEVICES 3 350 int nbds, bds[3] = { 0, }; 351 int i; 352 353 nbds = strlen(boot_device); 354 if (nbds > PC_MAX_BOOT_DEVICES) { 355 error_setg(errp, "Too many boot devices for PC"); 356 return; 357 } 358 for (i = 0; i < nbds; i++) { 359 bds[i] = boot_device2nibble(boot_device[i]); 360 if (bds[i] == 0) { 361 error_setg(errp, "Invalid boot device for PC: '%c'", 362 boot_device[i]); 363 return; 364 } 365 } 366 mc146818rtc_set_cmos_data(s, 0x3d, (bds[1] << 4) | bds[0]); 367 mc146818rtc_set_cmos_data(s, 0x38, (bds[2] << 4) | !pcms->fd_bootchk); 368 } 369 370 static void pc_boot_set(void *opaque, const char *boot_device, Error **errp) 371 { 372 PCMachineState *pcms = opaque; 373 X86MachineState *x86ms = X86_MACHINE(pcms); 374 375 set_boot_dev(pcms, MC146818_RTC(x86ms->rtc), boot_device, errp); 376 } 377 378 static void pc_cmos_init_floppy(MC146818RtcState *rtc_state, ISADevice *floppy) 379 { 380 int val, nb; 381 FloppyDriveType fd_type[2] = { FLOPPY_DRIVE_TYPE_NONE, 382 FLOPPY_DRIVE_TYPE_NONE }; 383 384 #ifdef CONFIG_FDC_ISA 385 /* floppy type */ 386 if (floppy) { 387 for (int i = 0; i < 2; i++) { 388 fd_type[i] = isa_fdc_get_drive_type(floppy, i); 389 } 390 } 391 #endif 392 393 val = (cmos_get_fd_drive_type(fd_type[0]) << 4) | 394 cmos_get_fd_drive_type(fd_type[1]); 395 mc146818rtc_set_cmos_data(rtc_state, 0x10, val); 396 397 val = mc146818rtc_get_cmos_data(rtc_state, REG_EQUIPMENT_BYTE); 398 nb = 0; 399 if (fd_type[0] != FLOPPY_DRIVE_TYPE_NONE) { 400 nb++; 401 } 402 if (fd_type[1] != FLOPPY_DRIVE_TYPE_NONE) { 403 nb++; 404 } 405 switch (nb) { 406 case 0: 407 break; 408 case 1: 409 val |= 0x01; /* 1 drive, ready for boot */ 410 break; 411 case 2: 412 val |= 0x41; /* 2 drives, ready for boot */ 413 break; 414 } 415 mc146818rtc_set_cmos_data(rtc_state, REG_EQUIPMENT_BYTE, val); 416 } 417 418 typedef struct check_fdc_state { 419 ISADevice *floppy; 420 bool multiple; 421 } CheckFdcState; 422 423 static int check_fdc(Object *obj, void *opaque) 424 { 425 CheckFdcState *state = opaque; 426 Object *fdc; 427 uint32_t iobase; 428 Error *local_err = NULL; 429 430 fdc = object_dynamic_cast(obj, TYPE_ISA_FDC); 431 if (!fdc) { 432 return 0; 433 } 434 435 iobase = object_property_get_uint(obj, "iobase", &local_err); 436 if (local_err || iobase != 0x3f0) { 437 error_free(local_err); 438 return 0; 439 } 440 441 if (state->floppy) { 442 state->multiple = true; 443 } else { 444 state->floppy = ISA_DEVICE(obj); 445 } 446 return 0; 447 } 448 449 static const char * const fdc_container_path[] = { 450 "unattached", "peripheral", "peripheral-anon" 451 }; 452 453 /* 454 * Locate the FDC at IO address 0x3f0, in order to configure the CMOS registers 455 * and ACPI objects. 456 */ 457 static ISADevice *pc_find_fdc0(void) 458 { 459 int i; 460 Object *container; 461 CheckFdcState state = { 0 }; 462 463 for (i = 0; i < ARRAY_SIZE(fdc_container_path); i++) { 464 container = machine_get_container(fdc_container_path[i]); 465 object_child_foreach(container, check_fdc, &state); 466 } 467 468 if (state.multiple) { 469 warn_report("multiple floppy disk controllers with " 470 "iobase=0x3f0 have been found"); 471 error_printf("the one being picked for CMOS setup might not reflect " 472 "your intent"); 473 } 474 475 return state.floppy; 476 } 477 478 static void pc_cmos_init_late(PCMachineState *pcms) 479 { 480 X86MachineState *x86ms = X86_MACHINE(pcms); 481 MC146818RtcState *s = MC146818_RTC(x86ms->rtc); 482 int16_t cylinders; 483 int8_t heads, sectors; 484 int val; 485 int i, trans; 486 487 val = 0; 488 if (pcms->idebus[0] && 489 ide_get_geometry(pcms->idebus[0], 0, 490 &cylinders, &heads, §ors) >= 0) { 491 cmos_init_hd(s, 0x19, 0x1b, cylinders, heads, sectors); 492 val |= 0xf0; 493 } 494 if (pcms->idebus[0] && 495 ide_get_geometry(pcms->idebus[0], 1, 496 &cylinders, &heads, §ors) >= 0) { 497 cmos_init_hd(s, 0x1a, 0x24, cylinders, heads, sectors); 498 val |= 0x0f; 499 } 500 mc146818rtc_set_cmos_data(s, 0x12, val); 501 502 val = 0; 503 for (i = 0; i < 4; i++) { 504 /* NOTE: ide_get_geometry() returns the physical 505 geometry. It is always such that: 1 <= sects <= 63, 1 506 <= heads <= 16, 1 <= cylinders <= 16383. The BIOS 507 geometry can be different if a translation is done. */ 508 BusState *idebus = pcms->idebus[i / 2]; 509 if (idebus && 510 ide_get_geometry(idebus, i % 2, 511 &cylinders, &heads, §ors) >= 0) { 512 trans = ide_get_bios_chs_trans(idebus, i % 2) - 1; 513 assert((trans & ~3) == 0); 514 val |= trans << (i * 2); 515 } 516 } 517 mc146818rtc_set_cmos_data(s, 0x39, val); 518 519 pc_cmos_init_floppy(s, pc_find_fdc0()); 520 521 /* various important CMOS locations needed by PC/Bochs bios */ 522 523 /* memory size */ 524 /* base memory (first MiB) */ 525 val = MIN(x86ms->below_4g_mem_size / KiB, 640); 526 mc146818rtc_set_cmos_data(s, 0x15, val); 527 mc146818rtc_set_cmos_data(s, 0x16, val >> 8); 528 /* extended memory (next 64MiB) */ 529 if (x86ms->below_4g_mem_size > 1 * MiB) { 530 val = (x86ms->below_4g_mem_size - 1 * MiB) / KiB; 531 } else { 532 val = 0; 533 } 534 if (val > 65535) 535 val = 65535; 536 mc146818rtc_set_cmos_data(s, 0x17, val); 537 mc146818rtc_set_cmos_data(s, 0x18, val >> 8); 538 mc146818rtc_set_cmos_data(s, 0x30, val); 539 mc146818rtc_set_cmos_data(s, 0x31, val >> 8); 540 /* memory between 16MiB and 4GiB */ 541 if (x86ms->below_4g_mem_size > 16 * MiB) { 542 val = (x86ms->below_4g_mem_size - 16 * MiB) / (64 * KiB); 543 } else { 544 val = 0; 545 } 546 if (val > 65535) 547 val = 65535; 548 mc146818rtc_set_cmos_data(s, 0x34, val); 549 mc146818rtc_set_cmos_data(s, 0x35, val >> 8); 550 /* memory above 4GiB */ 551 val = x86ms->above_4g_mem_size / 65536; 552 mc146818rtc_set_cmos_data(s, 0x5b, val); 553 mc146818rtc_set_cmos_data(s, 0x5c, val >> 8); 554 mc146818rtc_set_cmos_data(s, 0x5d, val >> 16); 555 556 val = 0; 557 val |= 0x02; /* FPU is there */ 558 val |= 0x04; /* PS/2 mouse installed */ 559 mc146818rtc_set_cmos_data(s, REG_EQUIPMENT_BYTE, val); 560 } 561 562 static void handle_a20_line_change(void *opaque, int irq, int level) 563 { 564 X86CPU *cpu = opaque; 565 566 /* XXX: send to all CPUs ? */ 567 /* XXX: add logic to handle multiple A20 line sources */ 568 x86_cpu_set_a20(cpu, level); 569 } 570 571 #define NE2000_NB_MAX 6 572 573 static const int ne2000_io[NE2000_NB_MAX] = { 0x300, 0x320, 0x340, 0x360, 574 0x280, 0x380 }; 575 static const int ne2000_irq[NE2000_NB_MAX] = { 9, 10, 11, 3, 4, 5 }; 576 577 static gboolean pc_init_ne2k_isa(ISABus *bus, NICInfo *nd, Error **errp) 578 { 579 static int nb_ne2k = 0; 580 581 if (nb_ne2k == NE2000_NB_MAX) { 582 error_setg(errp, 583 "maximum number of ISA NE2000 devices exceeded"); 584 return false; 585 } 586 isa_ne2000_init(bus, ne2000_io[nb_ne2k], 587 ne2000_irq[nb_ne2k], nd); 588 nb_ne2k++; 589 return true; 590 } 591 592 void pc_acpi_smi_interrupt(void *opaque, int irq, int level) 593 { 594 X86CPU *cpu = opaque; 595 596 if (level) { 597 cpu_interrupt(CPU(cpu), CPU_INTERRUPT_SMI); 598 } 599 } 600 601 static 602 void pc_machine_done(Notifier *notifier, void *data) 603 { 604 PCMachineState *pcms = container_of(notifier, 605 PCMachineState, machine_done); 606 X86MachineState *x86ms = X86_MACHINE(pcms); 607 608 cxl_hook_up_pxb_registers(pcms->pcibus, &pcms->cxl_devices_state, 609 &error_fatal); 610 611 if (pcms->cxl_devices_state.is_enabled) { 612 cxl_fmws_link_targets(&pcms->cxl_devices_state, &error_fatal); 613 } 614 615 /* set the number of CPUs */ 616 x86_rtc_set_cpus_count(x86ms->rtc, x86ms->boot_cpus); 617 618 pci_bus_add_fw_cfg_extra_pci_roots(x86ms->fw_cfg, pcms->pcibus, 619 &error_abort); 620 621 acpi_setup(); 622 if (x86ms->fw_cfg) { 623 fw_cfg_build_smbios(pcms, x86ms->fw_cfg, pcms->smbios_entry_point_type); 624 fw_cfg_add_e820(x86ms->fw_cfg); 625 fw_cfg_build_feature_control(MACHINE(pcms), x86ms->fw_cfg); 626 /* update FW_CFG_NB_CPUS to account for -device added CPUs */ 627 fw_cfg_modify_i16(x86ms->fw_cfg, FW_CFG_NB_CPUS, x86ms->boot_cpus); 628 } 629 630 pc_cmos_init_late(pcms); 631 } 632 633 /* setup pci memory address space mapping into system address space */ 634 void pc_pci_as_mapping_init(MemoryRegion *system_memory, 635 MemoryRegion *pci_address_space) 636 { 637 /* Set to lower priority than RAM */ 638 memory_region_add_subregion_overlap(system_memory, 0x0, 639 pci_address_space, -1); 640 } 641 642 void xen_load_linux(PCMachineState *pcms) 643 { 644 int i; 645 FWCfgState *fw_cfg; 646 PCMachineClass *pcmc = PC_MACHINE_GET_CLASS(pcms); 647 X86MachineState *x86ms = X86_MACHINE(pcms); 648 649 assert(MACHINE(pcms)->kernel_filename != NULL); 650 651 fw_cfg = fw_cfg_init_io_dma(FW_CFG_IO_BASE, FW_CFG_IO_BASE + 4, 652 &address_space_memory); 653 fw_cfg_add_i16(fw_cfg, FW_CFG_NB_CPUS, x86ms->boot_cpus); 654 rom_set_fw(fw_cfg); 655 656 x86_load_linux(x86ms, fw_cfg, PC_FW_DATA, pcmc->pvh_enabled); 657 for (i = 0; i < nb_option_roms; i++) { 658 assert(!strcmp(option_rom[i].name, "linuxboot.bin") || 659 !strcmp(option_rom[i].name, "linuxboot_dma.bin") || 660 !strcmp(option_rom[i].name, "pvh.bin") || 661 !strcmp(option_rom[i].name, "multiboot.bin") || 662 !strcmp(option_rom[i].name, "multiboot_dma.bin")); 663 rom_add_option(option_rom[i].name, option_rom[i].bootindex); 664 } 665 x86ms->fw_cfg = fw_cfg; 666 } 667 668 #define PC_ROM_MIN_VGA 0xc0000 669 #define PC_ROM_MIN_OPTION 0xc8000 670 #define PC_ROM_MAX 0xe0000 671 #define PC_ROM_ALIGN 0x800 672 #define PC_ROM_SIZE (PC_ROM_MAX - PC_ROM_MIN_VGA) 673 674 static hwaddr pc_above_4g_end(PCMachineState *pcms) 675 { 676 X86MachineState *x86ms = X86_MACHINE(pcms); 677 678 if (pcms->sgx_epc.size != 0) { 679 return sgx_epc_above_4g_end(&pcms->sgx_epc); 680 } 681 682 return x86ms->above_4g_mem_start + x86ms->above_4g_mem_size; 683 } 684 685 static void pc_get_device_memory_range(PCMachineState *pcms, 686 hwaddr *base, 687 ram_addr_t *device_mem_size) 688 { 689 MachineState *machine = MACHINE(pcms); 690 ram_addr_t size; 691 hwaddr addr; 692 693 size = machine->maxram_size - machine->ram_size; 694 addr = ROUND_UP(pc_above_4g_end(pcms), 1 * GiB); 695 696 /* size device region assuming 1G page max alignment per slot */ 697 size += (1 * GiB) * machine->ram_slots; 698 699 *base = addr; 700 *device_mem_size = size; 701 } 702 703 static uint64_t pc_get_cxl_range_start(PCMachineState *pcms) 704 { 705 PCMachineClass *pcmc = PC_MACHINE_GET_CLASS(pcms); 706 MachineState *ms = MACHINE(pcms); 707 hwaddr cxl_base; 708 ram_addr_t size; 709 710 if (pcmc->has_reserved_memory && 711 (ms->ram_size < ms->maxram_size)) { 712 pc_get_device_memory_range(pcms, &cxl_base, &size); 713 cxl_base += size; 714 } else { 715 cxl_base = pc_above_4g_end(pcms); 716 } 717 718 return cxl_base; 719 } 720 721 static uint64_t pc_get_cxl_range_end(PCMachineState *pcms) 722 { 723 uint64_t start = pc_get_cxl_range_start(pcms) + MiB; 724 725 if (pcms->cxl_devices_state.fixed_windows) { 726 GList *it; 727 728 start = ROUND_UP(start, 256 * MiB); 729 for (it = pcms->cxl_devices_state.fixed_windows; it; it = it->next) { 730 CXLFixedWindow *fw = it->data; 731 start += fw->size; 732 } 733 } 734 735 return start; 736 } 737 738 static hwaddr pc_max_used_gpa(PCMachineState *pcms, uint64_t pci_hole64_size) 739 { 740 X86CPU *cpu = X86_CPU(first_cpu); 741 PCMachineClass *pcmc = PC_MACHINE_GET_CLASS(pcms); 742 MachineState *ms = MACHINE(pcms); 743 744 if (cpu->env.features[FEAT_8000_0001_EDX] & CPUID_EXT2_LM) { 745 /* 64-bit systems */ 746 return pc_pci_hole64_start() + pci_hole64_size - 1; 747 } 748 749 /* 32-bit systems */ 750 if (pcmc->broken_32bit_mem_addr_check) { 751 /* old value for compatibility reasons */ 752 return ((hwaddr)1 << cpu->phys_bits) - 1; 753 } 754 755 /* 756 * 32-bit systems don't have hole64 but they might have a region for 757 * memory devices. Even if additional hotplugged memory devices might 758 * not be usable by most guest OSes, we need to still consider them for 759 * calculating the highest possible GPA so that we can properly report 760 * if someone configures them on a CPU that cannot possibly address them. 761 */ 762 if (pcmc->has_reserved_memory && 763 (ms->ram_size < ms->maxram_size)) { 764 hwaddr devmem_start; 765 ram_addr_t devmem_size; 766 767 pc_get_device_memory_range(pcms, &devmem_start, &devmem_size); 768 devmem_start += devmem_size; 769 return devmem_start - 1; 770 } 771 772 /* configuration without any memory hotplug */ 773 return pc_above_4g_end(pcms) - 1; 774 } 775 776 /* 777 * AMD systems with an IOMMU have an additional hole close to the 778 * 1Tb, which are special GPAs that cannot be DMA mapped. Depending 779 * on kernel version, VFIO may or may not let you DMA map those ranges. 780 * Starting Linux v5.4 we validate it, and can't create guests on AMD machines 781 * with certain memory sizes. It's also wrong to use those IOVA ranges 782 * in detriment of leading to IOMMU INVALID_DEVICE_REQUEST or worse. 783 * The ranges reserved for Hyper-Transport are: 784 * 785 * FD_0000_0000h - FF_FFFF_FFFFh 786 * 787 * The ranges represent the following: 788 * 789 * Base Address Top Address Use 790 * 791 * FD_0000_0000h FD_F7FF_FFFFh Reserved interrupt address space 792 * FD_F800_0000h FD_F8FF_FFFFh Interrupt/EOI IntCtl 793 * FD_F900_0000h FD_F90F_FFFFh Legacy PIC IACK 794 * FD_F910_0000h FD_F91F_FFFFh System Management 795 * FD_F920_0000h FD_FAFF_FFFFh Reserved Page Tables 796 * FD_FB00_0000h FD_FBFF_FFFFh Address Translation 797 * FD_FC00_0000h FD_FDFF_FFFFh I/O Space 798 * FD_FE00_0000h FD_FFFF_FFFFh Configuration 799 * FE_0000_0000h FE_1FFF_FFFFh Extended Configuration/Device Messages 800 * FE_2000_0000h FF_FFFF_FFFFh Reserved 801 * 802 * See AMD IOMMU spec, section 2.1.2 "IOMMU Logical Topology", 803 * Table 3: Special Address Controls (GPA) for more information. 804 */ 805 #define AMD_HT_START 0xfd00000000UL 806 #define AMD_HT_END 0xffffffffffUL 807 #define AMD_ABOVE_1TB_START (AMD_HT_END + 1) 808 #define AMD_HT_SIZE (AMD_ABOVE_1TB_START - AMD_HT_START) 809 810 void pc_memory_init(PCMachineState *pcms, 811 MemoryRegion *system_memory, 812 MemoryRegion *rom_memory, 813 uint64_t pci_hole64_size) 814 { 815 int linux_boot, i; 816 MemoryRegion *option_rom_mr; 817 MemoryRegion *ram_below_4g, *ram_above_4g; 818 FWCfgState *fw_cfg; 819 MachineState *machine = MACHINE(pcms); 820 MachineClass *mc = MACHINE_GET_CLASS(machine); 821 PCMachineClass *pcmc = PC_MACHINE_GET_CLASS(pcms); 822 X86MachineState *x86ms = X86_MACHINE(pcms); 823 hwaddr maxphysaddr, maxusedaddr; 824 hwaddr cxl_base, cxl_resv_end = 0; 825 X86CPU *cpu = X86_CPU(first_cpu); 826 827 assert(machine->ram_size == x86ms->below_4g_mem_size + 828 x86ms->above_4g_mem_size); 829 830 linux_boot = (machine->kernel_filename != NULL); 831 832 /* 833 * The HyperTransport range close to the 1T boundary is unique to AMD 834 * hosts with IOMMUs enabled. Restrict the ram-above-4g relocation 835 * to above 1T to AMD vCPUs only. @enforce_amd_1tb_hole is only false in 836 * older machine types (<= 7.0) for compatibility purposes. 837 */ 838 if (IS_AMD_CPU(&cpu->env) && pcmc->enforce_amd_1tb_hole) { 839 /* Bail out if max possible address does not cross HT range */ 840 if (pc_max_used_gpa(pcms, pci_hole64_size) >= AMD_HT_START) { 841 x86ms->above_4g_mem_start = AMD_ABOVE_1TB_START; 842 } 843 844 /* 845 * Advertise the HT region if address space covers the reserved 846 * region or if we relocate. 847 */ 848 if (cpu->phys_bits >= 40) { 849 e820_add_entry(AMD_HT_START, AMD_HT_SIZE, E820_RESERVED); 850 } 851 } 852 853 /* 854 * phys-bits is required to be appropriately configured 855 * to make sure max used GPA is reachable. 856 */ 857 maxusedaddr = pc_max_used_gpa(pcms, pci_hole64_size); 858 maxphysaddr = ((hwaddr)1 << cpu->phys_bits) - 1; 859 if (maxphysaddr < maxusedaddr) { 860 error_report("Address space limit 0x%"PRIx64" < 0x%"PRIx64 861 " phys-bits too low (%u)", 862 maxphysaddr, maxusedaddr, cpu->phys_bits); 863 exit(EXIT_FAILURE); 864 } 865 866 /* 867 * Split single memory region and use aliases to address portions of it, 868 * done for backwards compatibility with older qemus. 869 */ 870 ram_below_4g = g_malloc(sizeof(*ram_below_4g)); 871 memory_region_init_alias(ram_below_4g, NULL, "ram-below-4g", machine->ram, 872 0, x86ms->below_4g_mem_size); 873 memory_region_add_subregion(system_memory, 0, ram_below_4g); 874 e820_add_entry(0, x86ms->below_4g_mem_size, E820_RAM); 875 if (x86ms->above_4g_mem_size > 0) { 876 ram_above_4g = g_malloc(sizeof(*ram_above_4g)); 877 memory_region_init_alias(ram_above_4g, NULL, "ram-above-4g", 878 machine->ram, 879 x86ms->below_4g_mem_size, 880 x86ms->above_4g_mem_size); 881 memory_region_add_subregion(system_memory, x86ms->above_4g_mem_start, 882 ram_above_4g); 883 e820_add_entry(x86ms->above_4g_mem_start, x86ms->above_4g_mem_size, 884 E820_RAM); 885 } 886 887 if (pcms->sgx_epc.size != 0) { 888 e820_add_entry(pcms->sgx_epc.base, pcms->sgx_epc.size, E820_RESERVED); 889 } 890 891 if (!pcmc->has_reserved_memory && 892 (machine->ram_slots || 893 (machine->maxram_size > machine->ram_size))) { 894 895 error_report("\"-memory 'slots|maxmem'\" is not supported by: %s", 896 mc->name); 897 exit(EXIT_FAILURE); 898 } 899 900 /* initialize device memory address space */ 901 if (pcmc->has_reserved_memory && 902 (machine->ram_size < machine->maxram_size)) { 903 ram_addr_t device_mem_size; 904 hwaddr device_mem_base; 905 906 if (machine->ram_slots > ACPI_MAX_RAM_SLOTS) { 907 error_report("unsupported amount of memory slots: %"PRIu64, 908 machine->ram_slots); 909 exit(EXIT_FAILURE); 910 } 911 912 if (QEMU_ALIGN_UP(machine->maxram_size, 913 TARGET_PAGE_SIZE) != machine->maxram_size) { 914 error_report("maximum memory size must by aligned to multiple of " 915 "%d bytes", TARGET_PAGE_SIZE); 916 exit(EXIT_FAILURE); 917 } 918 919 pc_get_device_memory_range(pcms, &device_mem_base, &device_mem_size); 920 921 if (device_mem_base + device_mem_size < device_mem_size) { 922 error_report("unsupported amount of maximum memory: " RAM_ADDR_FMT, 923 machine->maxram_size); 924 exit(EXIT_FAILURE); 925 } 926 machine_memory_devices_init(machine, device_mem_base, device_mem_size); 927 } 928 929 if (pcms->cxl_devices_state.is_enabled) { 930 MemoryRegion *mr = &pcms->cxl_devices_state.host_mr; 931 hwaddr cxl_size = MiB; 932 933 cxl_base = pc_get_cxl_range_start(pcms); 934 memory_region_init(mr, OBJECT(machine), "cxl_host_reg", cxl_size); 935 memory_region_add_subregion(system_memory, cxl_base, mr); 936 cxl_resv_end = cxl_base + cxl_size; 937 if (pcms->cxl_devices_state.fixed_windows) { 938 hwaddr cxl_fmw_base; 939 GList *it; 940 941 cxl_fmw_base = ROUND_UP(cxl_base + cxl_size, 256 * MiB); 942 for (it = pcms->cxl_devices_state.fixed_windows; it; it = it->next) { 943 CXLFixedWindow *fw = it->data; 944 945 fw->base = cxl_fmw_base; 946 memory_region_init_io(&fw->mr, OBJECT(machine), &cfmws_ops, fw, 947 "cxl-fixed-memory-region", fw->size); 948 memory_region_add_subregion(system_memory, fw->base, &fw->mr); 949 cxl_fmw_base += fw->size; 950 cxl_resv_end = cxl_fmw_base; 951 } 952 } 953 } 954 955 /* Initialize PC system firmware */ 956 pc_system_firmware_init(pcms, rom_memory); 957 958 if (!is_tdx_vm()) { 959 option_rom_mr = g_malloc(sizeof(*option_rom_mr)); 960 if (machine_require_guest_memfd(machine)) { 961 memory_region_init_ram_guest_memfd(option_rom_mr, NULL, "pc.rom", 962 PC_ROM_SIZE, &error_fatal); 963 } else { 964 memory_region_init_ram(option_rom_mr, NULL, "pc.rom", PC_ROM_SIZE, 965 &error_fatal); 966 if (pcmc->pci_enabled) { 967 memory_region_set_readonly(option_rom_mr, true); 968 } 969 } 970 memory_region_add_subregion_overlap(rom_memory, 971 PC_ROM_MIN_VGA, 972 option_rom_mr, 973 1); 974 } 975 976 fw_cfg = fw_cfg_arch_create(machine, 977 x86ms->boot_cpus, x86ms->apic_id_limit); 978 979 rom_set_fw(fw_cfg); 980 981 if (machine->device_memory) { 982 uint64_t *val = g_malloc(sizeof(*val)); 983 uint64_t res_mem_end; 984 985 if (pcms->cxl_devices_state.is_enabled) { 986 res_mem_end = cxl_resv_end; 987 } else { 988 res_mem_end = machine->device_memory->base 989 + memory_region_size(&machine->device_memory->mr); 990 } 991 *val = cpu_to_le64(ROUND_UP(res_mem_end, 1 * GiB)); 992 fw_cfg_add_file(fw_cfg, "etc/reserved-memory-end", val, sizeof(*val)); 993 } 994 995 if (linux_boot) { 996 x86_load_linux(x86ms, fw_cfg, PC_FW_DATA, pcmc->pvh_enabled); 997 } 998 999 for (i = 0; i < nb_option_roms; i++) { 1000 rom_add_option(option_rom[i].name, option_rom[i].bootindex); 1001 } 1002 x86ms->fw_cfg = fw_cfg; 1003 1004 /* Init default IOAPIC address space */ 1005 x86ms->ioapic_as = &address_space_memory; 1006 1007 /* Init ACPI memory hotplug IO base address */ 1008 pcms->memhp_io_base = ACPI_MEMORY_HOTPLUG_BASE; 1009 } 1010 1011 /* 1012 * The 64bit pci hole starts after "above 4G RAM" and 1013 * potentially the space reserved for memory hotplug. 1014 */ 1015 uint64_t pc_pci_hole64_start(void) 1016 { 1017 PCMachineState *pcms = PC_MACHINE(qdev_get_machine()); 1018 PCMachineClass *pcmc = PC_MACHINE_GET_CLASS(pcms); 1019 MachineState *ms = MACHINE(pcms); 1020 uint64_t hole64_start = 0; 1021 ram_addr_t size = 0; 1022 1023 if (pcms->cxl_devices_state.is_enabled) { 1024 hole64_start = pc_get_cxl_range_end(pcms); 1025 } else if (pcmc->has_reserved_memory && (ms->ram_size < ms->maxram_size)) { 1026 pc_get_device_memory_range(pcms, &hole64_start, &size); 1027 hole64_start += size; 1028 } else { 1029 hole64_start = pc_above_4g_end(pcms); 1030 } 1031 1032 return ROUND_UP(hole64_start, 1 * GiB); 1033 } 1034 1035 DeviceState *pc_vga_init(ISABus *isa_bus, PCIBus *pci_bus) 1036 { 1037 DeviceState *dev = NULL; 1038 1039 if (pci_bus) { 1040 PCIDevice *pcidev = pci_vga_init(pci_bus); 1041 dev = pcidev ? &pcidev->qdev : NULL; 1042 } else if (isa_bus) { 1043 ISADevice *isadev = isa_vga_init(isa_bus); 1044 dev = isadev ? DEVICE(isadev) : NULL; 1045 } 1046 1047 return dev; 1048 } 1049 1050 static const MemoryRegionOps ioport80_io_ops = { 1051 .write = ioport80_write, 1052 .read = ioport80_read, 1053 .endianness = DEVICE_LITTLE_ENDIAN, 1054 .impl = { 1055 .min_access_size = 1, 1056 .max_access_size = 1, 1057 }, 1058 }; 1059 1060 static const MemoryRegionOps ioportF0_io_ops = { 1061 .write = ioportF0_write, 1062 .read = ioportF0_read, 1063 .endianness = DEVICE_LITTLE_ENDIAN, 1064 .impl = { 1065 .min_access_size = 1, 1066 .max_access_size = 1, 1067 }, 1068 }; 1069 1070 static void pc_superio_init(ISABus *isa_bus, bool create_fdctrl, 1071 bool create_i8042, bool no_vmport, Error **errp) 1072 { 1073 int i; 1074 DriveInfo *fd[MAX_FD]; 1075 qemu_irq *a20_line; 1076 ISADevice *i8042, *port92, *vmmouse; 1077 1078 serial_hds_isa_init(isa_bus, 0, MAX_ISA_SERIAL_PORTS); 1079 parallel_hds_isa_init(isa_bus, MAX_PARALLEL_PORTS); 1080 1081 for (i = 0; i < MAX_FD; i++) { 1082 fd[i] = drive_get(IF_FLOPPY, 0, i); 1083 create_fdctrl |= !!fd[i]; 1084 } 1085 if (create_fdctrl) { 1086 #ifdef CONFIG_FDC_ISA 1087 ISADevice *fdc = isa_new(TYPE_ISA_FDC); 1088 if (fdc) { 1089 isa_realize_and_unref(fdc, isa_bus, &error_fatal); 1090 isa_fdc_init_drives(fdc, fd); 1091 } 1092 #endif 1093 } 1094 1095 if (!create_i8042) { 1096 if (!no_vmport) { 1097 error_setg(errp, 1098 "vmport requires the i8042 controller to be enabled"); 1099 } 1100 return; 1101 } 1102 1103 i8042 = isa_create_simple(isa_bus, TYPE_I8042); 1104 if (!no_vmport) { 1105 isa_create_simple(isa_bus, TYPE_VMPORT); 1106 vmmouse = isa_try_new("vmmouse"); 1107 } else { 1108 vmmouse = NULL; 1109 } 1110 if (vmmouse) { 1111 object_property_set_link(OBJECT(vmmouse), TYPE_I8042, OBJECT(i8042), 1112 &error_abort); 1113 isa_realize_and_unref(vmmouse, isa_bus, &error_fatal); 1114 } 1115 port92 = isa_create_simple(isa_bus, TYPE_PORT92); 1116 1117 a20_line = qemu_allocate_irqs(handle_a20_line_change, first_cpu, 2); 1118 qdev_connect_gpio_out_named(DEVICE(i8042), 1119 I8042_A20_LINE, 0, a20_line[0]); 1120 qdev_connect_gpio_out_named(DEVICE(port92), 1121 PORT92_A20_LINE, 0, a20_line[1]); 1122 g_free(a20_line); 1123 } 1124 1125 void pc_basic_device_init(struct PCMachineState *pcms, 1126 ISABus *isa_bus, qemu_irq *gsi, 1127 ISADevice *rtc_state, 1128 bool create_fdctrl, 1129 uint32_t hpet_irqs) 1130 { 1131 int i; 1132 DeviceState *hpet = NULL; 1133 int pit_isa_irq = 0; 1134 qemu_irq pit_alt_irq = NULL; 1135 ISADevice *pit = NULL; 1136 MemoryRegion *ioport80_io = g_new(MemoryRegion, 1); 1137 MemoryRegion *ioportF0_io = g_new(MemoryRegion, 1); 1138 X86MachineState *x86ms = X86_MACHINE(pcms); 1139 1140 memory_region_init_io(ioport80_io, NULL, &ioport80_io_ops, NULL, "ioport80", 1); 1141 memory_region_add_subregion(isa_bus->address_space_io, 0x80, ioport80_io); 1142 1143 memory_region_init_io(ioportF0_io, NULL, &ioportF0_io_ops, NULL, "ioportF0", 1); 1144 memory_region_add_subregion(isa_bus->address_space_io, 0xf0, ioportF0_io); 1145 1146 /* 1147 * Check if an HPET shall be created. 1148 */ 1149 if (pcms->hpet_enabled) { 1150 qemu_irq rtc_irq; 1151 1152 hpet = qdev_try_new(TYPE_HPET); 1153 if (!hpet) { 1154 error_report("couldn't create HPET device"); 1155 exit(1); 1156 } 1157 /* 1158 * For pc-piix-*, hpet's intcap is always IRQ2. For pc-q35-*, 1159 * use IRQ16~23, IRQ8 and IRQ2. If the user has already set 1160 * the property, use whatever mask they specified. 1161 */ 1162 uint8_t compat = object_property_get_uint(OBJECT(hpet), 1163 HPET_INTCAP, NULL); 1164 if (!compat) { 1165 qdev_prop_set_uint32(hpet, HPET_INTCAP, hpet_irqs); 1166 } 1167 sysbus_realize_and_unref(SYS_BUS_DEVICE(hpet), &error_fatal); 1168 sysbus_mmio_map(SYS_BUS_DEVICE(hpet), 0, HPET_BASE); 1169 1170 for (i = 0; i < IOAPIC_NUM_PINS; i++) { 1171 sysbus_connect_irq(SYS_BUS_DEVICE(hpet), i, gsi[i]); 1172 } 1173 pit_isa_irq = -1; 1174 pit_alt_irq = qdev_get_gpio_in(hpet, HPET_LEGACY_PIT_INT); 1175 rtc_irq = qdev_get_gpio_in(hpet, HPET_LEGACY_RTC_INT); 1176 1177 /* overwrite connection created by south bridge */ 1178 qdev_connect_gpio_out(DEVICE(rtc_state), 0, rtc_irq); 1179 } 1180 1181 object_property_add_alias(OBJECT(pcms), "rtc-time", OBJECT(rtc_state), 1182 "date"); 1183 1184 #ifdef CONFIG_XEN_EMU 1185 if (xen_mode == XEN_EMULATE) { 1186 xen_overlay_create(); 1187 xen_evtchn_create(IOAPIC_NUM_PINS, gsi); 1188 xen_gnttab_create(); 1189 xen_xenstore_create(); 1190 if (pcms->pcibus) { 1191 pci_create_simple(pcms->pcibus, -1, "xen-platform"); 1192 } 1193 xen_bus_init(); 1194 } 1195 #endif 1196 1197 qemu_register_boot_set(pc_boot_set, pcms); 1198 set_boot_dev(pcms, MC146818_RTC(rtc_state), 1199 MACHINE(pcms)->boot_config.order, &error_fatal); 1200 1201 if (!xen_enabled() && 1202 (x86ms->pit == ON_OFF_AUTO_AUTO || x86ms->pit == ON_OFF_AUTO_ON)) { 1203 if (kvm_pit_in_kernel()) { 1204 pit = kvm_pit_init(isa_bus, 0x40); 1205 } else { 1206 pit = i8254_pit_init(isa_bus, 0x40, pit_isa_irq, pit_alt_irq); 1207 } 1208 if (hpet) { 1209 /* connect PIT to output control line of the HPET */ 1210 qdev_connect_gpio_out(hpet, 0, qdev_get_gpio_in(DEVICE(pit), 0)); 1211 } 1212 object_property_set_link(OBJECT(pcms->pcspk), "pit", 1213 OBJECT(pit), &error_fatal); 1214 isa_realize_and_unref(pcms->pcspk, isa_bus, &error_fatal); 1215 } 1216 1217 if (pcms->vmport == ON_OFF_AUTO_AUTO) { 1218 pcms->vmport = (xen_enabled() || !pcms->i8042_enabled) 1219 ? ON_OFF_AUTO_OFF : ON_OFF_AUTO_ON; 1220 } 1221 1222 /* Super I/O */ 1223 pc_superio_init(isa_bus, create_fdctrl, pcms->i8042_enabled, 1224 pcms->vmport != ON_OFF_AUTO_ON, &error_fatal); 1225 1226 pcms->machine_done.notify = pc_machine_done; 1227 qemu_add_machine_init_done_notifier(&pcms->machine_done); 1228 } 1229 1230 void pc_nic_init(PCMachineClass *pcmc, ISABus *isa_bus, PCIBus *pci_bus) 1231 { 1232 MachineClass *mc = MACHINE_CLASS(pcmc); 1233 bool default_is_ne2k = g_str_equal(mc->default_nic, TYPE_ISA_NE2000); 1234 NICInfo *nd; 1235 1236 while ((nd = qemu_find_nic_info(TYPE_ISA_NE2000, default_is_ne2k, NULL))) { 1237 pc_init_ne2k_isa(isa_bus, nd, &error_fatal); 1238 } 1239 1240 /* Anything remaining should be a PCI NIC */ 1241 if (pci_bus) { 1242 pci_init_nic_devices(pci_bus, mc->default_nic); 1243 } 1244 } 1245 1246 void pc_i8259_create(ISABus *isa_bus, qemu_irq *i8259_irqs) 1247 { 1248 qemu_irq *i8259; 1249 1250 if (kvm_pic_in_kernel()) { 1251 i8259 = kvm_i8259_init(isa_bus); 1252 } else if (xen_enabled()) { 1253 i8259 = xen_interrupt_controller_init(); 1254 } else { 1255 i8259 = i8259_init(isa_bus, x86_allocate_cpu_irq()); 1256 } 1257 1258 for (size_t i = 0; i < ISA_NUM_IRQS; i++) { 1259 i8259_irqs[i] = i8259[i]; 1260 } 1261 1262 g_free(i8259); 1263 } 1264 1265 static void pc_memory_pre_plug(HotplugHandler *hotplug_dev, DeviceState *dev, 1266 Error **errp) 1267 { 1268 const X86MachineState *x86ms = X86_MACHINE(hotplug_dev); 1269 const MachineState *ms = MACHINE(hotplug_dev); 1270 const bool is_nvdimm = object_dynamic_cast(OBJECT(dev), TYPE_NVDIMM); 1271 Error *local_err = NULL; 1272 1273 /* 1274 * When "acpi=off" is used with the Q35 machine type, no ACPI is built, 1275 * but pcms->acpi_dev is still created. Check !acpi_enabled in 1276 * addition to cover this case. 1277 */ 1278 if (!x86ms->acpi_dev || !x86_machine_is_acpi_enabled(x86ms)) { 1279 error_setg(errp, 1280 "memory hotplug is not enabled: missing acpi device or acpi disabled"); 1281 return; 1282 } 1283 1284 if (is_nvdimm && !ms->nvdimms_state->is_enabled) { 1285 error_setg(errp, "nvdimm is not enabled: missing 'nvdimm' in '-M'"); 1286 return; 1287 } 1288 1289 hotplug_handler_pre_plug(x86ms->acpi_dev, dev, &local_err); 1290 if (local_err) { 1291 error_propagate(errp, local_err); 1292 return; 1293 } 1294 1295 pc_dimm_pre_plug(PC_DIMM(dev), MACHINE(hotplug_dev), errp); 1296 } 1297 1298 static void pc_memory_plug(HotplugHandler *hotplug_dev, 1299 DeviceState *dev, Error **errp) 1300 { 1301 PCMachineState *pcms = PC_MACHINE(hotplug_dev); 1302 X86MachineState *x86ms = X86_MACHINE(hotplug_dev); 1303 MachineState *ms = MACHINE(hotplug_dev); 1304 bool is_nvdimm = object_dynamic_cast(OBJECT(dev), TYPE_NVDIMM); 1305 1306 pc_dimm_plug(PC_DIMM(dev), MACHINE(pcms)); 1307 1308 if (is_nvdimm) { 1309 nvdimm_plug(ms->nvdimms_state); 1310 } 1311 1312 hotplug_handler_plug(x86ms->acpi_dev, dev, &error_abort); 1313 } 1314 1315 static void pc_memory_unplug_request(HotplugHandler *hotplug_dev, 1316 DeviceState *dev, Error **errp) 1317 { 1318 X86MachineState *x86ms = X86_MACHINE(hotplug_dev); 1319 1320 /* 1321 * When "acpi=off" is used with the Q35 machine type, no ACPI is built, 1322 * but pcms->acpi_dev is still created. Check !acpi_enabled in 1323 * addition to cover this case. 1324 */ 1325 if (!x86ms->acpi_dev || !x86_machine_is_acpi_enabled(x86ms)) { 1326 error_setg(errp, 1327 "memory hotplug is not enabled: missing acpi device or acpi disabled"); 1328 return; 1329 } 1330 1331 if (object_dynamic_cast(OBJECT(dev), TYPE_NVDIMM)) { 1332 error_setg(errp, "nvdimm device hot unplug is not supported yet."); 1333 return; 1334 } 1335 1336 hotplug_handler_unplug_request(x86ms->acpi_dev, dev, 1337 errp); 1338 } 1339 1340 static void pc_memory_unplug(HotplugHandler *hotplug_dev, 1341 DeviceState *dev, Error **errp) 1342 { 1343 PCMachineState *pcms = PC_MACHINE(hotplug_dev); 1344 X86MachineState *x86ms = X86_MACHINE(hotplug_dev); 1345 Error *local_err = NULL; 1346 1347 hotplug_handler_unplug(x86ms->acpi_dev, dev, &local_err); 1348 if (local_err) { 1349 goto out; 1350 } 1351 1352 pc_dimm_unplug(PC_DIMM(dev), MACHINE(pcms)); 1353 qdev_unrealize(dev); 1354 out: 1355 error_propagate(errp, local_err); 1356 } 1357 1358 static void pc_hv_balloon_pre_plug(HotplugHandler *hotplug_dev, 1359 DeviceState *dev, Error **errp) 1360 { 1361 /* The vmbus handler has no hotplug handler; we should never end up here. */ 1362 g_assert(!dev->hotplugged); 1363 memory_device_pre_plug(MEMORY_DEVICE(dev), MACHINE(hotplug_dev), errp); 1364 } 1365 1366 static void pc_hv_balloon_plug(HotplugHandler *hotplug_dev, 1367 DeviceState *dev, Error **errp) 1368 { 1369 memory_device_plug(MEMORY_DEVICE(dev), MACHINE(hotplug_dev)); 1370 } 1371 1372 static void pc_machine_device_pre_plug_cb(HotplugHandler *hotplug_dev, 1373 DeviceState *dev, Error **errp) 1374 { 1375 if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM)) { 1376 pc_memory_pre_plug(hotplug_dev, dev, errp); 1377 } else if (object_dynamic_cast(OBJECT(dev), TYPE_CPU)) { 1378 x86_cpu_pre_plug(hotplug_dev, dev, errp); 1379 } else if (object_dynamic_cast(OBJECT(dev), TYPE_VIRTIO_MD_PCI)) { 1380 virtio_md_pci_pre_plug(VIRTIO_MD_PCI(dev), MACHINE(hotplug_dev), errp); 1381 } else if (object_dynamic_cast(OBJECT(dev), TYPE_VIRTIO_IOMMU_PCI)) { 1382 /* Declare the APIC range as the reserved MSI region */ 1383 char *resv_prop_str = g_strdup_printf("0xfee00000:0xfeefffff:%d", 1384 VIRTIO_IOMMU_RESV_MEM_T_MSI); 1385 QList *reserved_regions = qlist_new(); 1386 1387 qlist_append_str(reserved_regions, resv_prop_str); 1388 qdev_prop_set_array(dev, "reserved-regions", reserved_regions); 1389 1390 g_free(resv_prop_str); 1391 } 1392 1393 if (object_dynamic_cast(OBJECT(dev), TYPE_X86_IOMMU_DEVICE) || 1394 object_dynamic_cast(OBJECT(dev), TYPE_VIRTIO_IOMMU_PCI)) { 1395 PCMachineState *pcms = PC_MACHINE(hotplug_dev); 1396 1397 if (pcms->iommu) { 1398 error_setg(errp, "QEMU does not support multiple vIOMMUs " 1399 "for x86 yet."); 1400 return; 1401 } 1402 pcms->iommu = dev; 1403 } else if (object_dynamic_cast(OBJECT(dev), TYPE_HV_BALLOON)) { 1404 pc_hv_balloon_pre_plug(hotplug_dev, dev, errp); 1405 } 1406 } 1407 1408 static void pc_machine_device_plug_cb(HotplugHandler *hotplug_dev, 1409 DeviceState *dev, Error **errp) 1410 { 1411 if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM)) { 1412 pc_memory_plug(hotplug_dev, dev, errp); 1413 } else if (object_dynamic_cast(OBJECT(dev), TYPE_CPU)) { 1414 x86_cpu_plug(hotplug_dev, dev, errp); 1415 } else if (object_dynamic_cast(OBJECT(dev), TYPE_VIRTIO_MD_PCI)) { 1416 virtio_md_pci_plug(VIRTIO_MD_PCI(dev), MACHINE(hotplug_dev), errp); 1417 } else if (object_dynamic_cast(OBJECT(dev), TYPE_HV_BALLOON)) { 1418 pc_hv_balloon_plug(hotplug_dev, dev, errp); 1419 } 1420 } 1421 1422 static void pc_machine_device_unplug_request_cb(HotplugHandler *hotplug_dev, 1423 DeviceState *dev, Error **errp) 1424 { 1425 if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM)) { 1426 pc_memory_unplug_request(hotplug_dev, dev, errp); 1427 } else if (object_dynamic_cast(OBJECT(dev), TYPE_CPU)) { 1428 x86_cpu_unplug_request_cb(hotplug_dev, dev, errp); 1429 } else if (object_dynamic_cast(OBJECT(dev), TYPE_VIRTIO_MD_PCI)) { 1430 virtio_md_pci_unplug_request(VIRTIO_MD_PCI(dev), MACHINE(hotplug_dev), 1431 errp); 1432 } else { 1433 error_setg(errp, "acpi: device unplug request for not supported device" 1434 " type: %s", object_get_typename(OBJECT(dev))); 1435 } 1436 } 1437 1438 static void pc_machine_device_unplug_cb(HotplugHandler *hotplug_dev, 1439 DeviceState *dev, Error **errp) 1440 { 1441 if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM)) { 1442 pc_memory_unplug(hotplug_dev, dev, errp); 1443 } else if (object_dynamic_cast(OBJECT(dev), TYPE_CPU)) { 1444 x86_cpu_unplug_cb(hotplug_dev, dev, errp); 1445 } else if (object_dynamic_cast(OBJECT(dev), TYPE_VIRTIO_MD_PCI)) { 1446 virtio_md_pci_unplug(VIRTIO_MD_PCI(dev), MACHINE(hotplug_dev), errp); 1447 } else { 1448 error_setg(errp, "acpi: device unplug for not supported device" 1449 " type: %s", object_get_typename(OBJECT(dev))); 1450 } 1451 } 1452 1453 static HotplugHandler *pc_get_hotplug_handler(MachineState *machine, 1454 DeviceState *dev) 1455 { 1456 if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM) || 1457 object_dynamic_cast(OBJECT(dev), TYPE_CPU) || 1458 object_dynamic_cast(OBJECT(dev), TYPE_VIRTIO_MD_PCI) || 1459 object_dynamic_cast(OBJECT(dev), TYPE_VIRTIO_IOMMU_PCI) || 1460 object_dynamic_cast(OBJECT(dev), TYPE_HV_BALLOON) || 1461 object_dynamic_cast(OBJECT(dev), TYPE_X86_IOMMU_DEVICE)) { 1462 return HOTPLUG_HANDLER(machine); 1463 } 1464 1465 return NULL; 1466 } 1467 1468 static void pc_machine_get_vmport(Object *obj, Visitor *v, const char *name, 1469 void *opaque, Error **errp) 1470 { 1471 PCMachineState *pcms = PC_MACHINE(obj); 1472 OnOffAuto vmport = pcms->vmport; 1473 1474 visit_type_OnOffAuto(v, name, &vmport, errp); 1475 } 1476 1477 static void pc_machine_set_vmport(Object *obj, Visitor *v, const char *name, 1478 void *opaque, Error **errp) 1479 { 1480 PCMachineState *pcms = PC_MACHINE(obj); 1481 1482 visit_type_OnOffAuto(v, name, &pcms->vmport, errp); 1483 } 1484 1485 static bool pc_machine_get_fd_bootchk(Object *obj, Error **errp) 1486 { 1487 PCMachineState *pcms = PC_MACHINE(obj); 1488 1489 return pcms->fd_bootchk; 1490 } 1491 1492 static void pc_machine_set_fd_bootchk(Object *obj, bool value, Error **errp) 1493 { 1494 PCMachineState *pcms = PC_MACHINE(obj); 1495 1496 pcms->fd_bootchk = value; 1497 } 1498 1499 static bool pc_machine_get_smbus(Object *obj, Error **errp) 1500 { 1501 PCMachineState *pcms = PC_MACHINE(obj); 1502 1503 return pcms->smbus_enabled; 1504 } 1505 1506 static void pc_machine_set_smbus(Object *obj, bool value, Error **errp) 1507 { 1508 PCMachineState *pcms = PC_MACHINE(obj); 1509 1510 pcms->smbus_enabled = value; 1511 } 1512 1513 static bool pc_machine_get_sata(Object *obj, Error **errp) 1514 { 1515 PCMachineState *pcms = PC_MACHINE(obj); 1516 1517 return pcms->sata_enabled; 1518 } 1519 1520 static void pc_machine_set_sata(Object *obj, bool value, Error **errp) 1521 { 1522 PCMachineState *pcms = PC_MACHINE(obj); 1523 1524 pcms->sata_enabled = value; 1525 } 1526 1527 static bool pc_machine_get_hpet(Object *obj, Error **errp) 1528 { 1529 PCMachineState *pcms = PC_MACHINE(obj); 1530 1531 return pcms->hpet_enabled; 1532 } 1533 1534 static void pc_machine_set_hpet(Object *obj, bool value, Error **errp) 1535 { 1536 PCMachineState *pcms = PC_MACHINE(obj); 1537 1538 pcms->hpet_enabled = value; 1539 } 1540 1541 static bool pc_machine_get_i8042(Object *obj, Error **errp) 1542 { 1543 PCMachineState *pcms = PC_MACHINE(obj); 1544 1545 return pcms->i8042_enabled; 1546 } 1547 1548 static void pc_machine_set_i8042(Object *obj, bool value, Error **errp) 1549 { 1550 PCMachineState *pcms = PC_MACHINE(obj); 1551 1552 pcms->i8042_enabled = value; 1553 } 1554 1555 static bool pc_machine_get_default_bus_bypass_iommu(Object *obj, Error **errp) 1556 { 1557 PCMachineState *pcms = PC_MACHINE(obj); 1558 1559 return pcms->default_bus_bypass_iommu; 1560 } 1561 1562 static void pc_machine_set_default_bus_bypass_iommu(Object *obj, bool value, 1563 Error **errp) 1564 { 1565 PCMachineState *pcms = PC_MACHINE(obj); 1566 1567 pcms->default_bus_bypass_iommu = value; 1568 } 1569 1570 static void pc_machine_get_smbios_ep(Object *obj, Visitor *v, const char *name, 1571 void *opaque, Error **errp) 1572 { 1573 PCMachineState *pcms = PC_MACHINE(obj); 1574 SmbiosEntryPointType smbios_entry_point_type = pcms->smbios_entry_point_type; 1575 1576 visit_type_SmbiosEntryPointType(v, name, &smbios_entry_point_type, errp); 1577 } 1578 1579 static void pc_machine_set_smbios_ep(Object *obj, Visitor *v, const char *name, 1580 void *opaque, Error **errp) 1581 { 1582 PCMachineState *pcms = PC_MACHINE(obj); 1583 1584 visit_type_SmbiosEntryPointType(v, name, &pcms->smbios_entry_point_type, errp); 1585 } 1586 1587 static void pc_machine_get_max_ram_below_4g(Object *obj, Visitor *v, 1588 const char *name, void *opaque, 1589 Error **errp) 1590 { 1591 PCMachineState *pcms = PC_MACHINE(obj); 1592 uint64_t value = pcms->max_ram_below_4g; 1593 1594 visit_type_size(v, name, &value, errp); 1595 } 1596 1597 static void pc_machine_set_max_ram_below_4g(Object *obj, Visitor *v, 1598 const char *name, void *opaque, 1599 Error **errp) 1600 { 1601 PCMachineState *pcms = PC_MACHINE(obj); 1602 uint64_t value; 1603 1604 if (!visit_type_size(v, name, &value, errp)) { 1605 return; 1606 } 1607 if (value > 4 * GiB) { 1608 error_setg(errp, 1609 "Machine option 'max-ram-below-4g=%"PRIu64 1610 "' expects size less than or equal to 4G", value); 1611 return; 1612 } 1613 1614 if (value < 1 * MiB) { 1615 warn_report("Only %" PRIu64 " bytes of RAM below the 4GiB boundary," 1616 "BIOS may not work with less than 1MiB", value); 1617 } 1618 1619 pcms->max_ram_below_4g = value; 1620 } 1621 1622 static void pc_machine_get_max_fw_size(Object *obj, Visitor *v, 1623 const char *name, void *opaque, 1624 Error **errp) 1625 { 1626 PCMachineState *pcms = PC_MACHINE(obj); 1627 uint64_t value = pcms->max_fw_size; 1628 1629 visit_type_size(v, name, &value, errp); 1630 } 1631 1632 static void pc_machine_set_max_fw_size(Object *obj, Visitor *v, 1633 const char *name, void *opaque, 1634 Error **errp) 1635 { 1636 PCMachineState *pcms = PC_MACHINE(obj); 1637 uint64_t value; 1638 1639 if (!visit_type_size(v, name, &value, errp)) { 1640 return; 1641 } 1642 1643 /* 1644 * We don't have a theoretically justifiable exact lower bound on the base 1645 * address of any flash mapping. In practice, the IO-APIC MMIO range is 1646 * [0xFEE00000..0xFEE01000] -- see IO_APIC_DEFAULT_ADDRESS --, leaving free 1647 * only 18MiB-4KiB below 4GiB. For now, restrict the cumulative mapping to 1648 * 16MiB in size. 1649 */ 1650 if (value > 16 * MiB) { 1651 error_setg(errp, 1652 "User specified max allowed firmware size %" PRIu64 " is " 1653 "greater than 16MiB. If combined firmware size exceeds " 1654 "16MiB the system may not boot, or experience intermittent" 1655 "stability issues.", 1656 value); 1657 return; 1658 } 1659 1660 pcms->max_fw_size = value; 1661 } 1662 1663 1664 static void pc_machine_initfn(Object *obj) 1665 { 1666 PCMachineState *pcms = PC_MACHINE(obj); 1667 PCMachineClass *pcmc = PC_MACHINE_GET_CLASS(pcms); 1668 1669 #ifdef CONFIG_VMPORT 1670 pcms->vmport = ON_OFF_AUTO_AUTO; 1671 #else 1672 pcms->vmport = ON_OFF_AUTO_OFF; 1673 #endif /* CONFIG_VMPORT */ 1674 pcms->max_ram_below_4g = 0; /* use default */ 1675 pcms->smbios_entry_point_type = pcmc->default_smbios_ep_type; 1676 pcms->south_bridge = pcmc->default_south_bridge; 1677 1678 /* acpi build is enabled by default if machine supports it */ 1679 pcms->acpi_build_enabled = pcmc->has_acpi_build; 1680 pcms->smbus_enabled = true; 1681 pcms->sata_enabled = true; 1682 pcms->i8042_enabled = true; 1683 pcms->max_fw_size = 8 * MiB; 1684 #if defined(CONFIG_HPET) 1685 pcms->hpet_enabled = true; 1686 #endif 1687 pcms->fd_bootchk = true; 1688 pcms->default_bus_bypass_iommu = false; 1689 1690 pc_system_flash_create(pcms); 1691 pcms->pcspk = isa_new(TYPE_PC_SPEAKER); 1692 object_property_add_alias(OBJECT(pcms), "pcspk-audiodev", 1693 OBJECT(pcms->pcspk), "audiodev"); 1694 if (pcmc->pci_enabled) { 1695 cxl_machine_init(obj, &pcms->cxl_devices_state); 1696 } 1697 } 1698 1699 static void pc_machine_reset(MachineState *machine, ResetType type) 1700 { 1701 CPUState *cs; 1702 X86CPU *cpu; 1703 1704 qemu_devices_reset(type); 1705 1706 /* Reset APIC after devices have been reset to cancel 1707 * any changes that qemu_devices_reset() might have done. 1708 */ 1709 CPU_FOREACH(cs) { 1710 cpu = X86_CPU(cs); 1711 1712 x86_cpu_after_reset(cpu); 1713 } 1714 } 1715 1716 static void pc_machine_wakeup(MachineState *machine) 1717 { 1718 cpu_synchronize_all_states(); 1719 pc_machine_reset(machine, RESET_TYPE_WAKEUP); 1720 cpu_synchronize_all_post_reset(); 1721 } 1722 1723 static bool pc_hotplug_allowed(MachineState *ms, DeviceState *dev, Error **errp) 1724 { 1725 X86IOMMUState *iommu = x86_iommu_get_default(); 1726 IntelIOMMUState *intel_iommu; 1727 1728 if (iommu && 1729 object_dynamic_cast((Object *)iommu, TYPE_INTEL_IOMMU_DEVICE) && 1730 object_dynamic_cast((Object *)dev, "vfio-pci")) { 1731 intel_iommu = INTEL_IOMMU_DEVICE(iommu); 1732 if (!intel_iommu->caching_mode) { 1733 error_setg(errp, "Device assignment is not allowed without " 1734 "enabling caching-mode=on for Intel IOMMU."); 1735 return false; 1736 } 1737 } 1738 1739 return true; 1740 } 1741 1742 static void pc_machine_class_init(ObjectClass *oc, const void *data) 1743 { 1744 MachineClass *mc = MACHINE_CLASS(oc); 1745 X86MachineClass *x86mc = X86_MACHINE_CLASS(oc); 1746 PCMachineClass *pcmc = PC_MACHINE_CLASS(oc); 1747 HotplugHandlerClass *hc = HOTPLUG_HANDLER_CLASS(oc); 1748 1749 pcmc->pci_enabled = true; 1750 pcmc->has_acpi_build = true; 1751 pcmc->smbios_defaults = true; 1752 pcmc->gigabyte_align = true; 1753 pcmc->has_reserved_memory = true; 1754 pcmc->enforce_amd_1tb_hole = true; 1755 pcmc->isa_bios_alias = true; 1756 pcmc->pvh_enabled = true; 1757 pcmc->kvmclock_create_always = true; 1758 x86mc->apic_xrupt_override = true; 1759 assert(!mc->get_hotplug_handler); 1760 mc->get_hotplug_handler = pc_get_hotplug_handler; 1761 mc->hotplug_allowed = pc_hotplug_allowed; 1762 mc->auto_enable_numa_with_memhp = true; 1763 mc->auto_enable_numa_with_memdev = true; 1764 mc->has_hotpluggable_cpus = true; 1765 mc->default_boot_order = "cad"; 1766 mc->block_default_type = IF_IDE; 1767 mc->max_cpus = 255; 1768 mc->reset = pc_machine_reset; 1769 mc->wakeup = pc_machine_wakeup; 1770 hc->pre_plug = pc_machine_device_pre_plug_cb; 1771 hc->plug = pc_machine_device_plug_cb; 1772 hc->unplug_request = pc_machine_device_unplug_request_cb; 1773 hc->unplug = pc_machine_device_unplug_cb; 1774 mc->default_cpu_type = TARGET_DEFAULT_CPU_TYPE; 1775 mc->nvdimm_supported = true; 1776 mc->smp_props.dies_supported = true; 1777 mc->smp_props.modules_supported = true; 1778 mc->smp_props.cache_supported[CACHE_LEVEL_AND_TYPE_L1D] = true; 1779 mc->smp_props.cache_supported[CACHE_LEVEL_AND_TYPE_L1I] = true; 1780 mc->smp_props.cache_supported[CACHE_LEVEL_AND_TYPE_L2] = true; 1781 mc->smp_props.cache_supported[CACHE_LEVEL_AND_TYPE_L3] = true; 1782 mc->default_ram_id = "pc.ram"; 1783 pcmc->default_smbios_ep_type = SMBIOS_ENTRY_POINT_TYPE_AUTO; 1784 1785 object_class_property_add(oc, PC_MACHINE_MAX_RAM_BELOW_4G, "size", 1786 pc_machine_get_max_ram_below_4g, pc_machine_set_max_ram_below_4g, 1787 NULL, NULL); 1788 object_class_property_set_description(oc, PC_MACHINE_MAX_RAM_BELOW_4G, 1789 "Maximum ram below the 4G boundary (32bit boundary)"); 1790 1791 object_class_property_add(oc, PC_MACHINE_VMPORT, "OnOffAuto", 1792 pc_machine_get_vmport, pc_machine_set_vmport, 1793 NULL, NULL); 1794 object_class_property_set_description(oc, PC_MACHINE_VMPORT, 1795 "Enable vmport (pc & q35)"); 1796 1797 object_class_property_add_bool(oc, PC_MACHINE_SMBUS, 1798 pc_machine_get_smbus, pc_machine_set_smbus); 1799 object_class_property_set_description(oc, PC_MACHINE_SMBUS, 1800 "Enable/disable system management bus"); 1801 1802 object_class_property_add_bool(oc, PC_MACHINE_SATA, 1803 pc_machine_get_sata, pc_machine_set_sata); 1804 object_class_property_set_description(oc, PC_MACHINE_SATA, 1805 "Enable/disable Serial ATA bus"); 1806 1807 object_class_property_add_bool(oc, "hpet", 1808 pc_machine_get_hpet, pc_machine_set_hpet); 1809 object_class_property_set_description(oc, "hpet", 1810 "Enable/disable high precision event timer emulation"); 1811 1812 object_class_property_add_bool(oc, PC_MACHINE_I8042, 1813 pc_machine_get_i8042, pc_machine_set_i8042); 1814 object_class_property_set_description(oc, PC_MACHINE_I8042, 1815 "Enable/disable Intel 8042 PS/2 controller emulation"); 1816 1817 object_class_property_add_bool(oc, "default-bus-bypass-iommu", 1818 pc_machine_get_default_bus_bypass_iommu, 1819 pc_machine_set_default_bus_bypass_iommu); 1820 1821 object_class_property_add(oc, PC_MACHINE_MAX_FW_SIZE, "size", 1822 pc_machine_get_max_fw_size, pc_machine_set_max_fw_size, 1823 NULL, NULL); 1824 object_class_property_set_description(oc, PC_MACHINE_MAX_FW_SIZE, 1825 "Maximum combined firmware size"); 1826 1827 object_class_property_add(oc, PC_MACHINE_SMBIOS_EP, "str", 1828 pc_machine_get_smbios_ep, pc_machine_set_smbios_ep, 1829 NULL, NULL); 1830 object_class_property_set_description(oc, PC_MACHINE_SMBIOS_EP, 1831 "SMBIOS Entry Point type [32, 64]"); 1832 1833 object_class_property_add_bool(oc, "fd-bootchk", 1834 pc_machine_get_fd_bootchk, 1835 pc_machine_set_fd_bootchk); 1836 } 1837 1838 static const TypeInfo pc_machine_info = { 1839 .name = TYPE_PC_MACHINE, 1840 .parent = TYPE_X86_MACHINE, 1841 .abstract = true, 1842 .instance_size = sizeof(PCMachineState), 1843 .instance_init = pc_machine_initfn, 1844 .class_size = sizeof(PCMachineClass), 1845 .class_init = pc_machine_class_init, 1846 .interfaces = (const InterfaceInfo[]) { 1847 { TYPE_HOTPLUG_HANDLER }, 1848 { } 1849 }, 1850 }; 1851 1852 static void pc_machine_register_types(void) 1853 { 1854 type_register_static(&pc_machine_info); 1855 } 1856 1857 type_init(pc_machine_register_types) 1858