1 /* 2 * QEMU PC System Emulator 3 * 4 * Copyright (c) 2003-2004 Fabrice Bellard 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a copy 7 * of this software and associated documentation files (the "Software"), to deal 8 * in the Software without restriction, including without limitation the rights 9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 10 * copies of the Software, and to permit persons to whom the Software is 11 * furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice shall be included in 14 * all copies or substantial portions of the Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN 22 * THE SOFTWARE. 23 */ 24 25 #include "qemu/osdep.h" 26 #include "qemu/units.h" 27 #include "hw/i386/x86.h" 28 #include "hw/i386/pc.h" 29 #include "hw/char/serial.h" 30 #include "hw/char/parallel.h" 31 #include "hw/i386/topology.h" 32 #include "hw/i386/fw_cfg.h" 33 #include "hw/i386/vmport.h" 34 #include "sysemu/cpus.h" 35 #include "hw/block/fdc.h" 36 #include "hw/ide.h" 37 #include "hw/pci/pci.h" 38 #include "hw/pci/pci_bus.h" 39 #include "hw/pci-bridge/pci_expander_bridge.h" 40 #include "hw/nvram/fw_cfg.h" 41 #include "hw/timer/hpet.h" 42 #include "hw/firmware/smbios.h" 43 #include "hw/loader.h" 44 #include "elf.h" 45 #include "migration/vmstate.h" 46 #include "multiboot.h" 47 #include "hw/rtc/mc146818rtc.h" 48 #include "hw/intc/i8259.h" 49 #include "hw/intc/ioapic.h" 50 #include "hw/timer/i8254.h" 51 #include "hw/input/i8042.h" 52 #include "hw/irq.h" 53 #include "hw/audio/pcspk.h" 54 #include "hw/pci/msi.h" 55 #include "hw/sysbus.h" 56 #include "sysemu/sysemu.h" 57 #include "sysemu/tcg.h" 58 #include "sysemu/numa.h" 59 #include "sysemu/kvm.h" 60 #include "sysemu/xen.h" 61 #include "sysemu/reset.h" 62 #include "sysemu/runstate.h" 63 #include "kvm/kvm_i386.h" 64 #include "hw/xen/xen.h" 65 #include "hw/xen/start_info.h" 66 #include "ui/qemu-spice.h" 67 #include "exec/memory.h" 68 #include "qemu/bitmap.h" 69 #include "qemu/config-file.h" 70 #include "qemu/error-report.h" 71 #include "qemu/option.h" 72 #include "qemu/cutils.h" 73 #include "hw/acpi/acpi.h" 74 #include "hw/acpi/cpu_hotplug.h" 75 #include "acpi-build.h" 76 #include "hw/mem/pc-dimm.h" 77 #include "hw/mem/nvdimm.h" 78 #include "hw/cxl/cxl.h" 79 #include "hw/cxl/cxl_host.h" 80 #include "qapi/error.h" 81 #include "qapi/qapi-visit-common.h" 82 #include "qapi/qapi-visit-machine.h" 83 #include "qapi/visitor.h" 84 #include "hw/core/cpu.h" 85 #include "hw/usb.h" 86 #include "hw/i386/intel_iommu.h" 87 #include "hw/net/ne2000-isa.h" 88 #include "standard-headers/asm-x86/bootparam.h" 89 #include "hw/virtio/virtio-iommu.h" 90 #include "hw/virtio/virtio-pmem-pci.h" 91 #include "hw/virtio/virtio-mem-pci.h" 92 #include "hw/mem/memory-device.h" 93 #include "sysemu/replay.h" 94 #include "target/i386/cpu.h" 95 #include "e820_memory_layout.h" 96 #include "fw_cfg.h" 97 #include "trace.h" 98 #include CONFIG_DEVICES 99 100 /* 101 * Helper for setting model-id for CPU models that changed model-id 102 * depending on QEMU versions up to QEMU 2.4. 103 */ 104 #define PC_CPU_MODEL_IDS(v) \ 105 { "qemu32-" TYPE_X86_CPU, "model-id", "QEMU Virtual CPU version " v, },\ 106 { "qemu64-" TYPE_X86_CPU, "model-id", "QEMU Virtual CPU version " v, },\ 107 { "athlon-" TYPE_X86_CPU, "model-id", "QEMU Virtual CPU version " v, }, 108 109 GlobalProperty pc_compat_7_2[] = { 110 { "ICH9-LPC", "noreboot", "true" }, 111 }; 112 const size_t pc_compat_7_2_len = G_N_ELEMENTS(pc_compat_7_2); 113 114 GlobalProperty pc_compat_7_1[] = {}; 115 const size_t pc_compat_7_1_len = G_N_ELEMENTS(pc_compat_7_1); 116 117 GlobalProperty pc_compat_7_0[] = {}; 118 const size_t pc_compat_7_0_len = G_N_ELEMENTS(pc_compat_7_0); 119 120 GlobalProperty pc_compat_6_2[] = { 121 { "virtio-mem", "unplugged-inaccessible", "off" }, 122 }; 123 const size_t pc_compat_6_2_len = G_N_ELEMENTS(pc_compat_6_2); 124 125 GlobalProperty pc_compat_6_1[] = { 126 { TYPE_X86_CPU, "hv-version-id-build", "0x1bbc" }, 127 { TYPE_X86_CPU, "hv-version-id-major", "0x0006" }, 128 { TYPE_X86_CPU, "hv-version-id-minor", "0x0001" }, 129 { "ICH9-LPC", "x-keep-pci-slot-hpc", "false" }, 130 }; 131 const size_t pc_compat_6_1_len = G_N_ELEMENTS(pc_compat_6_1); 132 133 GlobalProperty pc_compat_6_0[] = { 134 { "qemu64" "-" TYPE_X86_CPU, "family", "6" }, 135 { "qemu64" "-" TYPE_X86_CPU, "model", "6" }, 136 { "qemu64" "-" TYPE_X86_CPU, "stepping", "3" }, 137 { TYPE_X86_CPU, "x-vendor-cpuid-only", "off" }, 138 { "ICH9-LPC", ACPI_PM_PROP_ACPI_PCIHP_BRIDGE, "off" }, 139 { "ICH9-LPC", "x-keep-pci-slot-hpc", "true" }, 140 }; 141 const size_t pc_compat_6_0_len = G_N_ELEMENTS(pc_compat_6_0); 142 143 GlobalProperty pc_compat_5_2[] = { 144 { "ICH9-LPC", "x-smi-cpu-hotunplug", "off" }, 145 }; 146 const size_t pc_compat_5_2_len = G_N_ELEMENTS(pc_compat_5_2); 147 148 GlobalProperty pc_compat_5_1[] = { 149 { "ICH9-LPC", "x-smi-cpu-hotplug", "off" }, 150 { TYPE_X86_CPU, "kvm-msi-ext-dest-id", "off" }, 151 }; 152 const size_t pc_compat_5_1_len = G_N_ELEMENTS(pc_compat_5_1); 153 154 GlobalProperty pc_compat_5_0[] = { 155 }; 156 const size_t pc_compat_5_0_len = G_N_ELEMENTS(pc_compat_5_0); 157 158 GlobalProperty pc_compat_4_2[] = { 159 { "mch", "smbase-smram", "off" }, 160 }; 161 const size_t pc_compat_4_2_len = G_N_ELEMENTS(pc_compat_4_2); 162 163 GlobalProperty pc_compat_4_1[] = {}; 164 const size_t pc_compat_4_1_len = G_N_ELEMENTS(pc_compat_4_1); 165 166 GlobalProperty pc_compat_4_0[] = {}; 167 const size_t pc_compat_4_0_len = G_N_ELEMENTS(pc_compat_4_0); 168 169 GlobalProperty pc_compat_3_1[] = { 170 { "intel-iommu", "dma-drain", "off" }, 171 { "Opteron_G3" "-" TYPE_X86_CPU, "rdtscp", "off" }, 172 { "Opteron_G4" "-" TYPE_X86_CPU, "rdtscp", "off" }, 173 { "Opteron_G4" "-" TYPE_X86_CPU, "npt", "off" }, 174 { "Opteron_G4" "-" TYPE_X86_CPU, "nrip-save", "off" }, 175 { "Opteron_G5" "-" TYPE_X86_CPU, "rdtscp", "off" }, 176 { "Opteron_G5" "-" TYPE_X86_CPU, "npt", "off" }, 177 { "Opteron_G5" "-" TYPE_X86_CPU, "nrip-save", "off" }, 178 { "EPYC" "-" TYPE_X86_CPU, "npt", "off" }, 179 { "EPYC" "-" TYPE_X86_CPU, "nrip-save", "off" }, 180 { "EPYC-IBPB" "-" TYPE_X86_CPU, "npt", "off" }, 181 { "EPYC-IBPB" "-" TYPE_X86_CPU, "nrip-save", "off" }, 182 { "Skylake-Client" "-" TYPE_X86_CPU, "mpx", "on" }, 183 { "Skylake-Client-IBRS" "-" TYPE_X86_CPU, "mpx", "on" }, 184 { "Skylake-Server" "-" TYPE_X86_CPU, "mpx", "on" }, 185 { "Skylake-Server-IBRS" "-" TYPE_X86_CPU, "mpx", "on" }, 186 { "Cascadelake-Server" "-" TYPE_X86_CPU, "mpx", "on" }, 187 { "Icelake-Client" "-" TYPE_X86_CPU, "mpx", "on" }, 188 { "Icelake-Server" "-" TYPE_X86_CPU, "mpx", "on" }, 189 { "Cascadelake-Server" "-" TYPE_X86_CPU, "stepping", "5" }, 190 { TYPE_X86_CPU, "x-intel-pt-auto-level", "off" }, 191 }; 192 const size_t pc_compat_3_1_len = G_N_ELEMENTS(pc_compat_3_1); 193 194 GlobalProperty pc_compat_3_0[] = { 195 { TYPE_X86_CPU, "x-hv-synic-kvm-only", "on" }, 196 { "Skylake-Server" "-" TYPE_X86_CPU, "pku", "off" }, 197 { "Skylake-Server-IBRS" "-" TYPE_X86_CPU, "pku", "off" }, 198 }; 199 const size_t pc_compat_3_0_len = G_N_ELEMENTS(pc_compat_3_0); 200 201 GlobalProperty pc_compat_2_12[] = { 202 { TYPE_X86_CPU, "legacy-cache", "on" }, 203 { TYPE_X86_CPU, "topoext", "off" }, 204 { "EPYC-" TYPE_X86_CPU, "xlevel", "0x8000000a" }, 205 { "EPYC-IBPB-" TYPE_X86_CPU, "xlevel", "0x8000000a" }, 206 }; 207 const size_t pc_compat_2_12_len = G_N_ELEMENTS(pc_compat_2_12); 208 209 GlobalProperty pc_compat_2_11[] = { 210 { TYPE_X86_CPU, "x-migrate-smi-count", "off" }, 211 { "Skylake-Server" "-" TYPE_X86_CPU, "clflushopt", "off" }, 212 }; 213 const size_t pc_compat_2_11_len = G_N_ELEMENTS(pc_compat_2_11); 214 215 GlobalProperty pc_compat_2_10[] = { 216 { TYPE_X86_CPU, "x-hv-max-vps", "0x40" }, 217 { "i440FX-pcihost", "x-pci-hole64-fix", "off" }, 218 { "q35-pcihost", "x-pci-hole64-fix", "off" }, 219 }; 220 const size_t pc_compat_2_10_len = G_N_ELEMENTS(pc_compat_2_10); 221 222 GlobalProperty pc_compat_2_9[] = { 223 { "mch", "extended-tseg-mbytes", "0" }, 224 }; 225 const size_t pc_compat_2_9_len = G_N_ELEMENTS(pc_compat_2_9); 226 227 GlobalProperty pc_compat_2_8[] = { 228 { TYPE_X86_CPU, "tcg-cpuid", "off" }, 229 { "kvmclock", "x-mach-use-reliable-get-clock", "off" }, 230 { "ICH9-LPC", "x-smi-broadcast", "off" }, 231 { TYPE_X86_CPU, "vmware-cpuid-freq", "off" }, 232 { "Haswell-" TYPE_X86_CPU, "stepping", "1" }, 233 }; 234 const size_t pc_compat_2_8_len = G_N_ELEMENTS(pc_compat_2_8); 235 236 GlobalProperty pc_compat_2_7[] = { 237 { TYPE_X86_CPU, "l3-cache", "off" }, 238 { TYPE_X86_CPU, "full-cpuid-auto-level", "off" }, 239 { "Opteron_G3" "-" TYPE_X86_CPU, "family", "15" }, 240 { "Opteron_G3" "-" TYPE_X86_CPU, "model", "6" }, 241 { "Opteron_G3" "-" TYPE_X86_CPU, "stepping", "1" }, 242 { "isa-pcspk", "migrate", "off" }, 243 }; 244 const size_t pc_compat_2_7_len = G_N_ELEMENTS(pc_compat_2_7); 245 246 GlobalProperty pc_compat_2_6[] = { 247 { TYPE_X86_CPU, "cpuid-0xb", "off" }, 248 { "vmxnet3", "romfile", "" }, 249 { TYPE_X86_CPU, "fill-mtrr-mask", "off" }, 250 { "apic-common", "legacy-instance-id", "on", } 251 }; 252 const size_t pc_compat_2_6_len = G_N_ELEMENTS(pc_compat_2_6); 253 254 GlobalProperty pc_compat_2_5[] = {}; 255 const size_t pc_compat_2_5_len = G_N_ELEMENTS(pc_compat_2_5); 256 257 GlobalProperty pc_compat_2_4[] = { 258 PC_CPU_MODEL_IDS("2.4.0") 259 { "Haswell-" TYPE_X86_CPU, "abm", "off" }, 260 { "Haswell-noTSX-" TYPE_X86_CPU, "abm", "off" }, 261 { "Broadwell-" TYPE_X86_CPU, "abm", "off" }, 262 { "Broadwell-noTSX-" TYPE_X86_CPU, "abm", "off" }, 263 { "host" "-" TYPE_X86_CPU, "host-cache-info", "on" }, 264 { TYPE_X86_CPU, "check", "off" }, 265 { "qemu64" "-" TYPE_X86_CPU, "sse4a", "on" }, 266 { "qemu64" "-" TYPE_X86_CPU, "abm", "on" }, 267 { "qemu64" "-" TYPE_X86_CPU, "popcnt", "on" }, 268 { "qemu32" "-" TYPE_X86_CPU, "popcnt", "on" }, 269 { "Opteron_G2" "-" TYPE_X86_CPU, "rdtscp", "on" }, 270 { "Opteron_G3" "-" TYPE_X86_CPU, "rdtscp", "on" }, 271 { "Opteron_G4" "-" TYPE_X86_CPU, "rdtscp", "on" }, 272 { "Opteron_G5" "-" TYPE_X86_CPU, "rdtscp", "on", } 273 }; 274 const size_t pc_compat_2_4_len = G_N_ELEMENTS(pc_compat_2_4); 275 276 GlobalProperty pc_compat_2_3[] = { 277 PC_CPU_MODEL_IDS("2.3.0") 278 { TYPE_X86_CPU, "arat", "off" }, 279 { "qemu64" "-" TYPE_X86_CPU, "min-level", "4" }, 280 { "kvm64" "-" TYPE_X86_CPU, "min-level", "5" }, 281 { "pentium3" "-" TYPE_X86_CPU, "min-level", "2" }, 282 { "n270" "-" TYPE_X86_CPU, "min-level", "5" }, 283 { "Conroe" "-" TYPE_X86_CPU, "min-level", "4" }, 284 { "Penryn" "-" TYPE_X86_CPU, "min-level", "4" }, 285 { "Nehalem" "-" TYPE_X86_CPU, "min-level", "4" }, 286 { "n270" "-" TYPE_X86_CPU, "min-xlevel", "0x8000000a" }, 287 { "Penryn" "-" TYPE_X86_CPU, "min-xlevel", "0x8000000a" }, 288 { "Conroe" "-" TYPE_X86_CPU, "min-xlevel", "0x8000000a" }, 289 { "Nehalem" "-" TYPE_X86_CPU, "min-xlevel", "0x8000000a" }, 290 { "Westmere" "-" TYPE_X86_CPU, "min-xlevel", "0x8000000a" }, 291 { "SandyBridge" "-" TYPE_X86_CPU, "min-xlevel", "0x8000000a" }, 292 { "IvyBridge" "-" TYPE_X86_CPU, "min-xlevel", "0x8000000a" }, 293 { "Haswell" "-" TYPE_X86_CPU, "min-xlevel", "0x8000000a" }, 294 { "Haswell-noTSX" "-" TYPE_X86_CPU, "min-xlevel", "0x8000000a" }, 295 { "Broadwell" "-" TYPE_X86_CPU, "min-xlevel", "0x8000000a" }, 296 { "Broadwell-noTSX" "-" TYPE_X86_CPU, "min-xlevel", "0x8000000a" }, 297 { TYPE_X86_CPU, "kvm-no-smi-migration", "on" }, 298 }; 299 const size_t pc_compat_2_3_len = G_N_ELEMENTS(pc_compat_2_3); 300 301 GlobalProperty pc_compat_2_2[] = { 302 PC_CPU_MODEL_IDS("2.2.0") 303 { "kvm64" "-" TYPE_X86_CPU, "vme", "off" }, 304 { "kvm32" "-" TYPE_X86_CPU, "vme", "off" }, 305 { "Conroe" "-" TYPE_X86_CPU, "vme", "off" }, 306 { "Penryn" "-" TYPE_X86_CPU, "vme", "off" }, 307 { "Nehalem" "-" TYPE_X86_CPU, "vme", "off" }, 308 { "Westmere" "-" TYPE_X86_CPU, "vme", "off" }, 309 { "SandyBridge" "-" TYPE_X86_CPU, "vme", "off" }, 310 { "Haswell" "-" TYPE_X86_CPU, "vme", "off" }, 311 { "Broadwell" "-" TYPE_X86_CPU, "vme", "off" }, 312 { "Opteron_G1" "-" TYPE_X86_CPU, "vme", "off" }, 313 { "Opteron_G2" "-" TYPE_X86_CPU, "vme", "off" }, 314 { "Opteron_G3" "-" TYPE_X86_CPU, "vme", "off" }, 315 { "Opteron_G4" "-" TYPE_X86_CPU, "vme", "off" }, 316 { "Opteron_G5" "-" TYPE_X86_CPU, "vme", "off" }, 317 { "Haswell" "-" TYPE_X86_CPU, "f16c", "off" }, 318 { "Haswell" "-" TYPE_X86_CPU, "rdrand", "off" }, 319 { "Broadwell" "-" TYPE_X86_CPU, "f16c", "off" }, 320 { "Broadwell" "-" TYPE_X86_CPU, "rdrand", "off" }, 321 }; 322 const size_t pc_compat_2_2_len = G_N_ELEMENTS(pc_compat_2_2); 323 324 GlobalProperty pc_compat_2_1[] = { 325 PC_CPU_MODEL_IDS("2.1.0") 326 { "coreduo" "-" TYPE_X86_CPU, "vmx", "on" }, 327 { "core2duo" "-" TYPE_X86_CPU, "vmx", "on" }, 328 }; 329 const size_t pc_compat_2_1_len = G_N_ELEMENTS(pc_compat_2_1); 330 331 GlobalProperty pc_compat_2_0[] = { 332 PC_CPU_MODEL_IDS("2.0.0") 333 { "virtio-scsi-pci", "any_layout", "off" }, 334 { "PIIX4_PM", "memory-hotplug-support", "off" }, 335 { "apic", "version", "0x11" }, 336 { "nec-usb-xhci", "superspeed-ports-first", "off" }, 337 { "nec-usb-xhci", "force-pcie-endcap", "on" }, 338 { "pci-serial", "prog_if", "0" }, 339 { "pci-serial-2x", "prog_if", "0" }, 340 { "pci-serial-4x", "prog_if", "0" }, 341 { "virtio-net-pci", "guest_announce", "off" }, 342 { "ICH9-LPC", "memory-hotplug-support", "off" }, 343 }; 344 const size_t pc_compat_2_0_len = G_N_ELEMENTS(pc_compat_2_0); 345 346 GlobalProperty pc_compat_1_7[] = { 347 PC_CPU_MODEL_IDS("1.7.0") 348 { TYPE_USB_DEVICE, "msos-desc", "no" }, 349 { "PIIX4_PM", ACPI_PM_PROP_ACPI_PCIHP_BRIDGE, "off" }, 350 { "hpet", HPET_INTCAP, "4" }, 351 }; 352 const size_t pc_compat_1_7_len = G_N_ELEMENTS(pc_compat_1_7); 353 354 GlobalProperty pc_compat_1_6[] = { 355 PC_CPU_MODEL_IDS("1.6.0") 356 { "e1000", "mitigation", "off" }, 357 { "qemu64-" TYPE_X86_CPU, "model", "2" }, 358 { "qemu32-" TYPE_X86_CPU, "model", "3" }, 359 { "i440FX-pcihost", "short_root_bus", "1" }, 360 { "q35-pcihost", "short_root_bus", "1" }, 361 }; 362 const size_t pc_compat_1_6_len = G_N_ELEMENTS(pc_compat_1_6); 363 364 GlobalProperty pc_compat_1_5[] = { 365 PC_CPU_MODEL_IDS("1.5.0") 366 { "Conroe-" TYPE_X86_CPU, "model", "2" }, 367 { "Conroe-" TYPE_X86_CPU, "min-level", "2" }, 368 { "Penryn-" TYPE_X86_CPU, "model", "2" }, 369 { "Penryn-" TYPE_X86_CPU, "min-level", "2" }, 370 { "Nehalem-" TYPE_X86_CPU, "model", "2" }, 371 { "Nehalem-" TYPE_X86_CPU, "min-level", "2" }, 372 { "virtio-net-pci", "any_layout", "off" }, 373 { TYPE_X86_CPU, "pmu", "on" }, 374 { "i440FX-pcihost", "short_root_bus", "0" }, 375 { "q35-pcihost", "short_root_bus", "0" }, 376 }; 377 const size_t pc_compat_1_5_len = G_N_ELEMENTS(pc_compat_1_5); 378 379 GlobalProperty pc_compat_1_4[] = { 380 PC_CPU_MODEL_IDS("1.4.0") 381 { "scsi-hd", "discard_granularity", "0" }, 382 { "scsi-cd", "discard_granularity", "0" }, 383 { "ide-hd", "discard_granularity", "0" }, 384 { "ide-cd", "discard_granularity", "0" }, 385 { "virtio-blk-pci", "discard_granularity", "0" }, 386 /* DEV_NVECTORS_UNSPECIFIED as a uint32_t string: */ 387 { "virtio-serial-pci", "vectors", "0xFFFFFFFF" }, 388 { "virtio-net-pci", "ctrl_guest_offloads", "off" }, 389 { "e1000", "romfile", "pxe-e1000.rom" }, 390 { "ne2k_pci", "romfile", "pxe-ne2k_pci.rom" }, 391 { "pcnet", "romfile", "pxe-pcnet.rom" }, 392 { "rtl8139", "romfile", "pxe-rtl8139.rom" }, 393 { "virtio-net-pci", "romfile", "pxe-virtio.rom" }, 394 { "486-" TYPE_X86_CPU, "model", "0" }, 395 { "n270" "-" TYPE_X86_CPU, "movbe", "off" }, 396 { "Westmere" "-" TYPE_X86_CPU, "pclmulqdq", "off" }, 397 }; 398 const size_t pc_compat_1_4_len = G_N_ELEMENTS(pc_compat_1_4); 399 400 GSIState *pc_gsi_create(qemu_irq **irqs, bool pci_enabled) 401 { 402 GSIState *s; 403 404 s = g_new0(GSIState, 1); 405 if (kvm_ioapic_in_kernel()) { 406 kvm_pc_setup_irq_routing(pci_enabled); 407 } 408 *irqs = qemu_allocate_irqs(gsi_handler, s, IOAPIC_NUM_PINS); 409 410 return s; 411 } 412 413 static void ioport80_write(void *opaque, hwaddr addr, uint64_t data, 414 unsigned size) 415 { 416 } 417 418 static uint64_t ioport80_read(void *opaque, hwaddr addr, unsigned size) 419 { 420 return 0xffffffffffffffffULL; 421 } 422 423 /* MSDOS compatibility mode FPU exception support */ 424 static void ioportF0_write(void *opaque, hwaddr addr, uint64_t data, 425 unsigned size) 426 { 427 if (tcg_enabled()) { 428 cpu_set_ignne(); 429 } 430 } 431 432 static uint64_t ioportF0_read(void *opaque, hwaddr addr, unsigned size) 433 { 434 return 0xffffffffffffffffULL; 435 } 436 437 /* PC cmos mappings */ 438 439 #define REG_EQUIPMENT_BYTE 0x14 440 441 static void cmos_init_hd(MC146818RtcState *s, int type_ofs, int info_ofs, 442 int16_t cylinders, int8_t heads, int8_t sectors) 443 { 444 mc146818rtc_set_cmos_data(s, type_ofs, 47); 445 mc146818rtc_set_cmos_data(s, info_ofs, cylinders); 446 mc146818rtc_set_cmos_data(s, info_ofs + 1, cylinders >> 8); 447 mc146818rtc_set_cmos_data(s, info_ofs + 2, heads); 448 mc146818rtc_set_cmos_data(s, info_ofs + 3, 0xff); 449 mc146818rtc_set_cmos_data(s, info_ofs + 4, 0xff); 450 mc146818rtc_set_cmos_data(s, info_ofs + 5, 0xc0 | ((heads > 8) << 3)); 451 mc146818rtc_set_cmos_data(s, info_ofs + 6, cylinders); 452 mc146818rtc_set_cmos_data(s, info_ofs + 7, cylinders >> 8); 453 mc146818rtc_set_cmos_data(s, info_ofs + 8, sectors); 454 } 455 456 /* convert boot_device letter to something recognizable by the bios */ 457 static int boot_device2nibble(char boot_device) 458 { 459 switch(boot_device) { 460 case 'a': 461 case 'b': 462 return 0x01; /* floppy boot */ 463 case 'c': 464 return 0x02; /* hard drive boot */ 465 case 'd': 466 return 0x03; /* CD-ROM boot */ 467 case 'n': 468 return 0x04; /* Network boot */ 469 } 470 return 0; 471 } 472 473 static void set_boot_dev(MC146818RtcState *s, const char *boot_device, 474 Error **errp) 475 { 476 #define PC_MAX_BOOT_DEVICES 3 477 int nbds, bds[3] = { 0, }; 478 int i; 479 480 nbds = strlen(boot_device); 481 if (nbds > PC_MAX_BOOT_DEVICES) { 482 error_setg(errp, "Too many boot devices for PC"); 483 return; 484 } 485 for (i = 0; i < nbds; i++) { 486 bds[i] = boot_device2nibble(boot_device[i]); 487 if (bds[i] == 0) { 488 error_setg(errp, "Invalid boot device for PC: '%c'", 489 boot_device[i]); 490 return; 491 } 492 } 493 mc146818rtc_set_cmos_data(s, 0x3d, (bds[1] << 4) | bds[0]); 494 mc146818rtc_set_cmos_data(s, 0x38, (bds[2] << 4) | (fd_bootchk ? 0x0 : 0x1)); 495 } 496 497 static void pc_boot_set(void *opaque, const char *boot_device, Error **errp) 498 { 499 set_boot_dev(opaque, boot_device, errp); 500 } 501 502 static void pc_cmos_init_floppy(MC146818RtcState *rtc_state, ISADevice *floppy) 503 { 504 int val, nb, i; 505 FloppyDriveType fd_type[2] = { FLOPPY_DRIVE_TYPE_NONE, 506 FLOPPY_DRIVE_TYPE_NONE }; 507 508 /* floppy type */ 509 if (floppy) { 510 for (i = 0; i < 2; i++) { 511 fd_type[i] = isa_fdc_get_drive_type(floppy, i); 512 } 513 } 514 val = (cmos_get_fd_drive_type(fd_type[0]) << 4) | 515 cmos_get_fd_drive_type(fd_type[1]); 516 mc146818rtc_set_cmos_data(rtc_state, 0x10, val); 517 518 val = mc146818rtc_get_cmos_data(rtc_state, REG_EQUIPMENT_BYTE); 519 nb = 0; 520 if (fd_type[0] != FLOPPY_DRIVE_TYPE_NONE) { 521 nb++; 522 } 523 if (fd_type[1] != FLOPPY_DRIVE_TYPE_NONE) { 524 nb++; 525 } 526 switch (nb) { 527 case 0: 528 break; 529 case 1: 530 val |= 0x01; /* 1 drive, ready for boot */ 531 break; 532 case 2: 533 val |= 0x41; /* 2 drives, ready for boot */ 534 break; 535 } 536 mc146818rtc_set_cmos_data(rtc_state, REG_EQUIPMENT_BYTE, val); 537 } 538 539 typedef struct pc_cmos_init_late_arg { 540 MC146818RtcState *rtc_state; 541 BusState *idebus[2]; 542 } pc_cmos_init_late_arg; 543 544 typedef struct check_fdc_state { 545 ISADevice *floppy; 546 bool multiple; 547 } CheckFdcState; 548 549 static int check_fdc(Object *obj, void *opaque) 550 { 551 CheckFdcState *state = opaque; 552 Object *fdc; 553 uint32_t iobase; 554 Error *local_err = NULL; 555 556 fdc = object_dynamic_cast(obj, TYPE_ISA_FDC); 557 if (!fdc) { 558 return 0; 559 } 560 561 iobase = object_property_get_uint(obj, "iobase", &local_err); 562 if (local_err || iobase != 0x3f0) { 563 error_free(local_err); 564 return 0; 565 } 566 567 if (state->floppy) { 568 state->multiple = true; 569 } else { 570 state->floppy = ISA_DEVICE(obj); 571 } 572 return 0; 573 } 574 575 static const char * const fdc_container_path[] = { 576 "/unattached", "/peripheral", "/peripheral-anon" 577 }; 578 579 /* 580 * Locate the FDC at IO address 0x3f0, in order to configure the CMOS registers 581 * and ACPI objects. 582 */ 583 static ISADevice *pc_find_fdc0(void) 584 { 585 int i; 586 Object *container; 587 CheckFdcState state = { 0 }; 588 589 for (i = 0; i < ARRAY_SIZE(fdc_container_path); i++) { 590 container = container_get(qdev_get_machine(), fdc_container_path[i]); 591 object_child_foreach(container, check_fdc, &state); 592 } 593 594 if (state.multiple) { 595 warn_report("multiple floppy disk controllers with " 596 "iobase=0x3f0 have been found"); 597 error_printf("the one being picked for CMOS setup might not reflect " 598 "your intent"); 599 } 600 601 return state.floppy; 602 } 603 604 static void pc_cmos_init_late(void *opaque) 605 { 606 pc_cmos_init_late_arg *arg = opaque; 607 MC146818RtcState *s = arg->rtc_state; 608 int16_t cylinders; 609 int8_t heads, sectors; 610 int val; 611 int i, trans; 612 613 val = 0; 614 if (arg->idebus[0] && ide_get_geometry(arg->idebus[0], 0, 615 &cylinders, &heads, §ors) >= 0) { 616 cmos_init_hd(s, 0x19, 0x1b, cylinders, heads, sectors); 617 val |= 0xf0; 618 } 619 if (arg->idebus[0] && ide_get_geometry(arg->idebus[0], 1, 620 &cylinders, &heads, §ors) >= 0) { 621 cmos_init_hd(s, 0x1a, 0x24, cylinders, heads, sectors); 622 val |= 0x0f; 623 } 624 mc146818rtc_set_cmos_data(s, 0x12, val); 625 626 val = 0; 627 for (i = 0; i < 4; i++) { 628 /* NOTE: ide_get_geometry() returns the physical 629 geometry. It is always such that: 1 <= sects <= 63, 1 630 <= heads <= 16, 1 <= cylinders <= 16383. The BIOS 631 geometry can be different if a translation is done. */ 632 if (arg->idebus[i / 2] && 633 ide_get_geometry(arg->idebus[i / 2], i % 2, 634 &cylinders, &heads, §ors) >= 0) { 635 trans = ide_get_bios_chs_trans(arg->idebus[i / 2], i % 2) - 1; 636 assert((trans & ~3) == 0); 637 val |= trans << (i * 2); 638 } 639 } 640 mc146818rtc_set_cmos_data(s, 0x39, val); 641 642 pc_cmos_init_floppy(s, pc_find_fdc0()); 643 644 qemu_unregister_reset(pc_cmos_init_late, opaque); 645 } 646 647 void pc_cmos_init(PCMachineState *pcms, 648 BusState *idebus0, BusState *idebus1, 649 ISADevice *rtc) 650 { 651 int val; 652 static pc_cmos_init_late_arg arg; 653 X86MachineState *x86ms = X86_MACHINE(pcms); 654 MC146818RtcState *s = MC146818_RTC(rtc); 655 656 /* various important CMOS locations needed by PC/Bochs bios */ 657 658 /* memory size */ 659 /* base memory (first MiB) */ 660 val = MIN(x86ms->below_4g_mem_size / KiB, 640); 661 mc146818rtc_set_cmos_data(s, 0x15, val); 662 mc146818rtc_set_cmos_data(s, 0x16, val >> 8); 663 /* extended memory (next 64MiB) */ 664 if (x86ms->below_4g_mem_size > 1 * MiB) { 665 val = (x86ms->below_4g_mem_size - 1 * MiB) / KiB; 666 } else { 667 val = 0; 668 } 669 if (val > 65535) 670 val = 65535; 671 mc146818rtc_set_cmos_data(s, 0x17, val); 672 mc146818rtc_set_cmos_data(s, 0x18, val >> 8); 673 mc146818rtc_set_cmos_data(s, 0x30, val); 674 mc146818rtc_set_cmos_data(s, 0x31, val >> 8); 675 /* memory between 16MiB and 4GiB */ 676 if (x86ms->below_4g_mem_size > 16 * MiB) { 677 val = (x86ms->below_4g_mem_size - 16 * MiB) / (64 * KiB); 678 } else { 679 val = 0; 680 } 681 if (val > 65535) 682 val = 65535; 683 mc146818rtc_set_cmos_data(s, 0x34, val); 684 mc146818rtc_set_cmos_data(s, 0x35, val >> 8); 685 /* memory above 4GiB */ 686 val = x86ms->above_4g_mem_size / 65536; 687 mc146818rtc_set_cmos_data(s, 0x5b, val); 688 mc146818rtc_set_cmos_data(s, 0x5c, val >> 8); 689 mc146818rtc_set_cmos_data(s, 0x5d, val >> 16); 690 691 object_property_add_link(OBJECT(pcms), "rtc_state", 692 TYPE_ISA_DEVICE, 693 (Object **)&x86ms->rtc, 694 object_property_allow_set_link, 695 OBJ_PROP_LINK_STRONG); 696 object_property_set_link(OBJECT(pcms), "rtc_state", OBJECT(s), 697 &error_abort); 698 699 set_boot_dev(s, MACHINE(pcms)->boot_config.order, &error_fatal); 700 701 val = 0; 702 val |= 0x02; /* FPU is there */ 703 val |= 0x04; /* PS/2 mouse installed */ 704 mc146818rtc_set_cmos_data(s, REG_EQUIPMENT_BYTE, val); 705 706 /* hard drives and FDC */ 707 arg.rtc_state = s; 708 arg.idebus[0] = idebus0; 709 arg.idebus[1] = idebus1; 710 qemu_register_reset(pc_cmos_init_late, &arg); 711 } 712 713 static void handle_a20_line_change(void *opaque, int irq, int level) 714 { 715 X86CPU *cpu = opaque; 716 717 /* XXX: send to all CPUs ? */ 718 /* XXX: add logic to handle multiple A20 line sources */ 719 x86_cpu_set_a20(cpu, level); 720 } 721 722 #define NE2000_NB_MAX 6 723 724 static const int ne2000_io[NE2000_NB_MAX] = { 0x300, 0x320, 0x340, 0x360, 725 0x280, 0x380 }; 726 static const int ne2000_irq[NE2000_NB_MAX] = { 9, 10, 11, 3, 4, 5 }; 727 728 static void pc_init_ne2k_isa(ISABus *bus, NICInfo *nd) 729 { 730 static int nb_ne2k = 0; 731 732 if (nb_ne2k == NE2000_NB_MAX) 733 return; 734 isa_ne2000_init(bus, ne2000_io[nb_ne2k], 735 ne2000_irq[nb_ne2k], nd); 736 nb_ne2k++; 737 } 738 739 void pc_acpi_smi_interrupt(void *opaque, int irq, int level) 740 { 741 X86CPU *cpu = opaque; 742 743 if (level) { 744 cpu_interrupt(CPU(cpu), CPU_INTERRUPT_SMI); 745 } 746 } 747 748 static 749 void pc_machine_done(Notifier *notifier, void *data) 750 { 751 PCMachineState *pcms = container_of(notifier, 752 PCMachineState, machine_done); 753 X86MachineState *x86ms = X86_MACHINE(pcms); 754 755 cxl_hook_up_pxb_registers(pcms->bus, &pcms->cxl_devices_state, 756 &error_fatal); 757 758 if (pcms->cxl_devices_state.is_enabled) { 759 cxl_fmws_link_targets(&pcms->cxl_devices_state, &error_fatal); 760 } 761 762 /* set the number of CPUs */ 763 x86_rtc_set_cpus_count(x86ms->rtc, x86ms->boot_cpus); 764 765 fw_cfg_add_extra_pci_roots(pcms->bus, x86ms->fw_cfg); 766 767 acpi_setup(); 768 if (x86ms->fw_cfg) { 769 fw_cfg_build_smbios(MACHINE(pcms), x86ms->fw_cfg); 770 fw_cfg_build_feature_control(MACHINE(pcms), x86ms->fw_cfg); 771 /* update FW_CFG_NB_CPUS to account for -device added CPUs */ 772 fw_cfg_modify_i16(x86ms->fw_cfg, FW_CFG_NB_CPUS, x86ms->boot_cpus); 773 } 774 } 775 776 void pc_guest_info_init(PCMachineState *pcms) 777 { 778 X86MachineState *x86ms = X86_MACHINE(pcms); 779 780 x86ms->apic_xrupt_override = true; 781 pcms->machine_done.notify = pc_machine_done; 782 qemu_add_machine_init_done_notifier(&pcms->machine_done); 783 } 784 785 /* setup pci memory address space mapping into system address space */ 786 void pc_pci_as_mapping_init(MemoryRegion *system_memory, 787 MemoryRegion *pci_address_space) 788 { 789 /* Set to lower priority than RAM */ 790 memory_region_add_subregion_overlap(system_memory, 0x0, 791 pci_address_space, -1); 792 } 793 794 void xen_load_linux(PCMachineState *pcms) 795 { 796 int i; 797 FWCfgState *fw_cfg; 798 PCMachineClass *pcmc = PC_MACHINE_GET_CLASS(pcms); 799 X86MachineState *x86ms = X86_MACHINE(pcms); 800 801 assert(MACHINE(pcms)->kernel_filename != NULL); 802 803 fw_cfg = fw_cfg_init_io(FW_CFG_IO_BASE); 804 fw_cfg_add_i16(fw_cfg, FW_CFG_NB_CPUS, x86ms->boot_cpus); 805 rom_set_fw(fw_cfg); 806 807 x86_load_linux(x86ms, fw_cfg, pcmc->acpi_data_size, 808 pcmc->pvh_enabled, pcmc->legacy_no_rng_seed); 809 for (i = 0; i < nb_option_roms; i++) { 810 assert(!strcmp(option_rom[i].name, "linuxboot.bin") || 811 !strcmp(option_rom[i].name, "linuxboot_dma.bin") || 812 !strcmp(option_rom[i].name, "pvh.bin") || 813 !strcmp(option_rom[i].name, "multiboot.bin") || 814 !strcmp(option_rom[i].name, "multiboot_dma.bin")); 815 rom_add_option(option_rom[i].name, option_rom[i].bootindex); 816 } 817 x86ms->fw_cfg = fw_cfg; 818 } 819 820 #define PC_ROM_MIN_VGA 0xc0000 821 #define PC_ROM_MIN_OPTION 0xc8000 822 #define PC_ROM_MAX 0xe0000 823 #define PC_ROM_ALIGN 0x800 824 #define PC_ROM_SIZE (PC_ROM_MAX - PC_ROM_MIN_VGA) 825 826 static hwaddr pc_above_4g_end(PCMachineState *pcms) 827 { 828 X86MachineState *x86ms = X86_MACHINE(pcms); 829 830 if (pcms->sgx_epc.size != 0) { 831 return sgx_epc_above_4g_end(&pcms->sgx_epc); 832 } 833 834 return x86ms->above_4g_mem_start + x86ms->above_4g_mem_size; 835 } 836 837 static void pc_get_device_memory_range(PCMachineState *pcms, 838 hwaddr *base, 839 ram_addr_t *device_mem_size) 840 { 841 PCMachineClass *pcmc = PC_MACHINE_GET_CLASS(pcms); 842 MachineState *machine = MACHINE(pcms); 843 ram_addr_t size; 844 hwaddr addr; 845 846 size = machine->maxram_size - machine->ram_size; 847 addr = ROUND_UP(pc_above_4g_end(pcms), 1 * GiB); 848 849 if (pcmc->enforce_aligned_dimm) { 850 /* size device region assuming 1G page max alignment per slot */ 851 size += (1 * GiB) * machine->ram_slots; 852 } 853 854 *base = addr; 855 *device_mem_size = size; 856 } 857 858 static uint64_t pc_get_cxl_range_start(PCMachineState *pcms) 859 { 860 PCMachineClass *pcmc = PC_MACHINE_GET_CLASS(pcms); 861 hwaddr cxl_base; 862 ram_addr_t size; 863 864 if (pcmc->has_reserved_memory) { 865 pc_get_device_memory_range(pcms, &cxl_base, &size); 866 cxl_base += size; 867 } else { 868 cxl_base = pc_above_4g_end(pcms); 869 } 870 871 return cxl_base; 872 } 873 874 static uint64_t pc_get_cxl_range_end(PCMachineState *pcms) 875 { 876 uint64_t start = pc_get_cxl_range_start(pcms) + MiB; 877 878 if (pcms->cxl_devices_state.fixed_windows) { 879 GList *it; 880 881 start = ROUND_UP(start, 256 * MiB); 882 for (it = pcms->cxl_devices_state.fixed_windows; it; it = it->next) { 883 CXLFixedWindow *fw = it->data; 884 start += fw->size; 885 } 886 } 887 888 return start; 889 } 890 891 static hwaddr pc_max_used_gpa(PCMachineState *pcms, uint64_t pci_hole64_size) 892 { 893 X86CPU *cpu = X86_CPU(first_cpu); 894 895 /* 32-bit systems don't have hole64 thus return max CPU address */ 896 if (cpu->phys_bits <= 32) { 897 return ((hwaddr)1 << cpu->phys_bits) - 1; 898 } 899 900 return pc_pci_hole64_start() + pci_hole64_size - 1; 901 } 902 903 /* 904 * AMD systems with an IOMMU have an additional hole close to the 905 * 1Tb, which are special GPAs that cannot be DMA mapped. Depending 906 * on kernel version, VFIO may or may not let you DMA map those ranges. 907 * Starting Linux v5.4 we validate it, and can't create guests on AMD machines 908 * with certain memory sizes. It's also wrong to use those IOVA ranges 909 * in detriment of leading to IOMMU INVALID_DEVICE_REQUEST or worse. 910 * The ranges reserved for Hyper-Transport are: 911 * 912 * FD_0000_0000h - FF_FFFF_FFFFh 913 * 914 * The ranges represent the following: 915 * 916 * Base Address Top Address Use 917 * 918 * FD_0000_0000h FD_F7FF_FFFFh Reserved interrupt address space 919 * FD_F800_0000h FD_F8FF_FFFFh Interrupt/EOI IntCtl 920 * FD_F900_0000h FD_F90F_FFFFh Legacy PIC IACK 921 * FD_F910_0000h FD_F91F_FFFFh System Management 922 * FD_F920_0000h FD_FAFF_FFFFh Reserved Page Tables 923 * FD_FB00_0000h FD_FBFF_FFFFh Address Translation 924 * FD_FC00_0000h FD_FDFF_FFFFh I/O Space 925 * FD_FE00_0000h FD_FFFF_FFFFh Configuration 926 * FE_0000_0000h FE_1FFF_FFFFh Extended Configuration/Device Messages 927 * FE_2000_0000h FF_FFFF_FFFFh Reserved 928 * 929 * See AMD IOMMU spec, section 2.1.2 "IOMMU Logical Topology", 930 * Table 3: Special Address Controls (GPA) for more information. 931 */ 932 #define AMD_HT_START 0xfd00000000UL 933 #define AMD_HT_END 0xffffffffffUL 934 #define AMD_ABOVE_1TB_START (AMD_HT_END + 1) 935 #define AMD_HT_SIZE (AMD_ABOVE_1TB_START - AMD_HT_START) 936 937 void pc_memory_init(PCMachineState *pcms, 938 MemoryRegion *system_memory, 939 MemoryRegion *rom_memory, 940 MemoryRegion **ram_memory, 941 uint64_t pci_hole64_size) 942 { 943 int linux_boot, i; 944 MemoryRegion *option_rom_mr; 945 MemoryRegion *ram_below_4g, *ram_above_4g; 946 FWCfgState *fw_cfg; 947 MachineState *machine = MACHINE(pcms); 948 MachineClass *mc = MACHINE_GET_CLASS(machine); 949 PCMachineClass *pcmc = PC_MACHINE_GET_CLASS(pcms); 950 X86MachineState *x86ms = X86_MACHINE(pcms); 951 hwaddr maxphysaddr, maxusedaddr; 952 hwaddr cxl_base, cxl_resv_end = 0; 953 X86CPU *cpu = X86_CPU(first_cpu); 954 955 assert(machine->ram_size == x86ms->below_4g_mem_size + 956 x86ms->above_4g_mem_size); 957 958 linux_boot = (machine->kernel_filename != NULL); 959 960 /* 961 * The HyperTransport range close to the 1T boundary is unique to AMD 962 * hosts with IOMMUs enabled. Restrict the ram-above-4g relocation 963 * to above 1T to AMD vCPUs only. @enforce_amd_1tb_hole is only false in 964 * older machine types (<= 7.0) for compatibility purposes. 965 */ 966 if (IS_AMD_CPU(&cpu->env) && pcmc->enforce_amd_1tb_hole) { 967 /* Bail out if max possible address does not cross HT range */ 968 if (pc_max_used_gpa(pcms, pci_hole64_size) >= AMD_HT_START) { 969 x86ms->above_4g_mem_start = AMD_ABOVE_1TB_START; 970 } 971 972 /* 973 * Advertise the HT region if address space covers the reserved 974 * region or if we relocate. 975 */ 976 if (cpu->phys_bits >= 40) { 977 e820_add_entry(AMD_HT_START, AMD_HT_SIZE, E820_RESERVED); 978 } 979 } 980 981 /* 982 * phys-bits is required to be appropriately configured 983 * to make sure max used GPA is reachable. 984 */ 985 maxusedaddr = pc_max_used_gpa(pcms, pci_hole64_size); 986 maxphysaddr = ((hwaddr)1 << cpu->phys_bits) - 1; 987 if (maxphysaddr < maxusedaddr) { 988 error_report("Address space limit 0x%"PRIx64" < 0x%"PRIx64 989 " phys-bits too low (%u)", 990 maxphysaddr, maxusedaddr, cpu->phys_bits); 991 exit(EXIT_FAILURE); 992 } 993 994 /* 995 * Split single memory region and use aliases to address portions of it, 996 * done for backwards compatibility with older qemus. 997 */ 998 *ram_memory = machine->ram; 999 ram_below_4g = g_malloc(sizeof(*ram_below_4g)); 1000 memory_region_init_alias(ram_below_4g, NULL, "ram-below-4g", machine->ram, 1001 0, x86ms->below_4g_mem_size); 1002 memory_region_add_subregion(system_memory, 0, ram_below_4g); 1003 e820_add_entry(0, x86ms->below_4g_mem_size, E820_RAM); 1004 if (x86ms->above_4g_mem_size > 0) { 1005 ram_above_4g = g_malloc(sizeof(*ram_above_4g)); 1006 memory_region_init_alias(ram_above_4g, NULL, "ram-above-4g", 1007 machine->ram, 1008 x86ms->below_4g_mem_size, 1009 x86ms->above_4g_mem_size); 1010 memory_region_add_subregion(system_memory, x86ms->above_4g_mem_start, 1011 ram_above_4g); 1012 e820_add_entry(x86ms->above_4g_mem_start, x86ms->above_4g_mem_size, 1013 E820_RAM); 1014 } 1015 1016 if (pcms->sgx_epc.size != 0) { 1017 e820_add_entry(pcms->sgx_epc.base, pcms->sgx_epc.size, E820_RESERVED); 1018 } 1019 1020 if (!pcmc->has_reserved_memory && 1021 (machine->ram_slots || 1022 (machine->maxram_size > machine->ram_size))) { 1023 1024 error_report("\"-memory 'slots|maxmem'\" is not supported by: %s", 1025 mc->name); 1026 exit(EXIT_FAILURE); 1027 } 1028 1029 /* always allocate the device memory information */ 1030 machine->device_memory = g_malloc0(sizeof(*machine->device_memory)); 1031 1032 /* initialize device memory address space */ 1033 if (pcmc->has_reserved_memory && 1034 (machine->ram_size < machine->maxram_size)) { 1035 ram_addr_t device_mem_size; 1036 1037 if (machine->ram_slots > ACPI_MAX_RAM_SLOTS) { 1038 error_report("unsupported amount of memory slots: %"PRIu64, 1039 machine->ram_slots); 1040 exit(EXIT_FAILURE); 1041 } 1042 1043 if (QEMU_ALIGN_UP(machine->maxram_size, 1044 TARGET_PAGE_SIZE) != machine->maxram_size) { 1045 error_report("maximum memory size must by aligned to multiple of " 1046 "%d bytes", TARGET_PAGE_SIZE); 1047 exit(EXIT_FAILURE); 1048 } 1049 1050 pc_get_device_memory_range(pcms, &machine->device_memory->base, &device_mem_size); 1051 1052 if ((machine->device_memory->base + device_mem_size) < 1053 device_mem_size) { 1054 error_report("unsupported amount of maximum memory: " RAM_ADDR_FMT, 1055 machine->maxram_size); 1056 exit(EXIT_FAILURE); 1057 } 1058 1059 memory_region_init(&machine->device_memory->mr, OBJECT(pcms), 1060 "device-memory", device_mem_size); 1061 memory_region_add_subregion(system_memory, machine->device_memory->base, 1062 &machine->device_memory->mr); 1063 } 1064 1065 if (pcms->cxl_devices_state.is_enabled) { 1066 MemoryRegion *mr = &pcms->cxl_devices_state.host_mr; 1067 hwaddr cxl_size = MiB; 1068 1069 cxl_base = pc_get_cxl_range_start(pcms); 1070 memory_region_init(mr, OBJECT(machine), "cxl_host_reg", cxl_size); 1071 memory_region_add_subregion(system_memory, cxl_base, mr); 1072 cxl_resv_end = cxl_base + cxl_size; 1073 if (pcms->cxl_devices_state.fixed_windows) { 1074 hwaddr cxl_fmw_base; 1075 GList *it; 1076 1077 cxl_fmw_base = ROUND_UP(cxl_base + cxl_size, 256 * MiB); 1078 for (it = pcms->cxl_devices_state.fixed_windows; it; it = it->next) { 1079 CXLFixedWindow *fw = it->data; 1080 1081 fw->base = cxl_fmw_base; 1082 memory_region_init_io(&fw->mr, OBJECT(machine), &cfmws_ops, fw, 1083 "cxl-fixed-memory-region", fw->size); 1084 memory_region_add_subregion(system_memory, fw->base, &fw->mr); 1085 cxl_fmw_base += fw->size; 1086 cxl_resv_end = cxl_fmw_base; 1087 } 1088 } 1089 } 1090 1091 /* Initialize PC system firmware */ 1092 pc_system_firmware_init(pcms, rom_memory); 1093 1094 option_rom_mr = g_malloc(sizeof(*option_rom_mr)); 1095 memory_region_init_ram(option_rom_mr, NULL, "pc.rom", PC_ROM_SIZE, 1096 &error_fatal); 1097 if (pcmc->pci_enabled) { 1098 memory_region_set_readonly(option_rom_mr, true); 1099 } 1100 memory_region_add_subregion_overlap(rom_memory, 1101 PC_ROM_MIN_VGA, 1102 option_rom_mr, 1103 1); 1104 1105 fw_cfg = fw_cfg_arch_create(machine, 1106 x86ms->boot_cpus, x86ms->apic_id_limit); 1107 1108 rom_set_fw(fw_cfg); 1109 1110 if (pcmc->has_reserved_memory && machine->device_memory->base) { 1111 uint64_t *val = g_malloc(sizeof(*val)); 1112 PCMachineClass *pcmc = PC_MACHINE_GET_CLASS(pcms); 1113 uint64_t res_mem_end = machine->device_memory->base; 1114 1115 if (!pcmc->broken_reserved_end) { 1116 res_mem_end += memory_region_size(&machine->device_memory->mr); 1117 } 1118 1119 if (pcms->cxl_devices_state.is_enabled) { 1120 res_mem_end = cxl_resv_end; 1121 } 1122 *val = cpu_to_le64(ROUND_UP(res_mem_end, 1 * GiB)); 1123 fw_cfg_add_file(fw_cfg, "etc/reserved-memory-end", val, sizeof(*val)); 1124 } 1125 1126 if (linux_boot) { 1127 x86_load_linux(x86ms, fw_cfg, pcmc->acpi_data_size, 1128 pcmc->pvh_enabled, pcmc->legacy_no_rng_seed); 1129 } 1130 1131 for (i = 0; i < nb_option_roms; i++) { 1132 rom_add_option(option_rom[i].name, option_rom[i].bootindex); 1133 } 1134 x86ms->fw_cfg = fw_cfg; 1135 1136 /* Init default IOAPIC address space */ 1137 x86ms->ioapic_as = &address_space_memory; 1138 1139 /* Init ACPI memory hotplug IO base address */ 1140 pcms->memhp_io_base = ACPI_MEMORY_HOTPLUG_BASE; 1141 } 1142 1143 /* 1144 * The 64bit pci hole starts after "above 4G RAM" and 1145 * potentially the space reserved for memory hotplug. 1146 */ 1147 uint64_t pc_pci_hole64_start(void) 1148 { 1149 PCMachineState *pcms = PC_MACHINE(qdev_get_machine()); 1150 PCMachineClass *pcmc = PC_MACHINE_GET_CLASS(pcms); 1151 MachineState *ms = MACHINE(pcms); 1152 uint64_t hole64_start = 0; 1153 ram_addr_t size = 0; 1154 1155 if (pcms->cxl_devices_state.is_enabled) { 1156 hole64_start = pc_get_cxl_range_end(pcms); 1157 } else if (pcmc->has_reserved_memory && (ms->ram_size < ms->maxram_size)) { 1158 pc_get_device_memory_range(pcms, &hole64_start, &size); 1159 if (!pcmc->broken_reserved_end) { 1160 hole64_start += size; 1161 } 1162 } else { 1163 hole64_start = pc_above_4g_end(pcms); 1164 } 1165 1166 return ROUND_UP(hole64_start, 1 * GiB); 1167 } 1168 1169 DeviceState *pc_vga_init(ISABus *isa_bus, PCIBus *pci_bus) 1170 { 1171 DeviceState *dev = NULL; 1172 1173 rom_set_order_override(FW_CFG_ORDER_OVERRIDE_VGA); 1174 if (pci_bus) { 1175 PCIDevice *pcidev = pci_vga_init(pci_bus); 1176 dev = pcidev ? &pcidev->qdev : NULL; 1177 } else if (isa_bus) { 1178 ISADevice *isadev = isa_vga_init(isa_bus); 1179 dev = isadev ? DEVICE(isadev) : NULL; 1180 } 1181 rom_reset_order_override(); 1182 return dev; 1183 } 1184 1185 static const MemoryRegionOps ioport80_io_ops = { 1186 .write = ioport80_write, 1187 .read = ioport80_read, 1188 .endianness = DEVICE_NATIVE_ENDIAN, 1189 .impl = { 1190 .min_access_size = 1, 1191 .max_access_size = 1, 1192 }, 1193 }; 1194 1195 static const MemoryRegionOps ioportF0_io_ops = { 1196 .write = ioportF0_write, 1197 .read = ioportF0_read, 1198 .endianness = DEVICE_NATIVE_ENDIAN, 1199 .impl = { 1200 .min_access_size = 1, 1201 .max_access_size = 1, 1202 }, 1203 }; 1204 1205 static void pc_superio_init(ISABus *isa_bus, bool create_fdctrl, 1206 bool create_i8042, bool no_vmport) 1207 { 1208 int i; 1209 DriveInfo *fd[MAX_FD]; 1210 qemu_irq *a20_line; 1211 ISADevice *fdc, *i8042, *port92, *vmmouse; 1212 1213 serial_hds_isa_init(isa_bus, 0, MAX_ISA_SERIAL_PORTS); 1214 parallel_hds_isa_init(isa_bus, MAX_PARALLEL_PORTS); 1215 1216 for (i = 0; i < MAX_FD; i++) { 1217 fd[i] = drive_get(IF_FLOPPY, 0, i); 1218 create_fdctrl |= !!fd[i]; 1219 } 1220 if (create_fdctrl) { 1221 fdc = isa_new(TYPE_ISA_FDC); 1222 if (fdc) { 1223 isa_realize_and_unref(fdc, isa_bus, &error_fatal); 1224 isa_fdc_init_drives(fdc, fd); 1225 } 1226 } 1227 1228 if (!create_i8042) { 1229 return; 1230 } 1231 1232 i8042 = isa_create_simple(isa_bus, TYPE_I8042); 1233 if (!no_vmport) { 1234 isa_create_simple(isa_bus, TYPE_VMPORT); 1235 vmmouse = isa_try_new("vmmouse"); 1236 } else { 1237 vmmouse = NULL; 1238 } 1239 if (vmmouse) { 1240 object_property_set_link(OBJECT(vmmouse), TYPE_I8042, OBJECT(i8042), 1241 &error_abort); 1242 isa_realize_and_unref(vmmouse, isa_bus, &error_fatal); 1243 } 1244 port92 = isa_create_simple(isa_bus, TYPE_PORT92); 1245 1246 a20_line = qemu_allocate_irqs(handle_a20_line_change, first_cpu, 2); 1247 i8042_setup_a20_line(i8042, a20_line[0]); 1248 qdev_connect_gpio_out_named(DEVICE(port92), 1249 PORT92_A20_LINE, 0, a20_line[1]); 1250 g_free(a20_line); 1251 } 1252 1253 void pc_basic_device_init(struct PCMachineState *pcms, 1254 ISABus *isa_bus, qemu_irq *gsi, 1255 ISADevice **rtc_state, 1256 bool create_fdctrl, 1257 uint32_t hpet_irqs) 1258 { 1259 int i; 1260 DeviceState *hpet = NULL; 1261 int pit_isa_irq = 0; 1262 qemu_irq pit_alt_irq = NULL; 1263 qemu_irq rtc_irq = NULL; 1264 ISADevice *pit = NULL; 1265 MemoryRegion *ioport80_io = g_new(MemoryRegion, 1); 1266 MemoryRegion *ioportF0_io = g_new(MemoryRegion, 1); 1267 X86MachineState *x86ms = X86_MACHINE(pcms); 1268 1269 memory_region_init_io(ioport80_io, NULL, &ioport80_io_ops, NULL, "ioport80", 1); 1270 memory_region_add_subregion(isa_bus->address_space_io, 0x80, ioport80_io); 1271 1272 memory_region_init_io(ioportF0_io, NULL, &ioportF0_io_ops, NULL, "ioportF0", 1); 1273 memory_region_add_subregion(isa_bus->address_space_io, 0xf0, ioportF0_io); 1274 1275 /* 1276 * Check if an HPET shall be created. 1277 * 1278 * Without KVM_CAP_PIT_STATE2, we cannot switch off the in-kernel PIT 1279 * when the HPET wants to take over. Thus we have to disable the latter. 1280 */ 1281 if (pcms->hpet_enabled && (!kvm_irqchip_in_kernel() || 1282 kvm_has_pit_state2())) { 1283 hpet = qdev_try_new(TYPE_HPET); 1284 if (!hpet) { 1285 error_report("couldn't create HPET device"); 1286 exit(1); 1287 } 1288 /* 1289 * For pc-piix-*, hpet's intcap is always IRQ2. For pc-q35-1.7 and 1290 * earlier, use IRQ2 for compat. Otherwise, use IRQ16~23, IRQ8 and 1291 * IRQ2. 1292 */ 1293 uint8_t compat = object_property_get_uint(OBJECT(hpet), 1294 HPET_INTCAP, NULL); 1295 if (!compat) { 1296 qdev_prop_set_uint32(hpet, HPET_INTCAP, hpet_irqs); 1297 } 1298 sysbus_realize_and_unref(SYS_BUS_DEVICE(hpet), &error_fatal); 1299 sysbus_mmio_map(SYS_BUS_DEVICE(hpet), 0, HPET_BASE); 1300 1301 for (i = 0; i < IOAPIC_NUM_PINS; i++) { 1302 sysbus_connect_irq(SYS_BUS_DEVICE(hpet), i, gsi[i]); 1303 } 1304 pit_isa_irq = -1; 1305 pit_alt_irq = qdev_get_gpio_in(hpet, HPET_LEGACY_PIT_INT); 1306 rtc_irq = qdev_get_gpio_in(hpet, HPET_LEGACY_RTC_INT); 1307 } 1308 *rtc_state = ISA_DEVICE(mc146818_rtc_init(isa_bus, 2000, rtc_irq)); 1309 1310 qemu_register_boot_set(pc_boot_set, *rtc_state); 1311 1312 if (!xen_enabled() && 1313 (x86ms->pit == ON_OFF_AUTO_AUTO || x86ms->pit == ON_OFF_AUTO_ON)) { 1314 if (kvm_pit_in_kernel()) { 1315 pit = kvm_pit_init(isa_bus, 0x40); 1316 } else { 1317 pit = i8254_pit_init(isa_bus, 0x40, pit_isa_irq, pit_alt_irq); 1318 } 1319 if (hpet) { 1320 /* connect PIT to output control line of the HPET */ 1321 qdev_connect_gpio_out(hpet, 0, qdev_get_gpio_in(DEVICE(pit), 0)); 1322 } 1323 pcspk_init(pcms->pcspk, isa_bus, pit); 1324 } 1325 1326 /* Super I/O */ 1327 pc_superio_init(isa_bus, create_fdctrl, pcms->i8042_enabled, 1328 pcms->vmport != ON_OFF_AUTO_ON); 1329 } 1330 1331 void pc_nic_init(PCMachineClass *pcmc, ISABus *isa_bus, PCIBus *pci_bus) 1332 { 1333 int i; 1334 1335 rom_set_order_override(FW_CFG_ORDER_OVERRIDE_NIC); 1336 for (i = 0; i < nb_nics; i++) { 1337 NICInfo *nd = &nd_table[i]; 1338 const char *model = nd->model ? nd->model : pcmc->default_nic_model; 1339 1340 if (g_str_equal(model, "ne2k_isa")) { 1341 pc_init_ne2k_isa(isa_bus, nd); 1342 } else { 1343 pci_nic_init_nofail(nd, pci_bus, model, NULL); 1344 } 1345 } 1346 rom_reset_order_override(); 1347 } 1348 1349 void pc_i8259_create(ISABus *isa_bus, qemu_irq *i8259_irqs) 1350 { 1351 qemu_irq *i8259; 1352 1353 if (kvm_pic_in_kernel()) { 1354 i8259 = kvm_i8259_init(isa_bus); 1355 } else if (xen_enabled()) { 1356 i8259 = xen_interrupt_controller_init(); 1357 } else { 1358 i8259 = i8259_init(isa_bus, x86_allocate_cpu_irq()); 1359 } 1360 1361 for (size_t i = 0; i < ISA_NUM_IRQS; i++) { 1362 i8259_irqs[i] = i8259[i]; 1363 } 1364 1365 g_free(i8259); 1366 } 1367 1368 static void pc_memory_pre_plug(HotplugHandler *hotplug_dev, DeviceState *dev, 1369 Error **errp) 1370 { 1371 const PCMachineState *pcms = PC_MACHINE(hotplug_dev); 1372 const X86MachineState *x86ms = X86_MACHINE(hotplug_dev); 1373 const PCMachineClass *pcmc = PC_MACHINE_GET_CLASS(pcms); 1374 const MachineState *ms = MACHINE(hotplug_dev); 1375 const bool is_nvdimm = object_dynamic_cast(OBJECT(dev), TYPE_NVDIMM); 1376 const uint64_t legacy_align = TARGET_PAGE_SIZE; 1377 Error *local_err = NULL; 1378 1379 /* 1380 * When -no-acpi is used with Q35 machine type, no ACPI is built, 1381 * but pcms->acpi_dev is still created. Check !acpi_enabled in 1382 * addition to cover this case. 1383 */ 1384 if (!x86ms->acpi_dev || !x86_machine_is_acpi_enabled(x86ms)) { 1385 error_setg(errp, 1386 "memory hotplug is not enabled: missing acpi device or acpi disabled"); 1387 return; 1388 } 1389 1390 if (is_nvdimm && !ms->nvdimms_state->is_enabled) { 1391 error_setg(errp, "nvdimm is not enabled: missing 'nvdimm' in '-M'"); 1392 return; 1393 } 1394 1395 hotplug_handler_pre_plug(x86ms->acpi_dev, dev, &local_err); 1396 if (local_err) { 1397 error_propagate(errp, local_err); 1398 return; 1399 } 1400 1401 pc_dimm_pre_plug(PC_DIMM(dev), MACHINE(hotplug_dev), 1402 pcmc->enforce_aligned_dimm ? NULL : &legacy_align, errp); 1403 } 1404 1405 static void pc_memory_plug(HotplugHandler *hotplug_dev, 1406 DeviceState *dev, Error **errp) 1407 { 1408 PCMachineState *pcms = PC_MACHINE(hotplug_dev); 1409 X86MachineState *x86ms = X86_MACHINE(hotplug_dev); 1410 MachineState *ms = MACHINE(hotplug_dev); 1411 bool is_nvdimm = object_dynamic_cast(OBJECT(dev), TYPE_NVDIMM); 1412 1413 pc_dimm_plug(PC_DIMM(dev), MACHINE(pcms)); 1414 1415 if (is_nvdimm) { 1416 nvdimm_plug(ms->nvdimms_state); 1417 } 1418 1419 hotplug_handler_plug(x86ms->acpi_dev, dev, &error_abort); 1420 } 1421 1422 static void pc_memory_unplug_request(HotplugHandler *hotplug_dev, 1423 DeviceState *dev, Error **errp) 1424 { 1425 X86MachineState *x86ms = X86_MACHINE(hotplug_dev); 1426 1427 /* 1428 * When -no-acpi is used with Q35 machine type, no ACPI is built, 1429 * but pcms->acpi_dev is still created. Check !acpi_enabled in 1430 * addition to cover this case. 1431 */ 1432 if (!x86ms->acpi_dev || !x86_machine_is_acpi_enabled(x86ms)) { 1433 error_setg(errp, 1434 "memory hotplug is not enabled: missing acpi device or acpi disabled"); 1435 return; 1436 } 1437 1438 if (object_dynamic_cast(OBJECT(dev), TYPE_NVDIMM)) { 1439 error_setg(errp, "nvdimm device hot unplug is not supported yet."); 1440 return; 1441 } 1442 1443 hotplug_handler_unplug_request(x86ms->acpi_dev, dev, 1444 errp); 1445 } 1446 1447 static void pc_memory_unplug(HotplugHandler *hotplug_dev, 1448 DeviceState *dev, Error **errp) 1449 { 1450 PCMachineState *pcms = PC_MACHINE(hotplug_dev); 1451 X86MachineState *x86ms = X86_MACHINE(hotplug_dev); 1452 Error *local_err = NULL; 1453 1454 hotplug_handler_unplug(x86ms->acpi_dev, dev, &local_err); 1455 if (local_err) { 1456 goto out; 1457 } 1458 1459 pc_dimm_unplug(PC_DIMM(dev), MACHINE(pcms)); 1460 qdev_unrealize(dev); 1461 out: 1462 error_propagate(errp, local_err); 1463 } 1464 1465 static void pc_virtio_md_pci_pre_plug(HotplugHandler *hotplug_dev, 1466 DeviceState *dev, Error **errp) 1467 { 1468 HotplugHandler *hotplug_dev2 = qdev_get_bus_hotplug_handler(dev); 1469 Error *local_err = NULL; 1470 1471 if (!hotplug_dev2 && dev->hotplugged) { 1472 /* 1473 * Without a bus hotplug handler, we cannot control the plug/unplug 1474 * order. We should never reach this point when hotplugging on x86, 1475 * however, better add a safety net. 1476 */ 1477 error_setg(errp, "hotplug of virtio based memory devices not supported" 1478 " on this bus."); 1479 return; 1480 } 1481 /* 1482 * First, see if we can plug this memory device at all. If that 1483 * succeeds, branch of to the actual hotplug handler. 1484 */ 1485 memory_device_pre_plug(MEMORY_DEVICE(dev), MACHINE(hotplug_dev), NULL, 1486 &local_err); 1487 if (!local_err && hotplug_dev2) { 1488 hotplug_handler_pre_plug(hotplug_dev2, dev, &local_err); 1489 } 1490 error_propagate(errp, local_err); 1491 } 1492 1493 static void pc_virtio_md_pci_plug(HotplugHandler *hotplug_dev, 1494 DeviceState *dev, Error **errp) 1495 { 1496 HotplugHandler *hotplug_dev2 = qdev_get_bus_hotplug_handler(dev); 1497 Error *local_err = NULL; 1498 1499 /* 1500 * Plug the memory device first and then branch off to the actual 1501 * hotplug handler. If that one fails, we can easily undo the memory 1502 * device bits. 1503 */ 1504 memory_device_plug(MEMORY_DEVICE(dev), MACHINE(hotplug_dev)); 1505 if (hotplug_dev2) { 1506 hotplug_handler_plug(hotplug_dev2, dev, &local_err); 1507 if (local_err) { 1508 memory_device_unplug(MEMORY_DEVICE(dev), MACHINE(hotplug_dev)); 1509 } 1510 } 1511 error_propagate(errp, local_err); 1512 } 1513 1514 static void pc_virtio_md_pci_unplug_request(HotplugHandler *hotplug_dev, 1515 DeviceState *dev, Error **errp) 1516 { 1517 /* We don't support hot unplug of virtio based memory devices */ 1518 error_setg(errp, "virtio based memory devices cannot be unplugged."); 1519 } 1520 1521 static void pc_virtio_md_pci_unplug(HotplugHandler *hotplug_dev, 1522 DeviceState *dev, Error **errp) 1523 { 1524 /* We don't support hot unplug of virtio based memory devices */ 1525 } 1526 1527 static void pc_machine_device_pre_plug_cb(HotplugHandler *hotplug_dev, 1528 DeviceState *dev, Error **errp) 1529 { 1530 if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM)) { 1531 pc_memory_pre_plug(hotplug_dev, dev, errp); 1532 } else if (object_dynamic_cast(OBJECT(dev), TYPE_CPU)) { 1533 x86_cpu_pre_plug(hotplug_dev, dev, errp); 1534 } else if (object_dynamic_cast(OBJECT(dev), TYPE_VIRTIO_PMEM_PCI) || 1535 object_dynamic_cast(OBJECT(dev), TYPE_VIRTIO_MEM_PCI)) { 1536 pc_virtio_md_pci_pre_plug(hotplug_dev, dev, errp); 1537 } else if (object_dynamic_cast(OBJECT(dev), TYPE_VIRTIO_IOMMU_PCI)) { 1538 /* Declare the APIC range as the reserved MSI region */ 1539 char *resv_prop_str = g_strdup_printf("0xfee00000:0xfeefffff:%d", 1540 VIRTIO_IOMMU_RESV_MEM_T_MSI); 1541 1542 object_property_set_uint(OBJECT(dev), "len-reserved-regions", 1, errp); 1543 object_property_set_str(OBJECT(dev), "reserved-regions[0]", 1544 resv_prop_str, errp); 1545 g_free(resv_prop_str); 1546 } 1547 1548 if (object_dynamic_cast(OBJECT(dev), TYPE_X86_IOMMU_DEVICE) || 1549 object_dynamic_cast(OBJECT(dev), TYPE_VIRTIO_IOMMU_PCI)) { 1550 PCMachineState *pcms = PC_MACHINE(hotplug_dev); 1551 1552 if (pcms->iommu) { 1553 error_setg(errp, "QEMU does not support multiple vIOMMUs " 1554 "for x86 yet."); 1555 return; 1556 } 1557 pcms->iommu = dev; 1558 } 1559 } 1560 1561 static void pc_machine_device_plug_cb(HotplugHandler *hotplug_dev, 1562 DeviceState *dev, Error **errp) 1563 { 1564 if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM)) { 1565 pc_memory_plug(hotplug_dev, dev, errp); 1566 } else if (object_dynamic_cast(OBJECT(dev), TYPE_CPU)) { 1567 x86_cpu_plug(hotplug_dev, dev, errp); 1568 } else if (object_dynamic_cast(OBJECT(dev), TYPE_VIRTIO_PMEM_PCI) || 1569 object_dynamic_cast(OBJECT(dev), TYPE_VIRTIO_MEM_PCI)) { 1570 pc_virtio_md_pci_plug(hotplug_dev, dev, errp); 1571 } 1572 } 1573 1574 static void pc_machine_device_unplug_request_cb(HotplugHandler *hotplug_dev, 1575 DeviceState *dev, Error **errp) 1576 { 1577 if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM)) { 1578 pc_memory_unplug_request(hotplug_dev, dev, errp); 1579 } else if (object_dynamic_cast(OBJECT(dev), TYPE_CPU)) { 1580 x86_cpu_unplug_request_cb(hotplug_dev, dev, errp); 1581 } else if (object_dynamic_cast(OBJECT(dev), TYPE_VIRTIO_PMEM_PCI) || 1582 object_dynamic_cast(OBJECT(dev), TYPE_VIRTIO_MEM_PCI)) { 1583 pc_virtio_md_pci_unplug_request(hotplug_dev, dev, errp); 1584 } else { 1585 error_setg(errp, "acpi: device unplug request for not supported device" 1586 " type: %s", object_get_typename(OBJECT(dev))); 1587 } 1588 } 1589 1590 static void pc_machine_device_unplug_cb(HotplugHandler *hotplug_dev, 1591 DeviceState *dev, Error **errp) 1592 { 1593 if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM)) { 1594 pc_memory_unplug(hotplug_dev, dev, errp); 1595 } else if (object_dynamic_cast(OBJECT(dev), TYPE_CPU)) { 1596 x86_cpu_unplug_cb(hotplug_dev, dev, errp); 1597 } else if (object_dynamic_cast(OBJECT(dev), TYPE_VIRTIO_PMEM_PCI) || 1598 object_dynamic_cast(OBJECT(dev), TYPE_VIRTIO_MEM_PCI)) { 1599 pc_virtio_md_pci_unplug(hotplug_dev, dev, errp); 1600 } else { 1601 error_setg(errp, "acpi: device unplug for not supported device" 1602 " type: %s", object_get_typename(OBJECT(dev))); 1603 } 1604 } 1605 1606 static HotplugHandler *pc_get_hotplug_handler(MachineState *machine, 1607 DeviceState *dev) 1608 { 1609 if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM) || 1610 object_dynamic_cast(OBJECT(dev), TYPE_CPU) || 1611 object_dynamic_cast(OBJECT(dev), TYPE_VIRTIO_PMEM_PCI) || 1612 object_dynamic_cast(OBJECT(dev), TYPE_VIRTIO_MEM_PCI) || 1613 object_dynamic_cast(OBJECT(dev), TYPE_VIRTIO_IOMMU_PCI) || 1614 object_dynamic_cast(OBJECT(dev), TYPE_X86_IOMMU_DEVICE)) { 1615 return HOTPLUG_HANDLER(machine); 1616 } 1617 1618 return NULL; 1619 } 1620 1621 static void 1622 pc_machine_get_device_memory_region_size(Object *obj, Visitor *v, 1623 const char *name, void *opaque, 1624 Error **errp) 1625 { 1626 MachineState *ms = MACHINE(obj); 1627 int64_t value = 0; 1628 1629 if (ms->device_memory) { 1630 value = memory_region_size(&ms->device_memory->mr); 1631 } 1632 1633 visit_type_int(v, name, &value, errp); 1634 } 1635 1636 static void pc_machine_get_vmport(Object *obj, Visitor *v, const char *name, 1637 void *opaque, Error **errp) 1638 { 1639 PCMachineState *pcms = PC_MACHINE(obj); 1640 OnOffAuto vmport = pcms->vmport; 1641 1642 visit_type_OnOffAuto(v, name, &vmport, errp); 1643 } 1644 1645 static void pc_machine_set_vmport(Object *obj, Visitor *v, const char *name, 1646 void *opaque, Error **errp) 1647 { 1648 PCMachineState *pcms = PC_MACHINE(obj); 1649 1650 visit_type_OnOffAuto(v, name, &pcms->vmport, errp); 1651 } 1652 1653 static bool pc_machine_get_smbus(Object *obj, Error **errp) 1654 { 1655 PCMachineState *pcms = PC_MACHINE(obj); 1656 1657 return pcms->smbus_enabled; 1658 } 1659 1660 static void pc_machine_set_smbus(Object *obj, bool value, Error **errp) 1661 { 1662 PCMachineState *pcms = PC_MACHINE(obj); 1663 1664 pcms->smbus_enabled = value; 1665 } 1666 1667 static bool pc_machine_get_sata(Object *obj, Error **errp) 1668 { 1669 PCMachineState *pcms = PC_MACHINE(obj); 1670 1671 return pcms->sata_enabled; 1672 } 1673 1674 static void pc_machine_set_sata(Object *obj, bool value, Error **errp) 1675 { 1676 PCMachineState *pcms = PC_MACHINE(obj); 1677 1678 pcms->sata_enabled = value; 1679 } 1680 1681 static bool pc_machine_get_hpet(Object *obj, Error **errp) 1682 { 1683 PCMachineState *pcms = PC_MACHINE(obj); 1684 1685 return pcms->hpet_enabled; 1686 } 1687 1688 static void pc_machine_set_hpet(Object *obj, bool value, Error **errp) 1689 { 1690 PCMachineState *pcms = PC_MACHINE(obj); 1691 1692 pcms->hpet_enabled = value; 1693 } 1694 1695 static bool pc_machine_get_i8042(Object *obj, Error **errp) 1696 { 1697 PCMachineState *pcms = PC_MACHINE(obj); 1698 1699 return pcms->i8042_enabled; 1700 } 1701 1702 static void pc_machine_set_i8042(Object *obj, bool value, Error **errp) 1703 { 1704 PCMachineState *pcms = PC_MACHINE(obj); 1705 1706 pcms->i8042_enabled = value; 1707 } 1708 1709 static bool pc_machine_get_default_bus_bypass_iommu(Object *obj, Error **errp) 1710 { 1711 PCMachineState *pcms = PC_MACHINE(obj); 1712 1713 return pcms->default_bus_bypass_iommu; 1714 } 1715 1716 static void pc_machine_set_default_bus_bypass_iommu(Object *obj, bool value, 1717 Error **errp) 1718 { 1719 PCMachineState *pcms = PC_MACHINE(obj); 1720 1721 pcms->default_bus_bypass_iommu = value; 1722 } 1723 1724 static void pc_machine_get_smbios_ep(Object *obj, Visitor *v, const char *name, 1725 void *opaque, Error **errp) 1726 { 1727 PCMachineState *pcms = PC_MACHINE(obj); 1728 SmbiosEntryPointType smbios_entry_point_type = pcms->smbios_entry_point_type; 1729 1730 visit_type_SmbiosEntryPointType(v, name, &smbios_entry_point_type, errp); 1731 } 1732 1733 static void pc_machine_set_smbios_ep(Object *obj, Visitor *v, const char *name, 1734 void *opaque, Error **errp) 1735 { 1736 PCMachineState *pcms = PC_MACHINE(obj); 1737 1738 visit_type_SmbiosEntryPointType(v, name, &pcms->smbios_entry_point_type, errp); 1739 } 1740 1741 static void pc_machine_get_max_ram_below_4g(Object *obj, Visitor *v, 1742 const char *name, void *opaque, 1743 Error **errp) 1744 { 1745 PCMachineState *pcms = PC_MACHINE(obj); 1746 uint64_t value = pcms->max_ram_below_4g; 1747 1748 visit_type_size(v, name, &value, errp); 1749 } 1750 1751 static void pc_machine_set_max_ram_below_4g(Object *obj, Visitor *v, 1752 const char *name, void *opaque, 1753 Error **errp) 1754 { 1755 PCMachineState *pcms = PC_MACHINE(obj); 1756 uint64_t value; 1757 1758 if (!visit_type_size(v, name, &value, errp)) { 1759 return; 1760 } 1761 if (value > 4 * GiB) { 1762 error_setg(errp, 1763 "Machine option 'max-ram-below-4g=%"PRIu64 1764 "' expects size less than or equal to 4G", value); 1765 return; 1766 } 1767 1768 if (value < 1 * MiB) { 1769 warn_report("Only %" PRIu64 " bytes of RAM below the 4GiB boundary," 1770 "BIOS may not work with less than 1MiB", value); 1771 } 1772 1773 pcms->max_ram_below_4g = value; 1774 } 1775 1776 static void pc_machine_get_max_fw_size(Object *obj, Visitor *v, 1777 const char *name, void *opaque, 1778 Error **errp) 1779 { 1780 PCMachineState *pcms = PC_MACHINE(obj); 1781 uint64_t value = pcms->max_fw_size; 1782 1783 visit_type_size(v, name, &value, errp); 1784 } 1785 1786 static void pc_machine_set_max_fw_size(Object *obj, Visitor *v, 1787 const char *name, void *opaque, 1788 Error **errp) 1789 { 1790 PCMachineState *pcms = PC_MACHINE(obj); 1791 uint64_t value; 1792 1793 if (!visit_type_size(v, name, &value, errp)) { 1794 return; 1795 } 1796 1797 /* 1798 * We don't have a theoretically justifiable exact lower bound on the base 1799 * address of any flash mapping. In practice, the IO-APIC MMIO range is 1800 * [0xFEE00000..0xFEE01000] -- see IO_APIC_DEFAULT_ADDRESS --, leaving free 1801 * only 18MB-4KB below 4G. For now, restrict the cumulative mapping to 8MB in 1802 * size. 1803 */ 1804 if (value > 16 * MiB) { 1805 error_setg(errp, 1806 "User specified max allowed firmware size %" PRIu64 " is " 1807 "greater than 16MiB. If combined firwmare size exceeds " 1808 "16MiB the system may not boot, or experience intermittent" 1809 "stability issues.", 1810 value); 1811 return; 1812 } 1813 1814 pcms->max_fw_size = value; 1815 } 1816 1817 1818 static void pc_machine_initfn(Object *obj) 1819 { 1820 PCMachineState *pcms = PC_MACHINE(obj); 1821 1822 #ifdef CONFIG_VMPORT 1823 pcms->vmport = ON_OFF_AUTO_AUTO; 1824 #else 1825 pcms->vmport = ON_OFF_AUTO_OFF; 1826 #endif /* CONFIG_VMPORT */ 1827 pcms->max_ram_below_4g = 0; /* use default */ 1828 pcms->smbios_entry_point_type = SMBIOS_ENTRY_POINT_TYPE_32; 1829 1830 /* acpi build is enabled by default if machine supports it */ 1831 pcms->acpi_build_enabled = PC_MACHINE_GET_CLASS(pcms)->has_acpi_build; 1832 pcms->smbus_enabled = true; 1833 pcms->sata_enabled = true; 1834 pcms->i8042_enabled = true; 1835 pcms->max_fw_size = 8 * MiB; 1836 #ifdef CONFIG_HPET 1837 pcms->hpet_enabled = true; 1838 #endif 1839 pcms->default_bus_bypass_iommu = false; 1840 1841 pc_system_flash_create(pcms); 1842 pcms->pcspk = isa_new(TYPE_PC_SPEAKER); 1843 object_property_add_alias(OBJECT(pcms), "pcspk-audiodev", 1844 OBJECT(pcms->pcspk), "audiodev"); 1845 cxl_machine_init(obj, &pcms->cxl_devices_state); 1846 } 1847 1848 static void pc_machine_reset(MachineState *machine, ShutdownCause reason) 1849 { 1850 CPUState *cs; 1851 X86CPU *cpu; 1852 1853 qemu_devices_reset(reason); 1854 1855 /* Reset APIC after devices have been reset to cancel 1856 * any changes that qemu_devices_reset() might have done. 1857 */ 1858 CPU_FOREACH(cs) { 1859 cpu = X86_CPU(cs); 1860 1861 x86_cpu_after_reset(cpu); 1862 } 1863 } 1864 1865 static void pc_machine_wakeup(MachineState *machine) 1866 { 1867 cpu_synchronize_all_states(); 1868 pc_machine_reset(machine, SHUTDOWN_CAUSE_NONE); 1869 cpu_synchronize_all_post_reset(); 1870 } 1871 1872 static bool pc_hotplug_allowed(MachineState *ms, DeviceState *dev, Error **errp) 1873 { 1874 X86IOMMUState *iommu = x86_iommu_get_default(); 1875 IntelIOMMUState *intel_iommu; 1876 1877 if (iommu && 1878 object_dynamic_cast((Object *)iommu, TYPE_INTEL_IOMMU_DEVICE) && 1879 object_dynamic_cast((Object *)dev, "vfio-pci")) { 1880 intel_iommu = INTEL_IOMMU_DEVICE(iommu); 1881 if (!intel_iommu->caching_mode) { 1882 error_setg(errp, "Device assignment is not allowed without " 1883 "enabling caching-mode=on for Intel IOMMU."); 1884 return false; 1885 } 1886 } 1887 1888 return true; 1889 } 1890 1891 static void pc_machine_class_init(ObjectClass *oc, void *data) 1892 { 1893 MachineClass *mc = MACHINE_CLASS(oc); 1894 PCMachineClass *pcmc = PC_MACHINE_CLASS(oc); 1895 HotplugHandlerClass *hc = HOTPLUG_HANDLER_CLASS(oc); 1896 1897 pcmc->pci_enabled = true; 1898 pcmc->has_acpi_build = true; 1899 pcmc->rsdp_in_ram = true; 1900 pcmc->smbios_defaults = true; 1901 pcmc->smbios_uuid_encoded = true; 1902 pcmc->gigabyte_align = true; 1903 pcmc->has_reserved_memory = true; 1904 pcmc->kvmclock_enabled = true; 1905 pcmc->enforce_aligned_dimm = true; 1906 pcmc->enforce_amd_1tb_hole = true; 1907 /* BIOS ACPI tables: 128K. Other BIOS datastructures: less than 4K reported 1908 * to be used at the moment, 32K should be enough for a while. */ 1909 pcmc->acpi_data_size = 0x20000 + 0x8000; 1910 pcmc->pvh_enabled = true; 1911 pcmc->kvmclock_create_always = true; 1912 assert(!mc->get_hotplug_handler); 1913 mc->get_hotplug_handler = pc_get_hotplug_handler; 1914 mc->hotplug_allowed = pc_hotplug_allowed; 1915 mc->cpu_index_to_instance_props = x86_cpu_index_to_props; 1916 mc->get_default_cpu_node_id = x86_get_default_cpu_node_id; 1917 mc->possible_cpu_arch_ids = x86_possible_cpu_arch_ids; 1918 mc->auto_enable_numa_with_memhp = true; 1919 mc->auto_enable_numa_with_memdev = true; 1920 mc->has_hotpluggable_cpus = true; 1921 mc->default_boot_order = "cad"; 1922 mc->block_default_type = IF_IDE; 1923 mc->max_cpus = 255; 1924 mc->reset = pc_machine_reset; 1925 mc->wakeup = pc_machine_wakeup; 1926 hc->pre_plug = pc_machine_device_pre_plug_cb; 1927 hc->plug = pc_machine_device_plug_cb; 1928 hc->unplug_request = pc_machine_device_unplug_request_cb; 1929 hc->unplug = pc_machine_device_unplug_cb; 1930 mc->default_cpu_type = TARGET_DEFAULT_CPU_TYPE; 1931 mc->nvdimm_supported = true; 1932 mc->smp_props.dies_supported = true; 1933 mc->default_ram_id = "pc.ram"; 1934 1935 object_class_property_add(oc, PC_MACHINE_MAX_RAM_BELOW_4G, "size", 1936 pc_machine_get_max_ram_below_4g, pc_machine_set_max_ram_below_4g, 1937 NULL, NULL); 1938 object_class_property_set_description(oc, PC_MACHINE_MAX_RAM_BELOW_4G, 1939 "Maximum ram below the 4G boundary (32bit boundary)"); 1940 1941 object_class_property_add(oc, PC_MACHINE_DEVMEM_REGION_SIZE, "int", 1942 pc_machine_get_device_memory_region_size, NULL, 1943 NULL, NULL); 1944 1945 object_class_property_add(oc, PC_MACHINE_VMPORT, "OnOffAuto", 1946 pc_machine_get_vmport, pc_machine_set_vmport, 1947 NULL, NULL); 1948 object_class_property_set_description(oc, PC_MACHINE_VMPORT, 1949 "Enable vmport (pc & q35)"); 1950 1951 object_class_property_add_bool(oc, PC_MACHINE_SMBUS, 1952 pc_machine_get_smbus, pc_machine_set_smbus); 1953 object_class_property_set_description(oc, PC_MACHINE_SMBUS, 1954 "Enable/disable system management bus"); 1955 1956 object_class_property_add_bool(oc, PC_MACHINE_SATA, 1957 pc_machine_get_sata, pc_machine_set_sata); 1958 object_class_property_set_description(oc, PC_MACHINE_SATA, 1959 "Enable/disable Serial ATA bus"); 1960 1961 object_class_property_add_bool(oc, "hpet", 1962 pc_machine_get_hpet, pc_machine_set_hpet); 1963 object_class_property_set_description(oc, "hpet", 1964 "Enable/disable high precision event timer emulation"); 1965 1966 object_class_property_add_bool(oc, PC_MACHINE_I8042, 1967 pc_machine_get_i8042, pc_machine_set_i8042); 1968 1969 object_class_property_add_bool(oc, "default-bus-bypass-iommu", 1970 pc_machine_get_default_bus_bypass_iommu, 1971 pc_machine_set_default_bus_bypass_iommu); 1972 1973 object_class_property_add(oc, PC_MACHINE_MAX_FW_SIZE, "size", 1974 pc_machine_get_max_fw_size, pc_machine_set_max_fw_size, 1975 NULL, NULL); 1976 object_class_property_set_description(oc, PC_MACHINE_MAX_FW_SIZE, 1977 "Maximum combined firmware size"); 1978 1979 object_class_property_add(oc, PC_MACHINE_SMBIOS_EP, "str", 1980 pc_machine_get_smbios_ep, pc_machine_set_smbios_ep, 1981 NULL, NULL); 1982 object_class_property_set_description(oc, PC_MACHINE_SMBIOS_EP, 1983 "SMBIOS Entry Point type [32, 64]"); 1984 } 1985 1986 static const TypeInfo pc_machine_info = { 1987 .name = TYPE_PC_MACHINE, 1988 .parent = TYPE_X86_MACHINE, 1989 .abstract = true, 1990 .instance_size = sizeof(PCMachineState), 1991 .instance_init = pc_machine_initfn, 1992 .class_size = sizeof(PCMachineClass), 1993 .class_init = pc_machine_class_init, 1994 .interfaces = (InterfaceInfo[]) { 1995 { TYPE_HOTPLUG_HANDLER }, 1996 { } 1997 }, 1998 }; 1999 2000 static void pc_machine_register_types(void) 2001 { 2002 type_register_static(&pc_machine_info); 2003 } 2004 2005 type_init(pc_machine_register_types) 2006