1 /* 2 * QEMU PC System Emulator 3 * 4 * Copyright (c) 2003-2004 Fabrice Bellard 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a copy 7 * of this software and associated documentation files (the "Software"), to deal 8 * in the Software without restriction, including without limitation the rights 9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 10 * copies of the Software, and to permit persons to whom the Software is 11 * furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice shall be included in 14 * all copies or substantial portions of the Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN 22 * THE SOFTWARE. 23 */ 24 #include "hw/hw.h" 25 #include "hw/i386/pc.h" 26 #include "hw/char/serial.h" 27 #include "hw/i386/apic.h" 28 #include "hw/block/fdc.h" 29 #include "hw/ide.h" 30 #include "hw/pci/pci.h" 31 #include "monitor/monitor.h" 32 #include "hw/nvram/fw_cfg.h" 33 #include "hw/timer/hpet.h" 34 #include "hw/i386/smbios.h" 35 #include "hw/loader.h" 36 #include "elf.h" 37 #include "multiboot.h" 38 #include "hw/timer/mc146818rtc.h" 39 #include "hw/timer/i8254.h" 40 #include "hw/audio/pcspk.h" 41 #include "hw/pci/msi.h" 42 #include "hw/sysbus.h" 43 #include "sysemu/sysemu.h" 44 #include "sysemu/kvm.h" 45 #include "kvm_i386.h" 46 #include "hw/xen/xen.h" 47 #include "sysemu/blockdev.h" 48 #include "hw/block/block.h" 49 #include "ui/qemu-spice.h" 50 #include "exec/memory.h" 51 #include "exec/address-spaces.h" 52 #include "sysemu/arch_init.h" 53 #include "qemu/bitmap.h" 54 #include "qemu/config-file.h" 55 #include "hw/acpi/acpi.h" 56 #include "hw/cpu/icc_bus.h" 57 58 /* debug PC/ISA interrupts */ 59 //#define DEBUG_IRQ 60 61 #ifdef DEBUG_IRQ 62 #define DPRINTF(fmt, ...) \ 63 do { printf("CPUIRQ: " fmt , ## __VA_ARGS__); } while (0) 64 #else 65 #define DPRINTF(fmt, ...) 66 #endif 67 68 /* Leave a chunk of memory at the top of RAM for the BIOS ACPI tables. */ 69 #define ACPI_DATA_SIZE 0x10000 70 #define BIOS_CFG_IOPORT 0x510 71 #define FW_CFG_ACPI_TABLES (FW_CFG_ARCH_LOCAL + 0) 72 #define FW_CFG_SMBIOS_ENTRIES (FW_CFG_ARCH_LOCAL + 1) 73 #define FW_CFG_IRQ0_OVERRIDE (FW_CFG_ARCH_LOCAL + 2) 74 #define FW_CFG_E820_TABLE (FW_CFG_ARCH_LOCAL + 3) 75 #define FW_CFG_HPET (FW_CFG_ARCH_LOCAL + 4) 76 77 #define IO_APIC_DEFAULT_ADDRESS 0xfec00000 78 79 #define E820_NR_ENTRIES 16 80 81 struct e820_entry { 82 uint64_t address; 83 uint64_t length; 84 uint32_t type; 85 } QEMU_PACKED __attribute((__aligned__(4))); 86 87 struct e820_table { 88 uint32_t count; 89 struct e820_entry entry[E820_NR_ENTRIES]; 90 } QEMU_PACKED __attribute((__aligned__(4))); 91 92 static struct e820_table e820_table; 93 struct hpet_fw_config hpet_cfg = {.count = UINT8_MAX}; 94 95 void gsi_handler(void *opaque, int n, int level) 96 { 97 GSIState *s = opaque; 98 99 DPRINTF("pc: %s GSI %d\n", level ? "raising" : "lowering", n); 100 if (n < ISA_NUM_IRQS) { 101 qemu_set_irq(s->i8259_irq[n], level); 102 } 103 qemu_set_irq(s->ioapic_irq[n], level); 104 } 105 106 static void ioport80_write(void *opaque, hwaddr addr, uint64_t data, 107 unsigned size) 108 { 109 } 110 111 static uint64_t ioport80_read(void *opaque, hwaddr addr, unsigned size) 112 { 113 return 0xffffffffffffffffULL; 114 } 115 116 /* MSDOS compatibility mode FPU exception support */ 117 static qemu_irq ferr_irq; 118 119 void pc_register_ferr_irq(qemu_irq irq) 120 { 121 ferr_irq = irq; 122 } 123 124 /* XXX: add IGNNE support */ 125 void cpu_set_ferr(CPUX86State *s) 126 { 127 qemu_irq_raise(ferr_irq); 128 } 129 130 static void ioportF0_write(void *opaque, hwaddr addr, uint64_t data, 131 unsigned size) 132 { 133 qemu_irq_lower(ferr_irq); 134 } 135 136 static uint64_t ioportF0_read(void *opaque, hwaddr addr, unsigned size) 137 { 138 return 0xffffffffffffffffULL; 139 } 140 141 /* TSC handling */ 142 uint64_t cpu_get_tsc(CPUX86State *env) 143 { 144 return cpu_get_ticks(); 145 } 146 147 /* SMM support */ 148 149 static cpu_set_smm_t smm_set; 150 static void *smm_arg; 151 152 void cpu_smm_register(cpu_set_smm_t callback, void *arg) 153 { 154 assert(smm_set == NULL); 155 assert(smm_arg == NULL); 156 smm_set = callback; 157 smm_arg = arg; 158 } 159 160 void cpu_smm_update(CPUX86State *env) 161 { 162 if (smm_set && smm_arg && env == first_cpu) 163 smm_set(!!(env->hflags & HF_SMM_MASK), smm_arg); 164 } 165 166 167 /* IRQ handling */ 168 int cpu_get_pic_interrupt(CPUX86State *env) 169 { 170 int intno; 171 172 intno = apic_get_interrupt(env->apic_state); 173 if (intno >= 0) { 174 return intno; 175 } 176 /* read the irq from the PIC */ 177 if (!apic_accept_pic_intr(env->apic_state)) { 178 return -1; 179 } 180 181 intno = pic_read_irq(isa_pic); 182 return intno; 183 } 184 185 static void pic_irq_request(void *opaque, int irq, int level) 186 { 187 CPUX86State *env = first_cpu; 188 189 DPRINTF("pic_irqs: %s irq %d\n", level? "raise" : "lower", irq); 190 if (env->apic_state) { 191 while (env) { 192 if (apic_accept_pic_intr(env->apic_state)) { 193 apic_deliver_pic_intr(env->apic_state, level); 194 } 195 env = env->next_cpu; 196 } 197 } else { 198 CPUState *cs = CPU(x86_env_get_cpu(env)); 199 if (level) { 200 cpu_interrupt(cs, CPU_INTERRUPT_HARD); 201 } else { 202 cpu_reset_interrupt(cs, CPU_INTERRUPT_HARD); 203 } 204 } 205 } 206 207 /* PC cmos mappings */ 208 209 #define REG_EQUIPMENT_BYTE 0x14 210 211 static int cmos_get_fd_drive_type(FDriveType fd0) 212 { 213 int val; 214 215 switch (fd0) { 216 case FDRIVE_DRV_144: 217 /* 1.44 Mb 3"5 drive */ 218 val = 4; 219 break; 220 case FDRIVE_DRV_288: 221 /* 2.88 Mb 3"5 drive */ 222 val = 5; 223 break; 224 case FDRIVE_DRV_120: 225 /* 1.2 Mb 5"5 drive */ 226 val = 2; 227 break; 228 case FDRIVE_DRV_NONE: 229 default: 230 val = 0; 231 break; 232 } 233 return val; 234 } 235 236 static void cmos_init_hd(ISADevice *s, int type_ofs, int info_ofs, 237 int16_t cylinders, int8_t heads, int8_t sectors) 238 { 239 rtc_set_memory(s, type_ofs, 47); 240 rtc_set_memory(s, info_ofs, cylinders); 241 rtc_set_memory(s, info_ofs + 1, cylinders >> 8); 242 rtc_set_memory(s, info_ofs + 2, heads); 243 rtc_set_memory(s, info_ofs + 3, 0xff); 244 rtc_set_memory(s, info_ofs + 4, 0xff); 245 rtc_set_memory(s, info_ofs + 5, 0xc0 | ((heads > 8) << 3)); 246 rtc_set_memory(s, info_ofs + 6, cylinders); 247 rtc_set_memory(s, info_ofs + 7, cylinders >> 8); 248 rtc_set_memory(s, info_ofs + 8, sectors); 249 } 250 251 /* convert boot_device letter to something recognizable by the bios */ 252 static int boot_device2nibble(char boot_device) 253 { 254 switch(boot_device) { 255 case 'a': 256 case 'b': 257 return 0x01; /* floppy boot */ 258 case 'c': 259 return 0x02; /* hard drive boot */ 260 case 'd': 261 return 0x03; /* CD-ROM boot */ 262 case 'n': 263 return 0x04; /* Network boot */ 264 } 265 return 0; 266 } 267 268 static int set_boot_dev(ISADevice *s, const char *boot_device, int fd_bootchk) 269 { 270 #define PC_MAX_BOOT_DEVICES 3 271 int nbds, bds[3] = { 0, }; 272 int i; 273 274 nbds = strlen(boot_device); 275 if (nbds > PC_MAX_BOOT_DEVICES) { 276 error_report("Too many boot devices for PC"); 277 return(1); 278 } 279 for (i = 0; i < nbds; i++) { 280 bds[i] = boot_device2nibble(boot_device[i]); 281 if (bds[i] == 0) { 282 error_report("Invalid boot device for PC: '%c'", 283 boot_device[i]); 284 return(1); 285 } 286 } 287 rtc_set_memory(s, 0x3d, (bds[1] << 4) | bds[0]); 288 rtc_set_memory(s, 0x38, (bds[2] << 4) | (fd_bootchk ? 0x0 : 0x1)); 289 return(0); 290 } 291 292 static int pc_boot_set(void *opaque, const char *boot_device) 293 { 294 return set_boot_dev(opaque, boot_device, 0); 295 } 296 297 typedef struct pc_cmos_init_late_arg { 298 ISADevice *rtc_state; 299 BusState *idebus[2]; 300 } pc_cmos_init_late_arg; 301 302 static void pc_cmos_init_late(void *opaque) 303 { 304 pc_cmos_init_late_arg *arg = opaque; 305 ISADevice *s = arg->rtc_state; 306 int16_t cylinders; 307 int8_t heads, sectors; 308 int val; 309 int i, trans; 310 311 val = 0; 312 if (ide_get_geometry(arg->idebus[0], 0, 313 &cylinders, &heads, §ors) >= 0) { 314 cmos_init_hd(s, 0x19, 0x1b, cylinders, heads, sectors); 315 val |= 0xf0; 316 } 317 if (ide_get_geometry(arg->idebus[0], 1, 318 &cylinders, &heads, §ors) >= 0) { 319 cmos_init_hd(s, 0x1a, 0x24, cylinders, heads, sectors); 320 val |= 0x0f; 321 } 322 rtc_set_memory(s, 0x12, val); 323 324 val = 0; 325 for (i = 0; i < 4; i++) { 326 /* NOTE: ide_get_geometry() returns the physical 327 geometry. It is always such that: 1 <= sects <= 63, 1 328 <= heads <= 16, 1 <= cylinders <= 16383. The BIOS 329 geometry can be different if a translation is done. */ 330 if (ide_get_geometry(arg->idebus[i / 2], i % 2, 331 &cylinders, &heads, §ors) >= 0) { 332 trans = ide_get_bios_chs_trans(arg->idebus[i / 2], i % 2) - 1; 333 assert((trans & ~3) == 0); 334 val |= trans << (i * 2); 335 } 336 } 337 rtc_set_memory(s, 0x39, val); 338 339 qemu_unregister_reset(pc_cmos_init_late, opaque); 340 } 341 342 typedef struct RTCCPUHotplugArg { 343 Notifier cpu_added_notifier; 344 ISADevice *rtc_state; 345 } RTCCPUHotplugArg; 346 347 static void rtc_notify_cpu_added(Notifier *notifier, void *data) 348 { 349 RTCCPUHotplugArg *arg = container_of(notifier, RTCCPUHotplugArg, 350 cpu_added_notifier); 351 ISADevice *s = arg->rtc_state; 352 353 /* increment the number of CPUs */ 354 rtc_set_memory(s, 0x5f, rtc_get_memory(s, 0x5f) + 1); 355 } 356 357 void pc_cmos_init(ram_addr_t ram_size, ram_addr_t above_4g_mem_size, 358 const char *boot_device, 359 ISADevice *floppy, BusState *idebus0, BusState *idebus1, 360 ISADevice *s) 361 { 362 int val, nb, i; 363 FDriveType fd_type[2] = { FDRIVE_DRV_NONE, FDRIVE_DRV_NONE }; 364 static pc_cmos_init_late_arg arg; 365 static RTCCPUHotplugArg cpu_hotplug_cb; 366 367 /* various important CMOS locations needed by PC/Bochs bios */ 368 369 /* memory size */ 370 /* base memory (first MiB) */ 371 val = MIN(ram_size / 1024, 640); 372 rtc_set_memory(s, 0x15, val); 373 rtc_set_memory(s, 0x16, val >> 8); 374 /* extended memory (next 64MiB) */ 375 if (ram_size > 1024 * 1024) { 376 val = (ram_size - 1024 * 1024) / 1024; 377 } else { 378 val = 0; 379 } 380 if (val > 65535) 381 val = 65535; 382 rtc_set_memory(s, 0x17, val); 383 rtc_set_memory(s, 0x18, val >> 8); 384 rtc_set_memory(s, 0x30, val); 385 rtc_set_memory(s, 0x31, val >> 8); 386 /* memory between 16MiB and 4GiB */ 387 if (ram_size > 16 * 1024 * 1024) { 388 val = (ram_size - 16 * 1024 * 1024) / 65536; 389 } else { 390 val = 0; 391 } 392 if (val > 65535) 393 val = 65535; 394 rtc_set_memory(s, 0x34, val); 395 rtc_set_memory(s, 0x35, val >> 8); 396 /* memory above 4GiB */ 397 val = above_4g_mem_size / 65536; 398 rtc_set_memory(s, 0x5b, val); 399 rtc_set_memory(s, 0x5c, val >> 8); 400 rtc_set_memory(s, 0x5d, val >> 16); 401 402 /* set the number of CPU */ 403 rtc_set_memory(s, 0x5f, smp_cpus - 1); 404 /* init CPU hotplug notifier */ 405 cpu_hotplug_cb.rtc_state = s; 406 cpu_hotplug_cb.cpu_added_notifier.notify = rtc_notify_cpu_added; 407 qemu_register_cpu_added_notifier(&cpu_hotplug_cb.cpu_added_notifier); 408 409 /* set boot devices, and disable floppy signature check if requested */ 410 if (set_boot_dev(s, boot_device, fd_bootchk)) { 411 exit(1); 412 } 413 414 /* floppy type */ 415 if (floppy) { 416 for (i = 0; i < 2; i++) { 417 fd_type[i] = isa_fdc_get_drive_type(floppy, i); 418 } 419 } 420 val = (cmos_get_fd_drive_type(fd_type[0]) << 4) | 421 cmos_get_fd_drive_type(fd_type[1]); 422 rtc_set_memory(s, 0x10, val); 423 424 val = 0; 425 nb = 0; 426 if (fd_type[0] < FDRIVE_DRV_NONE) { 427 nb++; 428 } 429 if (fd_type[1] < FDRIVE_DRV_NONE) { 430 nb++; 431 } 432 switch (nb) { 433 case 0: 434 break; 435 case 1: 436 val |= 0x01; /* 1 drive, ready for boot */ 437 break; 438 case 2: 439 val |= 0x41; /* 2 drives, ready for boot */ 440 break; 441 } 442 val |= 0x02; /* FPU is there */ 443 val |= 0x04; /* PS/2 mouse installed */ 444 rtc_set_memory(s, REG_EQUIPMENT_BYTE, val); 445 446 /* hard drives */ 447 arg.rtc_state = s; 448 arg.idebus[0] = idebus0; 449 arg.idebus[1] = idebus1; 450 qemu_register_reset(pc_cmos_init_late, &arg); 451 } 452 453 #define TYPE_PORT92 "port92" 454 #define PORT92(obj) OBJECT_CHECK(Port92State, (obj), TYPE_PORT92) 455 456 /* port 92 stuff: could be split off */ 457 typedef struct Port92State { 458 ISADevice parent_obj; 459 460 MemoryRegion io; 461 uint8_t outport; 462 qemu_irq *a20_out; 463 } Port92State; 464 465 static void port92_write(void *opaque, hwaddr addr, uint64_t val, 466 unsigned size) 467 { 468 Port92State *s = opaque; 469 470 DPRINTF("port92: write 0x%02x\n", val); 471 s->outport = val; 472 qemu_set_irq(*s->a20_out, (val >> 1) & 1); 473 if (val & 1) { 474 qemu_system_reset_request(); 475 } 476 } 477 478 static uint64_t port92_read(void *opaque, hwaddr addr, 479 unsigned size) 480 { 481 Port92State *s = opaque; 482 uint32_t ret; 483 484 ret = s->outport; 485 DPRINTF("port92: read 0x%02x\n", ret); 486 return ret; 487 } 488 489 static void port92_init(ISADevice *dev, qemu_irq *a20_out) 490 { 491 Port92State *s = PORT92(dev); 492 493 s->a20_out = a20_out; 494 } 495 496 static const VMStateDescription vmstate_port92_isa = { 497 .name = "port92", 498 .version_id = 1, 499 .minimum_version_id = 1, 500 .minimum_version_id_old = 1, 501 .fields = (VMStateField []) { 502 VMSTATE_UINT8(outport, Port92State), 503 VMSTATE_END_OF_LIST() 504 } 505 }; 506 507 static void port92_reset(DeviceState *d) 508 { 509 Port92State *s = PORT92(d); 510 511 s->outport &= ~1; 512 } 513 514 static const MemoryRegionOps port92_ops = { 515 .read = port92_read, 516 .write = port92_write, 517 .impl = { 518 .min_access_size = 1, 519 .max_access_size = 1, 520 }, 521 .endianness = DEVICE_LITTLE_ENDIAN, 522 }; 523 524 static int port92_initfn(ISADevice *dev) 525 { 526 Port92State *s = PORT92(dev); 527 528 memory_region_init_io(&s->io, &port92_ops, s, "port92", 1); 529 isa_register_ioport(dev, &s->io, 0x92); 530 531 s->outport = 0; 532 return 0; 533 } 534 535 static void port92_class_initfn(ObjectClass *klass, void *data) 536 { 537 DeviceClass *dc = DEVICE_CLASS(klass); 538 ISADeviceClass *ic = ISA_DEVICE_CLASS(klass); 539 ic->init = port92_initfn; 540 dc->no_user = 1; 541 dc->reset = port92_reset; 542 dc->vmsd = &vmstate_port92_isa; 543 } 544 545 static const TypeInfo port92_info = { 546 .name = TYPE_PORT92, 547 .parent = TYPE_ISA_DEVICE, 548 .instance_size = sizeof(Port92State), 549 .class_init = port92_class_initfn, 550 }; 551 552 static void port92_register_types(void) 553 { 554 type_register_static(&port92_info); 555 } 556 557 type_init(port92_register_types) 558 559 static void handle_a20_line_change(void *opaque, int irq, int level) 560 { 561 X86CPU *cpu = opaque; 562 563 /* XXX: send to all CPUs ? */ 564 /* XXX: add logic to handle multiple A20 line sources */ 565 x86_cpu_set_a20(cpu, level); 566 } 567 568 int e820_add_entry(uint64_t address, uint64_t length, uint32_t type) 569 { 570 int index = le32_to_cpu(e820_table.count); 571 struct e820_entry *entry; 572 573 if (index >= E820_NR_ENTRIES) 574 return -EBUSY; 575 entry = &e820_table.entry[index++]; 576 577 entry->address = cpu_to_le64(address); 578 entry->length = cpu_to_le64(length); 579 entry->type = cpu_to_le32(type); 580 581 e820_table.count = cpu_to_le32(index); 582 return index; 583 } 584 585 /* Calculates the limit to CPU APIC ID values 586 * 587 * This function returns the limit for the APIC ID value, so that all 588 * CPU APIC IDs are < pc_apic_id_limit(). 589 * 590 * This is used for FW_CFG_MAX_CPUS. See comments on bochs_bios_init(). 591 */ 592 static unsigned int pc_apic_id_limit(unsigned int max_cpus) 593 { 594 return x86_cpu_apic_id_from_index(max_cpus - 1) + 1; 595 } 596 597 static void *bochs_bios_init(void) 598 { 599 void *fw_cfg; 600 uint8_t *smbios_table; 601 size_t smbios_len; 602 uint64_t *numa_fw_cfg; 603 int i, j; 604 unsigned int apic_id_limit = pc_apic_id_limit(max_cpus); 605 606 fw_cfg = fw_cfg_init(BIOS_CFG_IOPORT, BIOS_CFG_IOPORT + 1, 0, 0); 607 /* FW_CFG_MAX_CPUS is a bit confusing/problematic on x86: 608 * 609 * SeaBIOS needs FW_CFG_MAX_CPUS for CPU hotplug, but the CPU hotplug 610 * QEMU<->SeaBIOS interface is not based on the "CPU index", but on the APIC 611 * ID of hotplugged CPUs[1]. This means that FW_CFG_MAX_CPUS is not the 612 * "maximum number of CPUs", but the "limit to the APIC ID values SeaBIOS 613 * may see". 614 * 615 * So, this means we must not use max_cpus, here, but the maximum possible 616 * APIC ID value, plus one. 617 * 618 * [1] The only kind of "CPU identifier" used between SeaBIOS and QEMU is 619 * the APIC ID, not the "CPU index" 620 */ 621 fw_cfg_add_i16(fw_cfg, FW_CFG_MAX_CPUS, (uint16_t)apic_id_limit); 622 fw_cfg_add_i32(fw_cfg, FW_CFG_ID, 1); 623 fw_cfg_add_i64(fw_cfg, FW_CFG_RAM_SIZE, (uint64_t)ram_size); 624 fw_cfg_add_bytes(fw_cfg, FW_CFG_ACPI_TABLES, 625 acpi_tables, acpi_tables_len); 626 fw_cfg_add_i32(fw_cfg, FW_CFG_IRQ0_OVERRIDE, kvm_allows_irq0_override()); 627 628 smbios_table = smbios_get_table(&smbios_len); 629 if (smbios_table) 630 fw_cfg_add_bytes(fw_cfg, FW_CFG_SMBIOS_ENTRIES, 631 smbios_table, smbios_len); 632 fw_cfg_add_bytes(fw_cfg, FW_CFG_E820_TABLE, 633 &e820_table, sizeof(e820_table)); 634 635 fw_cfg_add_bytes(fw_cfg, FW_CFG_HPET, &hpet_cfg, sizeof(hpet_cfg)); 636 /* allocate memory for the NUMA channel: one (64bit) word for the number 637 * of nodes, one word for each VCPU->node and one word for each node to 638 * hold the amount of memory. 639 */ 640 numa_fw_cfg = g_new0(uint64_t, 1 + apic_id_limit + nb_numa_nodes); 641 numa_fw_cfg[0] = cpu_to_le64(nb_numa_nodes); 642 for (i = 0; i < max_cpus; i++) { 643 unsigned int apic_id = x86_cpu_apic_id_from_index(i); 644 assert(apic_id < apic_id_limit); 645 for (j = 0; j < nb_numa_nodes; j++) { 646 if (test_bit(i, node_cpumask[j])) { 647 numa_fw_cfg[apic_id + 1] = cpu_to_le64(j); 648 break; 649 } 650 } 651 } 652 for (i = 0; i < nb_numa_nodes; i++) { 653 numa_fw_cfg[apic_id_limit + 1 + i] = cpu_to_le64(node_mem[i]); 654 } 655 fw_cfg_add_bytes(fw_cfg, FW_CFG_NUMA, numa_fw_cfg, 656 (1 + apic_id_limit + nb_numa_nodes) * 657 sizeof(*numa_fw_cfg)); 658 659 return fw_cfg; 660 } 661 662 static long get_file_size(FILE *f) 663 { 664 long where, size; 665 666 /* XXX: on Unix systems, using fstat() probably makes more sense */ 667 668 where = ftell(f); 669 fseek(f, 0, SEEK_END); 670 size = ftell(f); 671 fseek(f, where, SEEK_SET); 672 673 return size; 674 } 675 676 static void load_linux(void *fw_cfg, 677 const char *kernel_filename, 678 const char *initrd_filename, 679 const char *kernel_cmdline, 680 hwaddr max_ram_size) 681 { 682 uint16_t protocol; 683 int setup_size, kernel_size, initrd_size = 0, cmdline_size; 684 uint32_t initrd_max; 685 uint8_t header[8192], *setup, *kernel, *initrd_data; 686 hwaddr real_addr, prot_addr, cmdline_addr, initrd_addr = 0; 687 FILE *f; 688 char *vmode; 689 690 /* Align to 16 bytes as a paranoia measure */ 691 cmdline_size = (strlen(kernel_cmdline)+16) & ~15; 692 693 /* load the kernel header */ 694 f = fopen(kernel_filename, "rb"); 695 if (!f || !(kernel_size = get_file_size(f)) || 696 fread(header, 1, MIN(ARRAY_SIZE(header), kernel_size), f) != 697 MIN(ARRAY_SIZE(header), kernel_size)) { 698 fprintf(stderr, "qemu: could not load kernel '%s': %s\n", 699 kernel_filename, strerror(errno)); 700 exit(1); 701 } 702 703 /* kernel protocol version */ 704 #if 0 705 fprintf(stderr, "header magic: %#x\n", ldl_p(header+0x202)); 706 #endif 707 if (ldl_p(header+0x202) == 0x53726448) { 708 protocol = lduw_p(header+0x206); 709 } else { 710 /* This looks like a multiboot kernel. If it is, let's stop 711 treating it like a Linux kernel. */ 712 if (load_multiboot(fw_cfg, f, kernel_filename, initrd_filename, 713 kernel_cmdline, kernel_size, header)) { 714 return; 715 } 716 protocol = 0; 717 } 718 719 if (protocol < 0x200 || !(header[0x211] & 0x01)) { 720 /* Low kernel */ 721 real_addr = 0x90000; 722 cmdline_addr = 0x9a000 - cmdline_size; 723 prot_addr = 0x10000; 724 } else if (protocol < 0x202) { 725 /* High but ancient kernel */ 726 real_addr = 0x90000; 727 cmdline_addr = 0x9a000 - cmdline_size; 728 prot_addr = 0x100000; 729 } else { 730 /* High and recent kernel */ 731 real_addr = 0x10000; 732 cmdline_addr = 0x20000; 733 prot_addr = 0x100000; 734 } 735 736 #if 0 737 fprintf(stderr, 738 "qemu: real_addr = 0x" TARGET_FMT_plx "\n" 739 "qemu: cmdline_addr = 0x" TARGET_FMT_plx "\n" 740 "qemu: prot_addr = 0x" TARGET_FMT_plx "\n", 741 real_addr, 742 cmdline_addr, 743 prot_addr); 744 #endif 745 746 /* highest address for loading the initrd */ 747 if (protocol >= 0x203) { 748 initrd_max = ldl_p(header+0x22c); 749 } else { 750 initrd_max = 0x37ffffff; 751 } 752 753 if (initrd_max >= max_ram_size-ACPI_DATA_SIZE) 754 initrd_max = max_ram_size-ACPI_DATA_SIZE-1; 755 756 fw_cfg_add_i32(fw_cfg, FW_CFG_CMDLINE_ADDR, cmdline_addr); 757 fw_cfg_add_i32(fw_cfg, FW_CFG_CMDLINE_SIZE, strlen(kernel_cmdline)+1); 758 fw_cfg_add_string(fw_cfg, FW_CFG_CMDLINE_DATA, kernel_cmdline); 759 760 if (protocol >= 0x202) { 761 stl_p(header+0x228, cmdline_addr); 762 } else { 763 stw_p(header+0x20, 0xA33F); 764 stw_p(header+0x22, cmdline_addr-real_addr); 765 } 766 767 /* handle vga= parameter */ 768 vmode = strstr(kernel_cmdline, "vga="); 769 if (vmode) { 770 unsigned int video_mode; 771 /* skip "vga=" */ 772 vmode += 4; 773 if (!strncmp(vmode, "normal", 6)) { 774 video_mode = 0xffff; 775 } else if (!strncmp(vmode, "ext", 3)) { 776 video_mode = 0xfffe; 777 } else if (!strncmp(vmode, "ask", 3)) { 778 video_mode = 0xfffd; 779 } else { 780 video_mode = strtol(vmode, NULL, 0); 781 } 782 stw_p(header+0x1fa, video_mode); 783 } 784 785 /* loader type */ 786 /* High nybble = B reserved for QEMU; low nybble is revision number. 787 If this code is substantially changed, you may want to consider 788 incrementing the revision. */ 789 if (protocol >= 0x200) { 790 header[0x210] = 0xB0; 791 } 792 /* heap */ 793 if (protocol >= 0x201) { 794 header[0x211] |= 0x80; /* CAN_USE_HEAP */ 795 stw_p(header+0x224, cmdline_addr-real_addr-0x200); 796 } 797 798 /* load initrd */ 799 if (initrd_filename) { 800 if (protocol < 0x200) { 801 fprintf(stderr, "qemu: linux kernel too old to load a ram disk\n"); 802 exit(1); 803 } 804 805 initrd_size = get_image_size(initrd_filename); 806 if (initrd_size < 0) { 807 fprintf(stderr, "qemu: error reading initrd %s\n", 808 initrd_filename); 809 exit(1); 810 } 811 812 initrd_addr = (initrd_max-initrd_size) & ~4095; 813 814 initrd_data = g_malloc(initrd_size); 815 load_image(initrd_filename, initrd_data); 816 817 fw_cfg_add_i32(fw_cfg, FW_CFG_INITRD_ADDR, initrd_addr); 818 fw_cfg_add_i32(fw_cfg, FW_CFG_INITRD_SIZE, initrd_size); 819 fw_cfg_add_bytes(fw_cfg, FW_CFG_INITRD_DATA, initrd_data, initrd_size); 820 821 stl_p(header+0x218, initrd_addr); 822 stl_p(header+0x21c, initrd_size); 823 } 824 825 /* load kernel and setup */ 826 setup_size = header[0x1f1]; 827 if (setup_size == 0) { 828 setup_size = 4; 829 } 830 setup_size = (setup_size+1)*512; 831 kernel_size -= setup_size; 832 833 setup = g_malloc(setup_size); 834 kernel = g_malloc(kernel_size); 835 fseek(f, 0, SEEK_SET); 836 if (fread(setup, 1, setup_size, f) != setup_size) { 837 fprintf(stderr, "fread() failed\n"); 838 exit(1); 839 } 840 if (fread(kernel, 1, kernel_size, f) != kernel_size) { 841 fprintf(stderr, "fread() failed\n"); 842 exit(1); 843 } 844 fclose(f); 845 memcpy(setup, header, MIN(sizeof(header), setup_size)); 846 847 fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_ADDR, prot_addr); 848 fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_SIZE, kernel_size); 849 fw_cfg_add_bytes(fw_cfg, FW_CFG_KERNEL_DATA, kernel, kernel_size); 850 851 fw_cfg_add_i32(fw_cfg, FW_CFG_SETUP_ADDR, real_addr); 852 fw_cfg_add_i32(fw_cfg, FW_CFG_SETUP_SIZE, setup_size); 853 fw_cfg_add_bytes(fw_cfg, FW_CFG_SETUP_DATA, setup, setup_size); 854 855 option_rom[nb_option_roms].name = "linuxboot.bin"; 856 option_rom[nb_option_roms].bootindex = 0; 857 nb_option_roms++; 858 } 859 860 #define NE2000_NB_MAX 6 861 862 static const int ne2000_io[NE2000_NB_MAX] = { 0x300, 0x320, 0x340, 0x360, 863 0x280, 0x380 }; 864 static const int ne2000_irq[NE2000_NB_MAX] = { 9, 10, 11, 3, 4, 5 }; 865 866 static const int parallel_io[MAX_PARALLEL_PORTS] = { 0x378, 0x278, 0x3bc }; 867 static const int parallel_irq[MAX_PARALLEL_PORTS] = { 7, 7, 7 }; 868 869 void pc_init_ne2k_isa(ISABus *bus, NICInfo *nd) 870 { 871 static int nb_ne2k = 0; 872 873 if (nb_ne2k == NE2000_NB_MAX) 874 return; 875 isa_ne2000_init(bus, ne2000_io[nb_ne2k], 876 ne2000_irq[nb_ne2k], nd); 877 nb_ne2k++; 878 } 879 880 DeviceState *cpu_get_current_apic(void) 881 { 882 if (cpu_single_env) { 883 return cpu_single_env->apic_state; 884 } else { 885 return NULL; 886 } 887 } 888 889 void pc_acpi_smi_interrupt(void *opaque, int irq, int level) 890 { 891 X86CPU *cpu = opaque; 892 893 if (level) { 894 cpu_interrupt(CPU(cpu), CPU_INTERRUPT_SMI); 895 } 896 } 897 898 static X86CPU *pc_new_cpu(const char *cpu_model, int64_t apic_id, 899 DeviceState *icc_bridge, Error **errp) 900 { 901 X86CPU *cpu; 902 Error *local_err = NULL; 903 904 cpu = cpu_x86_create(cpu_model, icc_bridge, errp); 905 if (!cpu) { 906 return cpu; 907 } 908 909 object_property_set_int(OBJECT(cpu), apic_id, "apic-id", &local_err); 910 object_property_set_bool(OBJECT(cpu), true, "realized", &local_err); 911 912 if (local_err) { 913 if (cpu != NULL) { 914 object_unref(OBJECT(cpu)); 915 cpu = NULL; 916 } 917 error_propagate(errp, local_err); 918 } 919 return cpu; 920 } 921 922 void pc_cpus_init(const char *cpu_model, DeviceState *icc_bridge) 923 { 924 int i; 925 X86CPU *cpu = NULL; 926 Error *error = NULL; 927 928 /* init CPUs */ 929 if (cpu_model == NULL) { 930 #ifdef TARGET_X86_64 931 cpu_model = "qemu64"; 932 #else 933 cpu_model = "qemu32"; 934 #endif 935 } 936 937 for (i = 0; i < smp_cpus; i++) { 938 cpu = pc_new_cpu(cpu_model, x86_cpu_apic_id_from_index(i), 939 icc_bridge, &error); 940 if (error) { 941 fprintf(stderr, "%s\n", error_get_pretty(error)); 942 error_free(error); 943 exit(1); 944 } 945 } 946 947 /* map APIC MMIO area if CPU has APIC */ 948 if (cpu && cpu->env.apic_state) { 949 /* XXX: what if the base changes? */ 950 sysbus_mmio_map_overlap(SYS_BUS_DEVICE(icc_bridge), 0, 951 APIC_DEFAULT_ADDRESS, 0x1000); 952 } 953 } 954 955 void pc_acpi_init(const char *default_dsdt) 956 { 957 char *filename; 958 959 if (acpi_tables != NULL) { 960 /* manually set via -acpitable, leave it alone */ 961 return; 962 } 963 964 filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, default_dsdt); 965 if (filename == NULL) { 966 fprintf(stderr, "WARNING: failed to find %s\n", default_dsdt); 967 } else { 968 char *arg; 969 QemuOpts *opts; 970 Error *err = NULL; 971 972 arg = g_strdup_printf("file=%s", filename); 973 974 /* creates a deep copy of "arg" */ 975 opts = qemu_opts_parse(qemu_find_opts("acpi"), arg, 0); 976 g_assert(opts != NULL); 977 978 acpi_table_add(opts, &err); 979 if (err) { 980 fprintf(stderr, "WARNING: failed to load %s: %s\n", filename, 981 error_get_pretty(err)); 982 error_free(err); 983 } 984 g_free(arg); 985 g_free(filename); 986 } 987 } 988 989 void *pc_memory_init(MemoryRegion *system_memory, 990 const char *kernel_filename, 991 const char *kernel_cmdline, 992 const char *initrd_filename, 993 ram_addr_t below_4g_mem_size, 994 ram_addr_t above_4g_mem_size, 995 MemoryRegion *rom_memory, 996 MemoryRegion **ram_memory) 997 { 998 int linux_boot, i; 999 MemoryRegion *ram, *option_rom_mr; 1000 MemoryRegion *ram_below_4g, *ram_above_4g; 1001 void *fw_cfg; 1002 1003 linux_boot = (kernel_filename != NULL); 1004 1005 /* Allocate RAM. We allocate it as a single memory region and use 1006 * aliases to address portions of it, mostly for backwards compatibility 1007 * with older qemus that used qemu_ram_alloc(). 1008 */ 1009 ram = g_malloc(sizeof(*ram)); 1010 memory_region_init_ram(ram, "pc.ram", 1011 below_4g_mem_size + above_4g_mem_size); 1012 vmstate_register_ram_global(ram); 1013 *ram_memory = ram; 1014 ram_below_4g = g_malloc(sizeof(*ram_below_4g)); 1015 memory_region_init_alias(ram_below_4g, "ram-below-4g", ram, 1016 0, below_4g_mem_size); 1017 memory_region_add_subregion(system_memory, 0, ram_below_4g); 1018 if (above_4g_mem_size > 0) { 1019 ram_above_4g = g_malloc(sizeof(*ram_above_4g)); 1020 memory_region_init_alias(ram_above_4g, "ram-above-4g", ram, 1021 below_4g_mem_size, above_4g_mem_size); 1022 memory_region_add_subregion(system_memory, 0x100000000ULL, 1023 ram_above_4g); 1024 } 1025 1026 1027 /* Initialize PC system firmware */ 1028 pc_system_firmware_init(rom_memory); 1029 1030 option_rom_mr = g_malloc(sizeof(*option_rom_mr)); 1031 memory_region_init_ram(option_rom_mr, "pc.rom", PC_ROM_SIZE); 1032 vmstate_register_ram_global(option_rom_mr); 1033 memory_region_add_subregion_overlap(rom_memory, 1034 PC_ROM_MIN_VGA, 1035 option_rom_mr, 1036 1); 1037 1038 fw_cfg = bochs_bios_init(); 1039 rom_set_fw(fw_cfg); 1040 1041 if (linux_boot) { 1042 load_linux(fw_cfg, kernel_filename, initrd_filename, kernel_cmdline, below_4g_mem_size); 1043 } 1044 1045 for (i = 0; i < nb_option_roms; i++) { 1046 rom_add_option(option_rom[i].name, option_rom[i].bootindex); 1047 } 1048 return fw_cfg; 1049 } 1050 1051 qemu_irq *pc_allocate_cpu_irq(void) 1052 { 1053 return qemu_allocate_irqs(pic_irq_request, NULL, 1); 1054 } 1055 1056 DeviceState *pc_vga_init(ISABus *isa_bus, PCIBus *pci_bus) 1057 { 1058 DeviceState *dev = NULL; 1059 1060 if (pci_bus) { 1061 PCIDevice *pcidev = pci_vga_init(pci_bus); 1062 dev = pcidev ? &pcidev->qdev : NULL; 1063 } else if (isa_bus) { 1064 ISADevice *isadev = isa_vga_init(isa_bus); 1065 dev = isadev ? &isadev->qdev : NULL; 1066 } 1067 return dev; 1068 } 1069 1070 static void cpu_request_exit(void *opaque, int irq, int level) 1071 { 1072 CPUX86State *env = cpu_single_env; 1073 1074 if (env && level) { 1075 cpu_exit(env); 1076 } 1077 } 1078 1079 static const MemoryRegionOps ioport80_io_ops = { 1080 .write = ioport80_write, 1081 .read = ioport80_read, 1082 .endianness = DEVICE_NATIVE_ENDIAN, 1083 .impl = { 1084 .min_access_size = 1, 1085 .max_access_size = 1, 1086 }, 1087 }; 1088 1089 static const MemoryRegionOps ioportF0_io_ops = { 1090 .write = ioportF0_write, 1091 .read = ioportF0_read, 1092 .endianness = DEVICE_NATIVE_ENDIAN, 1093 .impl = { 1094 .min_access_size = 1, 1095 .max_access_size = 1, 1096 }, 1097 }; 1098 1099 void pc_basic_device_init(ISABus *isa_bus, qemu_irq *gsi, 1100 ISADevice **rtc_state, 1101 ISADevice **floppy, 1102 bool no_vmport) 1103 { 1104 int i; 1105 DriveInfo *fd[MAX_FD]; 1106 DeviceState *hpet = NULL; 1107 int pit_isa_irq = 0; 1108 qemu_irq pit_alt_irq = NULL; 1109 qemu_irq rtc_irq = NULL; 1110 qemu_irq *a20_line; 1111 ISADevice *i8042, *port92, *vmmouse, *pit = NULL; 1112 qemu_irq *cpu_exit_irq; 1113 MemoryRegion *ioport80_io = g_new(MemoryRegion, 1); 1114 MemoryRegion *ioportF0_io = g_new(MemoryRegion, 1); 1115 1116 memory_region_init_io(ioport80_io, &ioport80_io_ops, NULL, "ioport80", 1); 1117 memory_region_add_subregion(isa_bus->address_space_io, 0x80, ioport80_io); 1118 1119 memory_region_init_io(ioportF0_io, &ioportF0_io_ops, NULL, "ioportF0", 1); 1120 memory_region_add_subregion(isa_bus->address_space_io, 0xf0, ioportF0_io); 1121 1122 /* 1123 * Check if an HPET shall be created. 1124 * 1125 * Without KVM_CAP_PIT_STATE2, we cannot switch off the in-kernel PIT 1126 * when the HPET wants to take over. Thus we have to disable the latter. 1127 */ 1128 if (!no_hpet && (!kvm_irqchip_in_kernel() || kvm_has_pit_state2())) { 1129 hpet = sysbus_try_create_simple("hpet", HPET_BASE, NULL); 1130 1131 if (hpet) { 1132 for (i = 0; i < GSI_NUM_PINS; i++) { 1133 sysbus_connect_irq(SYS_BUS_DEVICE(hpet), i, gsi[i]); 1134 } 1135 pit_isa_irq = -1; 1136 pit_alt_irq = qdev_get_gpio_in(hpet, HPET_LEGACY_PIT_INT); 1137 rtc_irq = qdev_get_gpio_in(hpet, HPET_LEGACY_RTC_INT); 1138 } 1139 } 1140 *rtc_state = rtc_init(isa_bus, 2000, rtc_irq); 1141 1142 qemu_register_boot_set(pc_boot_set, *rtc_state); 1143 1144 if (!xen_enabled()) { 1145 if (kvm_irqchip_in_kernel()) { 1146 pit = kvm_pit_init(isa_bus, 0x40); 1147 } else { 1148 pit = pit_init(isa_bus, 0x40, pit_isa_irq, pit_alt_irq); 1149 } 1150 if (hpet) { 1151 /* connect PIT to output control line of the HPET */ 1152 qdev_connect_gpio_out(hpet, 0, qdev_get_gpio_in(&pit->qdev, 0)); 1153 } 1154 pcspk_init(isa_bus, pit); 1155 } 1156 1157 for(i = 0; i < MAX_SERIAL_PORTS; i++) { 1158 if (serial_hds[i]) { 1159 serial_isa_init(isa_bus, i, serial_hds[i]); 1160 } 1161 } 1162 1163 for(i = 0; i < MAX_PARALLEL_PORTS; i++) { 1164 if (parallel_hds[i]) { 1165 parallel_init(isa_bus, i, parallel_hds[i]); 1166 } 1167 } 1168 1169 a20_line = qemu_allocate_irqs(handle_a20_line_change, 1170 x86_env_get_cpu(first_cpu), 2); 1171 i8042 = isa_create_simple(isa_bus, "i8042"); 1172 i8042_setup_a20_line(i8042, &a20_line[0]); 1173 if (!no_vmport) { 1174 vmport_init(isa_bus); 1175 vmmouse = isa_try_create(isa_bus, "vmmouse"); 1176 } else { 1177 vmmouse = NULL; 1178 } 1179 if (vmmouse) { 1180 qdev_prop_set_ptr(&vmmouse->qdev, "ps2_mouse", i8042); 1181 qdev_init_nofail(&vmmouse->qdev); 1182 } 1183 port92 = isa_create_simple(isa_bus, "port92"); 1184 port92_init(port92, &a20_line[1]); 1185 1186 cpu_exit_irq = qemu_allocate_irqs(cpu_request_exit, NULL, 1); 1187 DMA_init(0, cpu_exit_irq); 1188 1189 for(i = 0; i < MAX_FD; i++) { 1190 fd[i] = drive_get(IF_FLOPPY, 0, i); 1191 } 1192 *floppy = fdctrl_init_isa(isa_bus, fd); 1193 } 1194 1195 void pc_nic_init(ISABus *isa_bus, PCIBus *pci_bus) 1196 { 1197 int i; 1198 1199 for (i = 0; i < nb_nics; i++) { 1200 NICInfo *nd = &nd_table[i]; 1201 1202 if (!pci_bus || (nd->model && strcmp(nd->model, "ne2k_isa") == 0)) { 1203 pc_init_ne2k_isa(isa_bus, nd); 1204 } else { 1205 pci_nic_init_nofail(nd, "e1000", NULL); 1206 } 1207 } 1208 } 1209 1210 void pc_pci_device_init(PCIBus *pci_bus) 1211 { 1212 int max_bus; 1213 int bus; 1214 1215 max_bus = drive_get_max_bus(IF_SCSI); 1216 for (bus = 0; bus <= max_bus; bus++) { 1217 pci_create_simple(pci_bus, -1, "lsi53c895a"); 1218 } 1219 } 1220 1221 void ioapic_init_gsi(GSIState *gsi_state, const char *parent_name) 1222 { 1223 DeviceState *dev; 1224 SysBusDevice *d; 1225 unsigned int i; 1226 1227 if (kvm_irqchip_in_kernel()) { 1228 dev = qdev_create(NULL, "kvm-ioapic"); 1229 } else { 1230 dev = qdev_create(NULL, "ioapic"); 1231 } 1232 if (parent_name) { 1233 object_property_add_child(object_resolve_path(parent_name, NULL), 1234 "ioapic", OBJECT(dev), NULL); 1235 } 1236 qdev_init_nofail(dev); 1237 d = SYS_BUS_DEVICE(dev); 1238 sysbus_mmio_map(d, 0, IO_APIC_DEFAULT_ADDRESS); 1239 1240 for (i = 0; i < IOAPIC_NUM_PINS; i++) { 1241 gsi_state->ioapic_irq[i] = qdev_get_gpio_in(dev, i); 1242 } 1243 } 1244