1 /* 2 * QEMU PC System Emulator 3 * 4 * Copyright (c) 2003-2004 Fabrice Bellard 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a copy 7 * of this software and associated documentation files (the "Software"), to deal 8 * in the Software without restriction, including without limitation the rights 9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 10 * copies of the Software, and to permit persons to whom the Software is 11 * furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice shall be included in 14 * all copies or substantial portions of the Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN 22 * THE SOFTWARE. 23 */ 24 25 #include "qemu/osdep.h" 26 #include "qemu/units.h" 27 #include "hw/i386/pc.h" 28 #include "hw/char/serial-isa.h" 29 #include "hw/char/parallel.h" 30 #include "hw/hyperv/hv-balloon.h" 31 #include "hw/i386/fw_cfg.h" 32 #include "hw/i386/vmport.h" 33 #include "system/cpus.h" 34 #include "hw/ide/ide-bus.h" 35 #include "hw/timer/hpet.h" 36 #include "hw/loader.h" 37 #include "hw/rtc/mc146818rtc.h" 38 #include "hw/intc/i8259.h" 39 #include "hw/timer/i8254.h" 40 #include "hw/input/i8042.h" 41 #include "hw/audio/pcspk.h" 42 #include "system/system.h" 43 #include "system/xen.h" 44 #include "system/reset.h" 45 #include "kvm/kvm_i386.h" 46 #include "hw/xen/xen.h" 47 #include "qobject/qlist.h" 48 #include "qemu/error-report.h" 49 #include "hw/acpi/cpu_hotplug.h" 50 #include "acpi-build.h" 51 #include "hw/mem/nvdimm.h" 52 #include "hw/cxl/cxl_host.h" 53 #include "hw/usb.h" 54 #include "hw/i386/intel_iommu.h" 55 #include "hw/net/ne2000-isa.h" 56 #include "hw/virtio/virtio-iommu.h" 57 #include "hw/virtio/virtio-md-pci.h" 58 #include "hw/i386/kvm/xen_overlay.h" 59 #include "hw/i386/kvm/xen_evtchn.h" 60 #include "hw/i386/kvm/xen_gnttab.h" 61 #include "hw/i386/kvm/xen_xenstore.h" 62 #include "hw/mem/memory-device.h" 63 #include "e820_memory_layout.h" 64 #include "trace.h" 65 #include "sev.h" 66 #include CONFIG_DEVICES 67 68 #ifdef CONFIG_XEN_EMU 69 #include "hw/xen/xen-legacy-backend.h" 70 #include "hw/xen/xen-bus.h" 71 #endif 72 73 /* 74 * Helper for setting model-id for CPU models that changed model-id 75 * depending on QEMU versions up to QEMU 2.4. 76 */ 77 #define PC_CPU_MODEL_IDS(v) \ 78 { "qemu32-" TYPE_X86_CPU, "model-id", "QEMU Virtual CPU version " v, },\ 79 { "qemu64-" TYPE_X86_CPU, "model-id", "QEMU Virtual CPU version " v, },\ 80 { "athlon-" TYPE_X86_CPU, "model-id", "QEMU Virtual CPU version " v, }, 81 82 GlobalProperty pc_compat_9_2[] = {}; 83 const size_t pc_compat_9_2_len = G_N_ELEMENTS(pc_compat_9_2); 84 85 GlobalProperty pc_compat_9_1[] = { 86 { "ICH9-LPC", "x-smi-swsmi-timer", "off" }, 87 { "ICH9-LPC", "x-smi-periodic-timer", "off" }, 88 { TYPE_INTEL_IOMMU_DEVICE, "stale-tm", "on" }, 89 { TYPE_INTEL_IOMMU_DEVICE, "aw-bits", "39" }, 90 }; 91 const size_t pc_compat_9_1_len = G_N_ELEMENTS(pc_compat_9_1); 92 93 GlobalProperty pc_compat_9_0[] = { 94 { TYPE_X86_CPU, "x-amd-topoext-features-only", "false" }, 95 { TYPE_X86_CPU, "x-l1-cache-per-thread", "false" }, 96 { TYPE_X86_CPU, "guest-phys-bits", "0" }, 97 { "sev-guest", "legacy-vm-type", "on" }, 98 { TYPE_X86_CPU, "legacy-multi-node", "on" }, 99 }; 100 const size_t pc_compat_9_0_len = G_N_ELEMENTS(pc_compat_9_0); 101 102 GlobalProperty pc_compat_8_2[] = {}; 103 const size_t pc_compat_8_2_len = G_N_ELEMENTS(pc_compat_8_2); 104 105 GlobalProperty pc_compat_8_1[] = {}; 106 const size_t pc_compat_8_1_len = G_N_ELEMENTS(pc_compat_8_1); 107 108 GlobalProperty pc_compat_8_0[] = { 109 { "virtio-mem", "unplugged-inaccessible", "auto" }, 110 }; 111 const size_t pc_compat_8_0_len = G_N_ELEMENTS(pc_compat_8_0); 112 113 GlobalProperty pc_compat_7_2[] = { 114 { "ICH9-LPC", "noreboot", "true" }, 115 }; 116 const size_t pc_compat_7_2_len = G_N_ELEMENTS(pc_compat_7_2); 117 118 GlobalProperty pc_compat_7_1[] = {}; 119 const size_t pc_compat_7_1_len = G_N_ELEMENTS(pc_compat_7_1); 120 121 GlobalProperty pc_compat_7_0[] = {}; 122 const size_t pc_compat_7_0_len = G_N_ELEMENTS(pc_compat_7_0); 123 124 GlobalProperty pc_compat_6_2[] = { 125 { "virtio-mem", "unplugged-inaccessible", "off" }, 126 }; 127 const size_t pc_compat_6_2_len = G_N_ELEMENTS(pc_compat_6_2); 128 129 GlobalProperty pc_compat_6_1[] = { 130 { TYPE_X86_CPU, "hv-version-id-build", "0x1bbc" }, 131 { TYPE_X86_CPU, "hv-version-id-major", "0x0006" }, 132 { TYPE_X86_CPU, "hv-version-id-minor", "0x0001" }, 133 { "ICH9-LPC", "x-keep-pci-slot-hpc", "false" }, 134 }; 135 const size_t pc_compat_6_1_len = G_N_ELEMENTS(pc_compat_6_1); 136 137 GlobalProperty pc_compat_6_0[] = { 138 { "qemu64" "-" TYPE_X86_CPU, "family", "6" }, 139 { "qemu64" "-" TYPE_X86_CPU, "model", "6" }, 140 { "qemu64" "-" TYPE_X86_CPU, "stepping", "3" }, 141 { TYPE_X86_CPU, "x-vendor-cpuid-only", "off" }, 142 { "ICH9-LPC", ACPI_PM_PROP_ACPI_PCIHP_BRIDGE, "off" }, 143 { "ICH9-LPC", "x-keep-pci-slot-hpc", "true" }, 144 }; 145 const size_t pc_compat_6_0_len = G_N_ELEMENTS(pc_compat_6_0); 146 147 GlobalProperty pc_compat_5_2[] = { 148 { "ICH9-LPC", "x-smi-cpu-hotunplug", "off" }, 149 }; 150 const size_t pc_compat_5_2_len = G_N_ELEMENTS(pc_compat_5_2); 151 152 GlobalProperty pc_compat_5_1[] = { 153 { "ICH9-LPC", "x-smi-cpu-hotplug", "off" }, 154 { TYPE_X86_CPU, "kvm-msi-ext-dest-id", "off" }, 155 }; 156 const size_t pc_compat_5_1_len = G_N_ELEMENTS(pc_compat_5_1); 157 158 GlobalProperty pc_compat_5_0[] = { 159 }; 160 const size_t pc_compat_5_0_len = G_N_ELEMENTS(pc_compat_5_0); 161 162 GlobalProperty pc_compat_4_2[] = { 163 { "mch", "smbase-smram", "off" }, 164 }; 165 const size_t pc_compat_4_2_len = G_N_ELEMENTS(pc_compat_4_2); 166 167 GlobalProperty pc_compat_4_1[] = {}; 168 const size_t pc_compat_4_1_len = G_N_ELEMENTS(pc_compat_4_1); 169 170 GlobalProperty pc_compat_4_0[] = {}; 171 const size_t pc_compat_4_0_len = G_N_ELEMENTS(pc_compat_4_0); 172 173 GlobalProperty pc_compat_3_1[] = { 174 { "intel-iommu", "dma-drain", "off" }, 175 { "Opteron_G3" "-" TYPE_X86_CPU, "rdtscp", "off" }, 176 { "Opteron_G4" "-" TYPE_X86_CPU, "rdtscp", "off" }, 177 { "Opteron_G4" "-" TYPE_X86_CPU, "npt", "off" }, 178 { "Opteron_G4" "-" TYPE_X86_CPU, "nrip-save", "off" }, 179 { "Opteron_G5" "-" TYPE_X86_CPU, "rdtscp", "off" }, 180 { "Opteron_G5" "-" TYPE_X86_CPU, "npt", "off" }, 181 { "Opteron_G5" "-" TYPE_X86_CPU, "nrip-save", "off" }, 182 { "EPYC" "-" TYPE_X86_CPU, "npt", "off" }, 183 { "EPYC" "-" TYPE_X86_CPU, "nrip-save", "off" }, 184 { "EPYC-IBPB" "-" TYPE_X86_CPU, "npt", "off" }, 185 { "EPYC-IBPB" "-" TYPE_X86_CPU, "nrip-save", "off" }, 186 { "Skylake-Client" "-" TYPE_X86_CPU, "mpx", "on" }, 187 { "Skylake-Client-IBRS" "-" TYPE_X86_CPU, "mpx", "on" }, 188 { "Skylake-Server" "-" TYPE_X86_CPU, "mpx", "on" }, 189 { "Skylake-Server-IBRS" "-" TYPE_X86_CPU, "mpx", "on" }, 190 { "Cascadelake-Server" "-" TYPE_X86_CPU, "mpx", "on" }, 191 { "Icelake-Client" "-" TYPE_X86_CPU, "mpx", "on" }, 192 { "Icelake-Server" "-" TYPE_X86_CPU, "mpx", "on" }, 193 { "Cascadelake-Server" "-" TYPE_X86_CPU, "stepping", "5" }, 194 { TYPE_X86_CPU, "x-intel-pt-auto-level", "off" }, 195 }; 196 const size_t pc_compat_3_1_len = G_N_ELEMENTS(pc_compat_3_1); 197 198 GlobalProperty pc_compat_3_0[] = { 199 { TYPE_X86_CPU, "x-hv-synic-kvm-only", "on" }, 200 { "Skylake-Server" "-" TYPE_X86_CPU, "pku", "off" }, 201 { "Skylake-Server-IBRS" "-" TYPE_X86_CPU, "pku", "off" }, 202 }; 203 const size_t pc_compat_3_0_len = G_N_ELEMENTS(pc_compat_3_0); 204 205 GlobalProperty pc_compat_2_12[] = { 206 { TYPE_X86_CPU, "legacy-cache", "on" }, 207 { TYPE_X86_CPU, "topoext", "off" }, 208 { "EPYC-" TYPE_X86_CPU, "xlevel", "0x8000000a" }, 209 { "EPYC-IBPB-" TYPE_X86_CPU, "xlevel", "0x8000000a" }, 210 }; 211 const size_t pc_compat_2_12_len = G_N_ELEMENTS(pc_compat_2_12); 212 213 GlobalProperty pc_compat_2_11[] = { 214 { TYPE_X86_CPU, "x-migrate-smi-count", "off" }, 215 { "Skylake-Server" "-" TYPE_X86_CPU, "clflushopt", "off" }, 216 }; 217 const size_t pc_compat_2_11_len = G_N_ELEMENTS(pc_compat_2_11); 218 219 GlobalProperty pc_compat_2_10[] = { 220 { TYPE_X86_CPU, "x-hv-max-vps", "0x40" }, 221 { "i440FX-pcihost", "x-pci-hole64-fix", "off" }, 222 { "q35-pcihost", "x-pci-hole64-fix", "off" }, 223 }; 224 const size_t pc_compat_2_10_len = G_N_ELEMENTS(pc_compat_2_10); 225 226 GlobalProperty pc_compat_2_9[] = { 227 { "mch", "extended-tseg-mbytes", "0" }, 228 }; 229 const size_t pc_compat_2_9_len = G_N_ELEMENTS(pc_compat_2_9); 230 231 GlobalProperty pc_compat_2_8[] = { 232 { TYPE_X86_CPU, "tcg-cpuid", "off" }, 233 { "kvmclock", "x-mach-use-reliable-get-clock", "off" }, 234 { "ICH9-LPC", "x-smi-broadcast", "off" }, 235 { TYPE_X86_CPU, "vmware-cpuid-freq", "off" }, 236 { "Haswell-" TYPE_X86_CPU, "stepping", "1" }, 237 }; 238 const size_t pc_compat_2_8_len = G_N_ELEMENTS(pc_compat_2_8); 239 240 GlobalProperty pc_compat_2_7[] = { 241 { TYPE_X86_CPU, "l3-cache", "off" }, 242 { TYPE_X86_CPU, "full-cpuid-auto-level", "off" }, 243 { "Opteron_G3" "-" TYPE_X86_CPU, "family", "15" }, 244 { "Opteron_G3" "-" TYPE_X86_CPU, "model", "6" }, 245 { "Opteron_G3" "-" TYPE_X86_CPU, "stepping", "1" }, 246 { "isa-pcspk", "migrate", "off" }, 247 }; 248 const size_t pc_compat_2_7_len = G_N_ELEMENTS(pc_compat_2_7); 249 250 GlobalProperty pc_compat_2_6[] = { 251 { TYPE_X86_CPU, "cpuid-0xb", "off" }, 252 { "vmxnet3", "romfile", "" }, 253 { TYPE_X86_CPU, "fill-mtrr-mask", "off" }, 254 { "apic-common", "legacy-instance-id", "on", } 255 }; 256 const size_t pc_compat_2_6_len = G_N_ELEMENTS(pc_compat_2_6); 257 258 GlobalProperty pc_compat_2_5[] = {}; 259 const size_t pc_compat_2_5_len = G_N_ELEMENTS(pc_compat_2_5); 260 261 GlobalProperty pc_compat_2_4[] = { 262 PC_CPU_MODEL_IDS("2.4.0") 263 { "Haswell-" TYPE_X86_CPU, "abm", "off" }, 264 { "Haswell-noTSX-" TYPE_X86_CPU, "abm", "off" }, 265 { "Broadwell-" TYPE_X86_CPU, "abm", "off" }, 266 { "Broadwell-noTSX-" TYPE_X86_CPU, "abm", "off" }, 267 { "host" "-" TYPE_X86_CPU, "host-cache-info", "on" }, 268 { TYPE_X86_CPU, "check", "off" }, 269 { "qemu64" "-" TYPE_X86_CPU, "sse4a", "on" }, 270 { "qemu64" "-" TYPE_X86_CPU, "abm", "on" }, 271 { "qemu64" "-" TYPE_X86_CPU, "popcnt", "on" }, 272 { "qemu32" "-" TYPE_X86_CPU, "popcnt", "on" }, 273 { "Opteron_G2" "-" TYPE_X86_CPU, "rdtscp", "on" }, 274 { "Opteron_G3" "-" TYPE_X86_CPU, "rdtscp", "on" }, 275 { "Opteron_G4" "-" TYPE_X86_CPU, "rdtscp", "on" }, 276 { "Opteron_G5" "-" TYPE_X86_CPU, "rdtscp", "on", } 277 }; 278 const size_t pc_compat_2_4_len = G_N_ELEMENTS(pc_compat_2_4); 279 280 /* 281 * @PC_FW_DATA: 282 * Size of the chunk of memory at the top of RAM for the BIOS ACPI tables 283 * and other BIOS datastructures. 284 * 285 * BIOS ACPI tables: 128K. Other BIOS datastructures: less than 4K 286 * reported to be used at the moment, 32K should be enough for a while. 287 */ 288 #define PC_FW_DATA (0x20000 + 0x8000) 289 290 GSIState *pc_gsi_create(qemu_irq **irqs, bool pci_enabled) 291 { 292 GSIState *s; 293 294 s = g_new0(GSIState, 1); 295 if (kvm_ioapic_in_kernel()) { 296 kvm_pc_setup_irq_routing(pci_enabled); 297 } 298 *irqs = qemu_allocate_irqs(gsi_handler, s, IOAPIC_NUM_PINS); 299 300 return s; 301 } 302 303 static void ioport80_write(void *opaque, hwaddr addr, uint64_t data, 304 unsigned size) 305 { 306 } 307 308 static uint64_t ioport80_read(void *opaque, hwaddr addr, unsigned size) 309 { 310 return 0xffffffffffffffffULL; 311 } 312 313 /* MS-DOS compatibility mode FPU exception support */ 314 static void ioportF0_write(void *opaque, hwaddr addr, uint64_t data, 315 unsigned size) 316 { 317 if (tcg_enabled()) { 318 cpu_set_ignne(); 319 } 320 } 321 322 static uint64_t ioportF0_read(void *opaque, hwaddr addr, unsigned size) 323 { 324 return 0xffffffffffffffffULL; 325 } 326 327 /* PC cmos mappings */ 328 329 #define REG_EQUIPMENT_BYTE 0x14 330 331 static void cmos_init_hd(MC146818RtcState *s, int type_ofs, int info_ofs, 332 int16_t cylinders, int8_t heads, int8_t sectors) 333 { 334 mc146818rtc_set_cmos_data(s, type_ofs, 47); 335 mc146818rtc_set_cmos_data(s, info_ofs, cylinders); 336 mc146818rtc_set_cmos_data(s, info_ofs + 1, cylinders >> 8); 337 mc146818rtc_set_cmos_data(s, info_ofs + 2, heads); 338 mc146818rtc_set_cmos_data(s, info_ofs + 3, 0xff); 339 mc146818rtc_set_cmos_data(s, info_ofs + 4, 0xff); 340 mc146818rtc_set_cmos_data(s, info_ofs + 5, 0xc0 | ((heads > 8) << 3)); 341 mc146818rtc_set_cmos_data(s, info_ofs + 6, cylinders); 342 mc146818rtc_set_cmos_data(s, info_ofs + 7, cylinders >> 8); 343 mc146818rtc_set_cmos_data(s, info_ofs + 8, sectors); 344 } 345 346 /* convert boot_device letter to something recognizable by the bios */ 347 static int boot_device2nibble(char boot_device) 348 { 349 switch(boot_device) { 350 case 'a': 351 case 'b': 352 return 0x01; /* floppy boot */ 353 case 'c': 354 return 0x02; /* hard drive boot */ 355 case 'd': 356 return 0x03; /* CD-ROM boot */ 357 case 'n': 358 return 0x04; /* Network boot */ 359 } 360 return 0; 361 } 362 363 static void set_boot_dev(PCMachineState *pcms, MC146818RtcState *s, 364 const char *boot_device, Error **errp) 365 { 366 #define PC_MAX_BOOT_DEVICES 3 367 int nbds, bds[3] = { 0, }; 368 int i; 369 370 nbds = strlen(boot_device); 371 if (nbds > PC_MAX_BOOT_DEVICES) { 372 error_setg(errp, "Too many boot devices for PC"); 373 return; 374 } 375 for (i = 0; i < nbds; i++) { 376 bds[i] = boot_device2nibble(boot_device[i]); 377 if (bds[i] == 0) { 378 error_setg(errp, "Invalid boot device for PC: '%c'", 379 boot_device[i]); 380 return; 381 } 382 } 383 mc146818rtc_set_cmos_data(s, 0x3d, (bds[1] << 4) | bds[0]); 384 mc146818rtc_set_cmos_data(s, 0x38, (bds[2] << 4) | !pcms->fd_bootchk); 385 } 386 387 static void pc_boot_set(void *opaque, const char *boot_device, Error **errp) 388 { 389 PCMachineState *pcms = opaque; 390 X86MachineState *x86ms = X86_MACHINE(pcms); 391 392 set_boot_dev(pcms, MC146818_RTC(x86ms->rtc), boot_device, errp); 393 } 394 395 static void pc_cmos_init_floppy(MC146818RtcState *rtc_state, ISADevice *floppy) 396 { 397 int val, nb; 398 FloppyDriveType fd_type[2] = { FLOPPY_DRIVE_TYPE_NONE, 399 FLOPPY_DRIVE_TYPE_NONE }; 400 401 #ifdef CONFIG_FDC_ISA 402 /* floppy type */ 403 if (floppy) { 404 for (int i = 0; i < 2; i++) { 405 fd_type[i] = isa_fdc_get_drive_type(floppy, i); 406 } 407 } 408 #endif 409 410 val = (cmos_get_fd_drive_type(fd_type[0]) << 4) | 411 cmos_get_fd_drive_type(fd_type[1]); 412 mc146818rtc_set_cmos_data(rtc_state, 0x10, val); 413 414 val = mc146818rtc_get_cmos_data(rtc_state, REG_EQUIPMENT_BYTE); 415 nb = 0; 416 if (fd_type[0] != FLOPPY_DRIVE_TYPE_NONE) { 417 nb++; 418 } 419 if (fd_type[1] != FLOPPY_DRIVE_TYPE_NONE) { 420 nb++; 421 } 422 switch (nb) { 423 case 0: 424 break; 425 case 1: 426 val |= 0x01; /* 1 drive, ready for boot */ 427 break; 428 case 2: 429 val |= 0x41; /* 2 drives, ready for boot */ 430 break; 431 } 432 mc146818rtc_set_cmos_data(rtc_state, REG_EQUIPMENT_BYTE, val); 433 } 434 435 typedef struct check_fdc_state { 436 ISADevice *floppy; 437 bool multiple; 438 } CheckFdcState; 439 440 static int check_fdc(Object *obj, void *opaque) 441 { 442 CheckFdcState *state = opaque; 443 Object *fdc; 444 uint32_t iobase; 445 Error *local_err = NULL; 446 447 fdc = object_dynamic_cast(obj, TYPE_ISA_FDC); 448 if (!fdc) { 449 return 0; 450 } 451 452 iobase = object_property_get_uint(obj, "iobase", &local_err); 453 if (local_err || iobase != 0x3f0) { 454 error_free(local_err); 455 return 0; 456 } 457 458 if (state->floppy) { 459 state->multiple = true; 460 } else { 461 state->floppy = ISA_DEVICE(obj); 462 } 463 return 0; 464 } 465 466 static const char * const fdc_container_path[] = { 467 "unattached", "peripheral", "peripheral-anon" 468 }; 469 470 /* 471 * Locate the FDC at IO address 0x3f0, in order to configure the CMOS registers 472 * and ACPI objects. 473 */ 474 static ISADevice *pc_find_fdc0(void) 475 { 476 int i; 477 Object *container; 478 CheckFdcState state = { 0 }; 479 480 for (i = 0; i < ARRAY_SIZE(fdc_container_path); i++) { 481 container = machine_get_container(fdc_container_path[i]); 482 object_child_foreach(container, check_fdc, &state); 483 } 484 485 if (state.multiple) { 486 warn_report("multiple floppy disk controllers with " 487 "iobase=0x3f0 have been found"); 488 error_printf("the one being picked for CMOS setup might not reflect " 489 "your intent"); 490 } 491 492 return state.floppy; 493 } 494 495 static void pc_cmos_init_late(PCMachineState *pcms) 496 { 497 X86MachineState *x86ms = X86_MACHINE(pcms); 498 MC146818RtcState *s = MC146818_RTC(x86ms->rtc); 499 int16_t cylinders; 500 int8_t heads, sectors; 501 int val; 502 int i, trans; 503 504 val = 0; 505 if (pcms->idebus[0] && 506 ide_get_geometry(pcms->idebus[0], 0, 507 &cylinders, &heads, §ors) >= 0) { 508 cmos_init_hd(s, 0x19, 0x1b, cylinders, heads, sectors); 509 val |= 0xf0; 510 } 511 if (pcms->idebus[0] && 512 ide_get_geometry(pcms->idebus[0], 1, 513 &cylinders, &heads, §ors) >= 0) { 514 cmos_init_hd(s, 0x1a, 0x24, cylinders, heads, sectors); 515 val |= 0x0f; 516 } 517 mc146818rtc_set_cmos_data(s, 0x12, val); 518 519 val = 0; 520 for (i = 0; i < 4; i++) { 521 /* NOTE: ide_get_geometry() returns the physical 522 geometry. It is always such that: 1 <= sects <= 63, 1 523 <= heads <= 16, 1 <= cylinders <= 16383. The BIOS 524 geometry can be different if a translation is done. */ 525 BusState *idebus = pcms->idebus[i / 2]; 526 if (idebus && 527 ide_get_geometry(idebus, i % 2, 528 &cylinders, &heads, §ors) >= 0) { 529 trans = ide_get_bios_chs_trans(idebus, i % 2) - 1; 530 assert((trans & ~3) == 0); 531 val |= trans << (i * 2); 532 } 533 } 534 mc146818rtc_set_cmos_data(s, 0x39, val); 535 536 pc_cmos_init_floppy(s, pc_find_fdc0()); 537 538 /* various important CMOS locations needed by PC/Bochs bios */ 539 540 /* memory size */ 541 /* base memory (first MiB) */ 542 val = MIN(x86ms->below_4g_mem_size / KiB, 640); 543 mc146818rtc_set_cmos_data(s, 0x15, val); 544 mc146818rtc_set_cmos_data(s, 0x16, val >> 8); 545 /* extended memory (next 64MiB) */ 546 if (x86ms->below_4g_mem_size > 1 * MiB) { 547 val = (x86ms->below_4g_mem_size - 1 * MiB) / KiB; 548 } else { 549 val = 0; 550 } 551 if (val > 65535) 552 val = 65535; 553 mc146818rtc_set_cmos_data(s, 0x17, val); 554 mc146818rtc_set_cmos_data(s, 0x18, val >> 8); 555 mc146818rtc_set_cmos_data(s, 0x30, val); 556 mc146818rtc_set_cmos_data(s, 0x31, val >> 8); 557 /* memory between 16MiB and 4GiB */ 558 if (x86ms->below_4g_mem_size > 16 * MiB) { 559 val = (x86ms->below_4g_mem_size - 16 * MiB) / (64 * KiB); 560 } else { 561 val = 0; 562 } 563 if (val > 65535) 564 val = 65535; 565 mc146818rtc_set_cmos_data(s, 0x34, val); 566 mc146818rtc_set_cmos_data(s, 0x35, val >> 8); 567 /* memory above 4GiB */ 568 val = x86ms->above_4g_mem_size / 65536; 569 mc146818rtc_set_cmos_data(s, 0x5b, val); 570 mc146818rtc_set_cmos_data(s, 0x5c, val >> 8); 571 mc146818rtc_set_cmos_data(s, 0x5d, val >> 16); 572 573 val = 0; 574 val |= 0x02; /* FPU is there */ 575 val |= 0x04; /* PS/2 mouse installed */ 576 mc146818rtc_set_cmos_data(s, REG_EQUIPMENT_BYTE, val); 577 } 578 579 static void handle_a20_line_change(void *opaque, int irq, int level) 580 { 581 X86CPU *cpu = opaque; 582 583 /* XXX: send to all CPUs ? */ 584 /* XXX: add logic to handle multiple A20 line sources */ 585 x86_cpu_set_a20(cpu, level); 586 } 587 588 #define NE2000_NB_MAX 6 589 590 static const int ne2000_io[NE2000_NB_MAX] = { 0x300, 0x320, 0x340, 0x360, 591 0x280, 0x380 }; 592 static const int ne2000_irq[NE2000_NB_MAX] = { 9, 10, 11, 3, 4, 5 }; 593 594 static gboolean pc_init_ne2k_isa(ISABus *bus, NICInfo *nd, Error **errp) 595 { 596 static int nb_ne2k = 0; 597 598 if (nb_ne2k == NE2000_NB_MAX) { 599 error_setg(errp, 600 "maximum number of ISA NE2000 devices exceeded"); 601 return false; 602 } 603 isa_ne2000_init(bus, ne2000_io[nb_ne2k], 604 ne2000_irq[nb_ne2k], nd); 605 nb_ne2k++; 606 return true; 607 } 608 609 void pc_acpi_smi_interrupt(void *opaque, int irq, int level) 610 { 611 X86CPU *cpu = opaque; 612 613 if (level) { 614 cpu_interrupt(CPU(cpu), CPU_INTERRUPT_SMI); 615 } 616 } 617 618 static 619 void pc_machine_done(Notifier *notifier, void *data) 620 { 621 PCMachineState *pcms = container_of(notifier, 622 PCMachineState, machine_done); 623 X86MachineState *x86ms = X86_MACHINE(pcms); 624 625 cxl_hook_up_pxb_registers(pcms->pcibus, &pcms->cxl_devices_state, 626 &error_fatal); 627 628 if (pcms->cxl_devices_state.is_enabled) { 629 cxl_fmws_link_targets(&pcms->cxl_devices_state, &error_fatal); 630 } 631 632 /* set the number of CPUs */ 633 x86_rtc_set_cpus_count(x86ms->rtc, x86ms->boot_cpus); 634 635 pci_bus_add_fw_cfg_extra_pci_roots(x86ms->fw_cfg, pcms->pcibus, 636 &error_abort); 637 638 acpi_setup(); 639 if (x86ms->fw_cfg) { 640 fw_cfg_build_smbios(pcms, x86ms->fw_cfg, pcms->smbios_entry_point_type); 641 fw_cfg_add_e820(x86ms->fw_cfg); 642 fw_cfg_build_feature_control(MACHINE(pcms), x86ms->fw_cfg); 643 /* update FW_CFG_NB_CPUS to account for -device added CPUs */ 644 fw_cfg_modify_i16(x86ms->fw_cfg, FW_CFG_NB_CPUS, x86ms->boot_cpus); 645 } 646 647 pc_cmos_init_late(pcms); 648 } 649 650 /* setup pci memory address space mapping into system address space */ 651 void pc_pci_as_mapping_init(MemoryRegion *system_memory, 652 MemoryRegion *pci_address_space) 653 { 654 /* Set to lower priority than RAM */ 655 memory_region_add_subregion_overlap(system_memory, 0x0, 656 pci_address_space, -1); 657 } 658 659 void xen_load_linux(PCMachineState *pcms) 660 { 661 int i; 662 FWCfgState *fw_cfg; 663 PCMachineClass *pcmc = PC_MACHINE_GET_CLASS(pcms); 664 X86MachineState *x86ms = X86_MACHINE(pcms); 665 666 assert(MACHINE(pcms)->kernel_filename != NULL); 667 668 fw_cfg = fw_cfg_init_io_dma(FW_CFG_IO_BASE, FW_CFG_IO_BASE + 4, 669 &address_space_memory); 670 fw_cfg_add_i16(fw_cfg, FW_CFG_NB_CPUS, x86ms->boot_cpus); 671 rom_set_fw(fw_cfg); 672 673 x86_load_linux(x86ms, fw_cfg, PC_FW_DATA, pcmc->pvh_enabled); 674 for (i = 0; i < nb_option_roms; i++) { 675 assert(!strcmp(option_rom[i].name, "linuxboot.bin") || 676 !strcmp(option_rom[i].name, "linuxboot_dma.bin") || 677 !strcmp(option_rom[i].name, "pvh.bin") || 678 !strcmp(option_rom[i].name, "multiboot.bin") || 679 !strcmp(option_rom[i].name, "multiboot_dma.bin")); 680 rom_add_option(option_rom[i].name, option_rom[i].bootindex); 681 } 682 x86ms->fw_cfg = fw_cfg; 683 } 684 685 #define PC_ROM_MIN_VGA 0xc0000 686 #define PC_ROM_MIN_OPTION 0xc8000 687 #define PC_ROM_MAX 0xe0000 688 #define PC_ROM_ALIGN 0x800 689 #define PC_ROM_SIZE (PC_ROM_MAX - PC_ROM_MIN_VGA) 690 691 static hwaddr pc_above_4g_end(PCMachineState *pcms) 692 { 693 X86MachineState *x86ms = X86_MACHINE(pcms); 694 695 if (pcms->sgx_epc.size != 0) { 696 return sgx_epc_above_4g_end(&pcms->sgx_epc); 697 } 698 699 return x86ms->above_4g_mem_start + x86ms->above_4g_mem_size; 700 } 701 702 static void pc_get_device_memory_range(PCMachineState *pcms, 703 hwaddr *base, 704 ram_addr_t *device_mem_size) 705 { 706 MachineState *machine = MACHINE(pcms); 707 ram_addr_t size; 708 hwaddr addr; 709 710 size = machine->maxram_size - machine->ram_size; 711 addr = ROUND_UP(pc_above_4g_end(pcms), 1 * GiB); 712 713 /* size device region assuming 1G page max alignment per slot */ 714 size += (1 * GiB) * machine->ram_slots; 715 716 *base = addr; 717 *device_mem_size = size; 718 } 719 720 static uint64_t pc_get_cxl_range_start(PCMachineState *pcms) 721 { 722 PCMachineClass *pcmc = PC_MACHINE_GET_CLASS(pcms); 723 MachineState *ms = MACHINE(pcms); 724 hwaddr cxl_base; 725 ram_addr_t size; 726 727 if (pcmc->has_reserved_memory && 728 (ms->ram_size < ms->maxram_size)) { 729 pc_get_device_memory_range(pcms, &cxl_base, &size); 730 cxl_base += size; 731 } else { 732 cxl_base = pc_above_4g_end(pcms); 733 } 734 735 return cxl_base; 736 } 737 738 static uint64_t pc_get_cxl_range_end(PCMachineState *pcms) 739 { 740 uint64_t start = pc_get_cxl_range_start(pcms) + MiB; 741 742 if (pcms->cxl_devices_state.fixed_windows) { 743 GList *it; 744 745 start = ROUND_UP(start, 256 * MiB); 746 for (it = pcms->cxl_devices_state.fixed_windows; it; it = it->next) { 747 CXLFixedWindow *fw = it->data; 748 start += fw->size; 749 } 750 } 751 752 return start; 753 } 754 755 static hwaddr pc_max_used_gpa(PCMachineState *pcms, uint64_t pci_hole64_size) 756 { 757 X86CPU *cpu = X86_CPU(first_cpu); 758 PCMachineClass *pcmc = PC_MACHINE_GET_CLASS(pcms); 759 MachineState *ms = MACHINE(pcms); 760 761 if (cpu->env.features[FEAT_8000_0001_EDX] & CPUID_EXT2_LM) { 762 /* 64-bit systems */ 763 return pc_pci_hole64_start() + pci_hole64_size - 1; 764 } 765 766 /* 32-bit systems */ 767 if (pcmc->broken_32bit_mem_addr_check) { 768 /* old value for compatibility reasons */ 769 return ((hwaddr)1 << cpu->phys_bits) - 1; 770 } 771 772 /* 773 * 32-bit systems don't have hole64 but they might have a region for 774 * memory devices. Even if additional hotplugged memory devices might 775 * not be usable by most guest OSes, we need to still consider them for 776 * calculating the highest possible GPA so that we can properly report 777 * if someone configures them on a CPU that cannot possibly address them. 778 */ 779 if (pcmc->has_reserved_memory && 780 (ms->ram_size < ms->maxram_size)) { 781 hwaddr devmem_start; 782 ram_addr_t devmem_size; 783 784 pc_get_device_memory_range(pcms, &devmem_start, &devmem_size); 785 devmem_start += devmem_size; 786 return devmem_start - 1; 787 } 788 789 /* configuration without any memory hotplug */ 790 return pc_above_4g_end(pcms) - 1; 791 } 792 793 /* 794 * AMD systems with an IOMMU have an additional hole close to the 795 * 1Tb, which are special GPAs that cannot be DMA mapped. Depending 796 * on kernel version, VFIO may or may not let you DMA map those ranges. 797 * Starting Linux v5.4 we validate it, and can't create guests on AMD machines 798 * with certain memory sizes. It's also wrong to use those IOVA ranges 799 * in detriment of leading to IOMMU INVALID_DEVICE_REQUEST or worse. 800 * The ranges reserved for Hyper-Transport are: 801 * 802 * FD_0000_0000h - FF_FFFF_FFFFh 803 * 804 * The ranges represent the following: 805 * 806 * Base Address Top Address Use 807 * 808 * FD_0000_0000h FD_F7FF_FFFFh Reserved interrupt address space 809 * FD_F800_0000h FD_F8FF_FFFFh Interrupt/EOI IntCtl 810 * FD_F900_0000h FD_F90F_FFFFh Legacy PIC IACK 811 * FD_F910_0000h FD_F91F_FFFFh System Management 812 * FD_F920_0000h FD_FAFF_FFFFh Reserved Page Tables 813 * FD_FB00_0000h FD_FBFF_FFFFh Address Translation 814 * FD_FC00_0000h FD_FDFF_FFFFh I/O Space 815 * FD_FE00_0000h FD_FFFF_FFFFh Configuration 816 * FE_0000_0000h FE_1FFF_FFFFh Extended Configuration/Device Messages 817 * FE_2000_0000h FF_FFFF_FFFFh Reserved 818 * 819 * See AMD IOMMU spec, section 2.1.2 "IOMMU Logical Topology", 820 * Table 3: Special Address Controls (GPA) for more information. 821 */ 822 #define AMD_HT_START 0xfd00000000UL 823 #define AMD_HT_END 0xffffffffffUL 824 #define AMD_ABOVE_1TB_START (AMD_HT_END + 1) 825 #define AMD_HT_SIZE (AMD_ABOVE_1TB_START - AMD_HT_START) 826 827 void pc_memory_init(PCMachineState *pcms, 828 MemoryRegion *system_memory, 829 MemoryRegion *rom_memory, 830 uint64_t pci_hole64_size) 831 { 832 int linux_boot, i; 833 MemoryRegion *option_rom_mr; 834 MemoryRegion *ram_below_4g, *ram_above_4g; 835 FWCfgState *fw_cfg; 836 MachineState *machine = MACHINE(pcms); 837 MachineClass *mc = MACHINE_GET_CLASS(machine); 838 PCMachineClass *pcmc = PC_MACHINE_GET_CLASS(pcms); 839 X86MachineState *x86ms = X86_MACHINE(pcms); 840 hwaddr maxphysaddr, maxusedaddr; 841 hwaddr cxl_base, cxl_resv_end = 0; 842 X86CPU *cpu = X86_CPU(first_cpu); 843 844 assert(machine->ram_size == x86ms->below_4g_mem_size + 845 x86ms->above_4g_mem_size); 846 847 linux_boot = (machine->kernel_filename != NULL); 848 849 /* 850 * The HyperTransport range close to the 1T boundary is unique to AMD 851 * hosts with IOMMUs enabled. Restrict the ram-above-4g relocation 852 * to above 1T to AMD vCPUs only. @enforce_amd_1tb_hole is only false in 853 * older machine types (<= 7.0) for compatibility purposes. 854 */ 855 if (IS_AMD_CPU(&cpu->env) && pcmc->enforce_amd_1tb_hole) { 856 /* Bail out if max possible address does not cross HT range */ 857 if (pc_max_used_gpa(pcms, pci_hole64_size) >= AMD_HT_START) { 858 x86ms->above_4g_mem_start = AMD_ABOVE_1TB_START; 859 } 860 861 /* 862 * Advertise the HT region if address space covers the reserved 863 * region or if we relocate. 864 */ 865 if (cpu->phys_bits >= 40) { 866 e820_add_entry(AMD_HT_START, AMD_HT_SIZE, E820_RESERVED); 867 } 868 } 869 870 /* 871 * phys-bits is required to be appropriately configured 872 * to make sure max used GPA is reachable. 873 */ 874 maxusedaddr = pc_max_used_gpa(pcms, pci_hole64_size); 875 maxphysaddr = ((hwaddr)1 << cpu->phys_bits) - 1; 876 if (maxphysaddr < maxusedaddr) { 877 error_report("Address space limit 0x%"PRIx64" < 0x%"PRIx64 878 " phys-bits too low (%u)", 879 maxphysaddr, maxusedaddr, cpu->phys_bits); 880 exit(EXIT_FAILURE); 881 } 882 883 /* 884 * Split single memory region and use aliases to address portions of it, 885 * done for backwards compatibility with older qemus. 886 */ 887 ram_below_4g = g_malloc(sizeof(*ram_below_4g)); 888 memory_region_init_alias(ram_below_4g, NULL, "ram-below-4g", machine->ram, 889 0, x86ms->below_4g_mem_size); 890 memory_region_add_subregion(system_memory, 0, ram_below_4g); 891 e820_add_entry(0, x86ms->below_4g_mem_size, E820_RAM); 892 if (x86ms->above_4g_mem_size > 0) { 893 ram_above_4g = g_malloc(sizeof(*ram_above_4g)); 894 memory_region_init_alias(ram_above_4g, NULL, "ram-above-4g", 895 machine->ram, 896 x86ms->below_4g_mem_size, 897 x86ms->above_4g_mem_size); 898 memory_region_add_subregion(system_memory, x86ms->above_4g_mem_start, 899 ram_above_4g); 900 e820_add_entry(x86ms->above_4g_mem_start, x86ms->above_4g_mem_size, 901 E820_RAM); 902 } 903 904 if (pcms->sgx_epc.size != 0) { 905 e820_add_entry(pcms->sgx_epc.base, pcms->sgx_epc.size, E820_RESERVED); 906 } 907 908 if (!pcmc->has_reserved_memory && 909 (machine->ram_slots || 910 (machine->maxram_size > machine->ram_size))) { 911 912 error_report("\"-memory 'slots|maxmem'\" is not supported by: %s", 913 mc->name); 914 exit(EXIT_FAILURE); 915 } 916 917 /* initialize device memory address space */ 918 if (pcmc->has_reserved_memory && 919 (machine->ram_size < machine->maxram_size)) { 920 ram_addr_t device_mem_size; 921 hwaddr device_mem_base; 922 923 if (machine->ram_slots > ACPI_MAX_RAM_SLOTS) { 924 error_report("unsupported amount of memory slots: %"PRIu64, 925 machine->ram_slots); 926 exit(EXIT_FAILURE); 927 } 928 929 if (QEMU_ALIGN_UP(machine->maxram_size, 930 TARGET_PAGE_SIZE) != machine->maxram_size) { 931 error_report("maximum memory size must by aligned to multiple of " 932 "%d bytes", TARGET_PAGE_SIZE); 933 exit(EXIT_FAILURE); 934 } 935 936 pc_get_device_memory_range(pcms, &device_mem_base, &device_mem_size); 937 938 if (device_mem_base + device_mem_size < device_mem_size) { 939 error_report("unsupported amount of maximum memory: " RAM_ADDR_FMT, 940 machine->maxram_size); 941 exit(EXIT_FAILURE); 942 } 943 machine_memory_devices_init(machine, device_mem_base, device_mem_size); 944 } 945 946 if (pcms->cxl_devices_state.is_enabled) { 947 MemoryRegion *mr = &pcms->cxl_devices_state.host_mr; 948 hwaddr cxl_size = MiB; 949 950 cxl_base = pc_get_cxl_range_start(pcms); 951 memory_region_init(mr, OBJECT(machine), "cxl_host_reg", cxl_size); 952 memory_region_add_subregion(system_memory, cxl_base, mr); 953 cxl_resv_end = cxl_base + cxl_size; 954 if (pcms->cxl_devices_state.fixed_windows) { 955 hwaddr cxl_fmw_base; 956 GList *it; 957 958 cxl_fmw_base = ROUND_UP(cxl_base + cxl_size, 256 * MiB); 959 for (it = pcms->cxl_devices_state.fixed_windows; it; it = it->next) { 960 CXLFixedWindow *fw = it->data; 961 962 fw->base = cxl_fmw_base; 963 memory_region_init_io(&fw->mr, OBJECT(machine), &cfmws_ops, fw, 964 "cxl-fixed-memory-region", fw->size); 965 memory_region_add_subregion(system_memory, fw->base, &fw->mr); 966 cxl_fmw_base += fw->size; 967 cxl_resv_end = cxl_fmw_base; 968 } 969 } 970 } 971 972 /* Initialize PC system firmware */ 973 pc_system_firmware_init(pcms, rom_memory); 974 975 option_rom_mr = g_malloc(sizeof(*option_rom_mr)); 976 if (machine_require_guest_memfd(machine)) { 977 memory_region_init_ram_guest_memfd(option_rom_mr, NULL, "pc.rom", 978 PC_ROM_SIZE, &error_fatal); 979 } else { 980 memory_region_init_ram(option_rom_mr, NULL, "pc.rom", PC_ROM_SIZE, 981 &error_fatal); 982 if (pcmc->pci_enabled) { 983 memory_region_set_readonly(option_rom_mr, true); 984 } 985 } 986 memory_region_add_subregion_overlap(rom_memory, 987 PC_ROM_MIN_VGA, 988 option_rom_mr, 989 1); 990 991 fw_cfg = fw_cfg_arch_create(machine, 992 x86ms->boot_cpus, x86ms->apic_id_limit); 993 994 rom_set_fw(fw_cfg); 995 996 if (machine->device_memory) { 997 uint64_t *val = g_malloc(sizeof(*val)); 998 uint64_t res_mem_end = machine->device_memory->base; 999 1000 if (!pcmc->broken_reserved_end) { 1001 res_mem_end += memory_region_size(&machine->device_memory->mr); 1002 } 1003 1004 if (pcms->cxl_devices_state.is_enabled) { 1005 res_mem_end = cxl_resv_end; 1006 } 1007 *val = cpu_to_le64(ROUND_UP(res_mem_end, 1 * GiB)); 1008 fw_cfg_add_file(fw_cfg, "etc/reserved-memory-end", val, sizeof(*val)); 1009 } 1010 1011 if (linux_boot) { 1012 x86_load_linux(x86ms, fw_cfg, PC_FW_DATA, pcmc->pvh_enabled); 1013 } 1014 1015 for (i = 0; i < nb_option_roms; i++) { 1016 rom_add_option(option_rom[i].name, option_rom[i].bootindex); 1017 } 1018 x86ms->fw_cfg = fw_cfg; 1019 1020 /* Init default IOAPIC address space */ 1021 x86ms->ioapic_as = &address_space_memory; 1022 1023 /* Init ACPI memory hotplug IO base address */ 1024 pcms->memhp_io_base = ACPI_MEMORY_HOTPLUG_BASE; 1025 } 1026 1027 /* 1028 * The 64bit pci hole starts after "above 4G RAM" and 1029 * potentially the space reserved for memory hotplug. 1030 */ 1031 uint64_t pc_pci_hole64_start(void) 1032 { 1033 PCMachineState *pcms = PC_MACHINE(qdev_get_machine()); 1034 PCMachineClass *pcmc = PC_MACHINE_GET_CLASS(pcms); 1035 MachineState *ms = MACHINE(pcms); 1036 uint64_t hole64_start = 0; 1037 ram_addr_t size = 0; 1038 1039 if (pcms->cxl_devices_state.is_enabled) { 1040 hole64_start = pc_get_cxl_range_end(pcms); 1041 } else if (pcmc->has_reserved_memory && (ms->ram_size < ms->maxram_size)) { 1042 pc_get_device_memory_range(pcms, &hole64_start, &size); 1043 if (!pcmc->broken_reserved_end) { 1044 hole64_start += size; 1045 } 1046 } else { 1047 hole64_start = pc_above_4g_end(pcms); 1048 } 1049 1050 return ROUND_UP(hole64_start, 1 * GiB); 1051 } 1052 1053 DeviceState *pc_vga_init(ISABus *isa_bus, PCIBus *pci_bus) 1054 { 1055 DeviceState *dev = NULL; 1056 1057 rom_set_order_override(FW_CFG_ORDER_OVERRIDE_VGA); 1058 if (pci_bus) { 1059 PCIDevice *pcidev = pci_vga_init(pci_bus); 1060 dev = pcidev ? &pcidev->qdev : NULL; 1061 } else if (isa_bus) { 1062 ISADevice *isadev = isa_vga_init(isa_bus); 1063 dev = isadev ? DEVICE(isadev) : NULL; 1064 } 1065 rom_reset_order_override(); 1066 return dev; 1067 } 1068 1069 static const MemoryRegionOps ioport80_io_ops = { 1070 .write = ioport80_write, 1071 .read = ioport80_read, 1072 .endianness = DEVICE_LITTLE_ENDIAN, 1073 .impl = { 1074 .min_access_size = 1, 1075 .max_access_size = 1, 1076 }, 1077 }; 1078 1079 static const MemoryRegionOps ioportF0_io_ops = { 1080 .write = ioportF0_write, 1081 .read = ioportF0_read, 1082 .endianness = DEVICE_LITTLE_ENDIAN, 1083 .impl = { 1084 .min_access_size = 1, 1085 .max_access_size = 1, 1086 }, 1087 }; 1088 1089 static void pc_superio_init(ISABus *isa_bus, bool create_fdctrl, 1090 bool create_i8042, bool no_vmport, Error **errp) 1091 { 1092 int i; 1093 DriveInfo *fd[MAX_FD]; 1094 qemu_irq *a20_line; 1095 ISADevice *i8042, *port92, *vmmouse; 1096 1097 serial_hds_isa_init(isa_bus, 0, MAX_ISA_SERIAL_PORTS); 1098 parallel_hds_isa_init(isa_bus, MAX_PARALLEL_PORTS); 1099 1100 for (i = 0; i < MAX_FD; i++) { 1101 fd[i] = drive_get(IF_FLOPPY, 0, i); 1102 create_fdctrl |= !!fd[i]; 1103 } 1104 if (create_fdctrl) { 1105 #ifdef CONFIG_FDC_ISA 1106 ISADevice *fdc = isa_new(TYPE_ISA_FDC); 1107 if (fdc) { 1108 isa_realize_and_unref(fdc, isa_bus, &error_fatal); 1109 isa_fdc_init_drives(fdc, fd); 1110 } 1111 #endif 1112 } 1113 1114 if (!create_i8042) { 1115 if (!no_vmport) { 1116 error_setg(errp, 1117 "vmport requires the i8042 controller to be enabled"); 1118 } 1119 return; 1120 } 1121 1122 i8042 = isa_create_simple(isa_bus, TYPE_I8042); 1123 if (!no_vmport) { 1124 isa_create_simple(isa_bus, TYPE_VMPORT); 1125 vmmouse = isa_try_new("vmmouse"); 1126 } else { 1127 vmmouse = NULL; 1128 } 1129 if (vmmouse) { 1130 object_property_set_link(OBJECT(vmmouse), TYPE_I8042, OBJECT(i8042), 1131 &error_abort); 1132 isa_realize_and_unref(vmmouse, isa_bus, &error_fatal); 1133 } 1134 port92 = isa_create_simple(isa_bus, TYPE_PORT92); 1135 1136 a20_line = qemu_allocate_irqs(handle_a20_line_change, first_cpu, 2); 1137 qdev_connect_gpio_out_named(DEVICE(i8042), 1138 I8042_A20_LINE, 0, a20_line[0]); 1139 qdev_connect_gpio_out_named(DEVICE(port92), 1140 PORT92_A20_LINE, 0, a20_line[1]); 1141 g_free(a20_line); 1142 } 1143 1144 void pc_basic_device_init(struct PCMachineState *pcms, 1145 ISABus *isa_bus, qemu_irq *gsi, 1146 ISADevice *rtc_state, 1147 bool create_fdctrl, 1148 uint32_t hpet_irqs) 1149 { 1150 int i; 1151 DeviceState *hpet = NULL; 1152 int pit_isa_irq = 0; 1153 qemu_irq pit_alt_irq = NULL; 1154 ISADevice *pit = NULL; 1155 MemoryRegion *ioport80_io = g_new(MemoryRegion, 1); 1156 MemoryRegion *ioportF0_io = g_new(MemoryRegion, 1); 1157 X86MachineState *x86ms = X86_MACHINE(pcms); 1158 1159 memory_region_init_io(ioport80_io, NULL, &ioport80_io_ops, NULL, "ioport80", 1); 1160 memory_region_add_subregion(isa_bus->address_space_io, 0x80, ioport80_io); 1161 1162 memory_region_init_io(ioportF0_io, NULL, &ioportF0_io_ops, NULL, "ioportF0", 1); 1163 memory_region_add_subregion(isa_bus->address_space_io, 0xf0, ioportF0_io); 1164 1165 /* 1166 * Check if an HPET shall be created. 1167 */ 1168 if (pcms->hpet_enabled) { 1169 qemu_irq rtc_irq; 1170 1171 hpet = qdev_try_new(TYPE_HPET); 1172 if (!hpet) { 1173 error_report("couldn't create HPET device"); 1174 exit(1); 1175 } 1176 /* 1177 * For pc-piix-*, hpet's intcap is always IRQ2. For pc-q35-*, 1178 * use IRQ16~23, IRQ8 and IRQ2. If the user has already set 1179 * the property, use whatever mask they specified. 1180 */ 1181 uint8_t compat = object_property_get_uint(OBJECT(hpet), 1182 HPET_INTCAP, NULL); 1183 if (!compat) { 1184 qdev_prop_set_uint32(hpet, HPET_INTCAP, hpet_irqs); 1185 } 1186 sysbus_realize_and_unref(SYS_BUS_DEVICE(hpet), &error_fatal); 1187 sysbus_mmio_map(SYS_BUS_DEVICE(hpet), 0, HPET_BASE); 1188 1189 for (i = 0; i < IOAPIC_NUM_PINS; i++) { 1190 sysbus_connect_irq(SYS_BUS_DEVICE(hpet), i, gsi[i]); 1191 } 1192 pit_isa_irq = -1; 1193 pit_alt_irq = qdev_get_gpio_in(hpet, HPET_LEGACY_PIT_INT); 1194 rtc_irq = qdev_get_gpio_in(hpet, HPET_LEGACY_RTC_INT); 1195 1196 /* overwrite connection created by south bridge */ 1197 qdev_connect_gpio_out(DEVICE(rtc_state), 0, rtc_irq); 1198 } 1199 1200 object_property_add_alias(OBJECT(pcms), "rtc-time", OBJECT(rtc_state), 1201 "date"); 1202 1203 #ifdef CONFIG_XEN_EMU 1204 if (xen_mode == XEN_EMULATE) { 1205 xen_overlay_create(); 1206 xen_evtchn_create(IOAPIC_NUM_PINS, gsi); 1207 xen_gnttab_create(); 1208 xen_xenstore_create(); 1209 if (pcms->pcibus) { 1210 pci_create_simple(pcms->pcibus, -1, "xen-platform"); 1211 } 1212 xen_bus_init(); 1213 } 1214 #endif 1215 1216 qemu_register_boot_set(pc_boot_set, pcms); 1217 set_boot_dev(pcms, MC146818_RTC(rtc_state), 1218 MACHINE(pcms)->boot_config.order, &error_fatal); 1219 1220 if (!xen_enabled() && 1221 (x86ms->pit == ON_OFF_AUTO_AUTO || x86ms->pit == ON_OFF_AUTO_ON)) { 1222 if (kvm_pit_in_kernel()) { 1223 pit = kvm_pit_init(isa_bus, 0x40); 1224 } else { 1225 pit = i8254_pit_init(isa_bus, 0x40, pit_isa_irq, pit_alt_irq); 1226 } 1227 if (hpet) { 1228 /* connect PIT to output control line of the HPET */ 1229 qdev_connect_gpio_out(hpet, 0, qdev_get_gpio_in(DEVICE(pit), 0)); 1230 } 1231 object_property_set_link(OBJECT(pcms->pcspk), "pit", 1232 OBJECT(pit), &error_fatal); 1233 isa_realize_and_unref(pcms->pcspk, isa_bus, &error_fatal); 1234 } 1235 1236 if (pcms->vmport == ON_OFF_AUTO_AUTO) { 1237 pcms->vmport = (xen_enabled() || !pcms->i8042_enabled) 1238 ? ON_OFF_AUTO_OFF : ON_OFF_AUTO_ON; 1239 } 1240 1241 /* Super I/O */ 1242 pc_superio_init(isa_bus, create_fdctrl, pcms->i8042_enabled, 1243 pcms->vmport != ON_OFF_AUTO_ON, &error_fatal); 1244 } 1245 1246 void pc_nic_init(PCMachineClass *pcmc, ISABus *isa_bus, PCIBus *pci_bus) 1247 { 1248 MachineClass *mc = MACHINE_CLASS(pcmc); 1249 bool default_is_ne2k = g_str_equal(mc->default_nic, TYPE_ISA_NE2000); 1250 NICInfo *nd; 1251 1252 rom_set_order_override(FW_CFG_ORDER_OVERRIDE_NIC); 1253 1254 while ((nd = qemu_find_nic_info(TYPE_ISA_NE2000, default_is_ne2k, NULL))) { 1255 pc_init_ne2k_isa(isa_bus, nd, &error_fatal); 1256 } 1257 1258 /* Anything remaining should be a PCI NIC */ 1259 if (pci_bus) { 1260 pci_init_nic_devices(pci_bus, mc->default_nic); 1261 } 1262 1263 rom_reset_order_override(); 1264 } 1265 1266 void pc_i8259_create(ISABus *isa_bus, qemu_irq *i8259_irqs) 1267 { 1268 qemu_irq *i8259; 1269 1270 if (kvm_pic_in_kernel()) { 1271 i8259 = kvm_i8259_init(isa_bus); 1272 } else if (xen_enabled()) { 1273 i8259 = xen_interrupt_controller_init(); 1274 } else { 1275 i8259 = i8259_init(isa_bus, x86_allocate_cpu_irq()); 1276 } 1277 1278 for (size_t i = 0; i < ISA_NUM_IRQS; i++) { 1279 i8259_irqs[i] = i8259[i]; 1280 } 1281 1282 g_free(i8259); 1283 } 1284 1285 static void pc_memory_pre_plug(HotplugHandler *hotplug_dev, DeviceState *dev, 1286 Error **errp) 1287 { 1288 const X86MachineState *x86ms = X86_MACHINE(hotplug_dev); 1289 const MachineState *ms = MACHINE(hotplug_dev); 1290 const bool is_nvdimm = object_dynamic_cast(OBJECT(dev), TYPE_NVDIMM); 1291 Error *local_err = NULL; 1292 1293 /* 1294 * When "acpi=off" is used with the Q35 machine type, no ACPI is built, 1295 * but pcms->acpi_dev is still created. Check !acpi_enabled in 1296 * addition to cover this case. 1297 */ 1298 if (!x86ms->acpi_dev || !x86_machine_is_acpi_enabled(x86ms)) { 1299 error_setg(errp, 1300 "memory hotplug is not enabled: missing acpi device or acpi disabled"); 1301 return; 1302 } 1303 1304 if (is_nvdimm && !ms->nvdimms_state->is_enabled) { 1305 error_setg(errp, "nvdimm is not enabled: missing 'nvdimm' in '-M'"); 1306 return; 1307 } 1308 1309 hotplug_handler_pre_plug(x86ms->acpi_dev, dev, &local_err); 1310 if (local_err) { 1311 error_propagate(errp, local_err); 1312 return; 1313 } 1314 1315 pc_dimm_pre_plug(PC_DIMM(dev), MACHINE(hotplug_dev), errp); 1316 } 1317 1318 static void pc_memory_plug(HotplugHandler *hotplug_dev, 1319 DeviceState *dev, Error **errp) 1320 { 1321 PCMachineState *pcms = PC_MACHINE(hotplug_dev); 1322 X86MachineState *x86ms = X86_MACHINE(hotplug_dev); 1323 MachineState *ms = MACHINE(hotplug_dev); 1324 bool is_nvdimm = object_dynamic_cast(OBJECT(dev), TYPE_NVDIMM); 1325 1326 pc_dimm_plug(PC_DIMM(dev), MACHINE(pcms)); 1327 1328 if (is_nvdimm) { 1329 nvdimm_plug(ms->nvdimms_state); 1330 } 1331 1332 hotplug_handler_plug(x86ms->acpi_dev, dev, &error_abort); 1333 } 1334 1335 static void pc_memory_unplug_request(HotplugHandler *hotplug_dev, 1336 DeviceState *dev, Error **errp) 1337 { 1338 X86MachineState *x86ms = X86_MACHINE(hotplug_dev); 1339 1340 /* 1341 * When "acpi=off" is used with the Q35 machine type, no ACPI is built, 1342 * but pcms->acpi_dev is still created. Check !acpi_enabled in 1343 * addition to cover this case. 1344 */ 1345 if (!x86ms->acpi_dev || !x86_machine_is_acpi_enabled(x86ms)) { 1346 error_setg(errp, 1347 "memory hotplug is not enabled: missing acpi device or acpi disabled"); 1348 return; 1349 } 1350 1351 if (object_dynamic_cast(OBJECT(dev), TYPE_NVDIMM)) { 1352 error_setg(errp, "nvdimm device hot unplug is not supported yet."); 1353 return; 1354 } 1355 1356 hotplug_handler_unplug_request(x86ms->acpi_dev, dev, 1357 errp); 1358 } 1359 1360 static void pc_memory_unplug(HotplugHandler *hotplug_dev, 1361 DeviceState *dev, Error **errp) 1362 { 1363 PCMachineState *pcms = PC_MACHINE(hotplug_dev); 1364 X86MachineState *x86ms = X86_MACHINE(hotplug_dev); 1365 Error *local_err = NULL; 1366 1367 hotplug_handler_unplug(x86ms->acpi_dev, dev, &local_err); 1368 if (local_err) { 1369 goto out; 1370 } 1371 1372 pc_dimm_unplug(PC_DIMM(dev), MACHINE(pcms)); 1373 qdev_unrealize(dev); 1374 out: 1375 error_propagate(errp, local_err); 1376 } 1377 1378 static void pc_hv_balloon_pre_plug(HotplugHandler *hotplug_dev, 1379 DeviceState *dev, Error **errp) 1380 { 1381 /* The vmbus handler has no hotplug handler; we should never end up here. */ 1382 g_assert(!dev->hotplugged); 1383 memory_device_pre_plug(MEMORY_DEVICE(dev), MACHINE(hotplug_dev), errp); 1384 } 1385 1386 static void pc_hv_balloon_plug(HotplugHandler *hotplug_dev, 1387 DeviceState *dev, Error **errp) 1388 { 1389 memory_device_plug(MEMORY_DEVICE(dev), MACHINE(hotplug_dev)); 1390 } 1391 1392 static void pc_machine_device_pre_plug_cb(HotplugHandler *hotplug_dev, 1393 DeviceState *dev, Error **errp) 1394 { 1395 if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM)) { 1396 pc_memory_pre_plug(hotplug_dev, dev, errp); 1397 } else if (object_dynamic_cast(OBJECT(dev), TYPE_CPU)) { 1398 x86_cpu_pre_plug(hotplug_dev, dev, errp); 1399 } else if (object_dynamic_cast(OBJECT(dev), TYPE_VIRTIO_MD_PCI)) { 1400 virtio_md_pci_pre_plug(VIRTIO_MD_PCI(dev), MACHINE(hotplug_dev), errp); 1401 } else if (object_dynamic_cast(OBJECT(dev), TYPE_VIRTIO_IOMMU_PCI)) { 1402 /* Declare the APIC range as the reserved MSI region */ 1403 char *resv_prop_str = g_strdup_printf("0xfee00000:0xfeefffff:%d", 1404 VIRTIO_IOMMU_RESV_MEM_T_MSI); 1405 QList *reserved_regions = qlist_new(); 1406 1407 qlist_append_str(reserved_regions, resv_prop_str); 1408 qdev_prop_set_array(dev, "reserved-regions", reserved_regions); 1409 1410 g_free(resv_prop_str); 1411 } 1412 1413 if (object_dynamic_cast(OBJECT(dev), TYPE_X86_IOMMU_DEVICE) || 1414 object_dynamic_cast(OBJECT(dev), TYPE_VIRTIO_IOMMU_PCI)) { 1415 PCMachineState *pcms = PC_MACHINE(hotplug_dev); 1416 1417 if (pcms->iommu) { 1418 error_setg(errp, "QEMU does not support multiple vIOMMUs " 1419 "for x86 yet."); 1420 return; 1421 } 1422 pcms->iommu = dev; 1423 } else if (object_dynamic_cast(OBJECT(dev), TYPE_HV_BALLOON)) { 1424 pc_hv_balloon_pre_plug(hotplug_dev, dev, errp); 1425 } 1426 } 1427 1428 static void pc_machine_device_plug_cb(HotplugHandler *hotplug_dev, 1429 DeviceState *dev, Error **errp) 1430 { 1431 if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM)) { 1432 pc_memory_plug(hotplug_dev, dev, errp); 1433 } else if (object_dynamic_cast(OBJECT(dev), TYPE_CPU)) { 1434 x86_cpu_plug(hotplug_dev, dev, errp); 1435 } else if (object_dynamic_cast(OBJECT(dev), TYPE_VIRTIO_MD_PCI)) { 1436 virtio_md_pci_plug(VIRTIO_MD_PCI(dev), MACHINE(hotplug_dev), errp); 1437 } else if (object_dynamic_cast(OBJECT(dev), TYPE_HV_BALLOON)) { 1438 pc_hv_balloon_plug(hotplug_dev, dev, errp); 1439 } 1440 } 1441 1442 static void pc_machine_device_unplug_request_cb(HotplugHandler *hotplug_dev, 1443 DeviceState *dev, Error **errp) 1444 { 1445 if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM)) { 1446 pc_memory_unplug_request(hotplug_dev, dev, errp); 1447 } else if (object_dynamic_cast(OBJECT(dev), TYPE_CPU)) { 1448 x86_cpu_unplug_request_cb(hotplug_dev, dev, errp); 1449 } else if (object_dynamic_cast(OBJECT(dev), TYPE_VIRTIO_MD_PCI)) { 1450 virtio_md_pci_unplug_request(VIRTIO_MD_PCI(dev), MACHINE(hotplug_dev), 1451 errp); 1452 } else { 1453 error_setg(errp, "acpi: device unplug request for not supported device" 1454 " type: %s", object_get_typename(OBJECT(dev))); 1455 } 1456 } 1457 1458 static void pc_machine_device_unplug_cb(HotplugHandler *hotplug_dev, 1459 DeviceState *dev, Error **errp) 1460 { 1461 if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM)) { 1462 pc_memory_unplug(hotplug_dev, dev, errp); 1463 } else if (object_dynamic_cast(OBJECT(dev), TYPE_CPU)) { 1464 x86_cpu_unplug_cb(hotplug_dev, dev, errp); 1465 } else if (object_dynamic_cast(OBJECT(dev), TYPE_VIRTIO_MD_PCI)) { 1466 virtio_md_pci_unplug(VIRTIO_MD_PCI(dev), MACHINE(hotplug_dev), errp); 1467 } else { 1468 error_setg(errp, "acpi: device unplug for not supported device" 1469 " type: %s", object_get_typename(OBJECT(dev))); 1470 } 1471 } 1472 1473 static HotplugHandler *pc_get_hotplug_handler(MachineState *machine, 1474 DeviceState *dev) 1475 { 1476 if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM) || 1477 object_dynamic_cast(OBJECT(dev), TYPE_CPU) || 1478 object_dynamic_cast(OBJECT(dev), TYPE_VIRTIO_MD_PCI) || 1479 object_dynamic_cast(OBJECT(dev), TYPE_VIRTIO_IOMMU_PCI) || 1480 object_dynamic_cast(OBJECT(dev), TYPE_HV_BALLOON) || 1481 object_dynamic_cast(OBJECT(dev), TYPE_X86_IOMMU_DEVICE)) { 1482 return HOTPLUG_HANDLER(machine); 1483 } 1484 1485 return NULL; 1486 } 1487 1488 static void pc_machine_get_vmport(Object *obj, Visitor *v, const char *name, 1489 void *opaque, Error **errp) 1490 { 1491 PCMachineState *pcms = PC_MACHINE(obj); 1492 OnOffAuto vmport = pcms->vmport; 1493 1494 visit_type_OnOffAuto(v, name, &vmport, errp); 1495 } 1496 1497 static void pc_machine_set_vmport(Object *obj, Visitor *v, const char *name, 1498 void *opaque, Error **errp) 1499 { 1500 PCMachineState *pcms = PC_MACHINE(obj); 1501 1502 visit_type_OnOffAuto(v, name, &pcms->vmport, errp); 1503 } 1504 1505 static bool pc_machine_get_fd_bootchk(Object *obj, Error **errp) 1506 { 1507 PCMachineState *pcms = PC_MACHINE(obj); 1508 1509 return pcms->fd_bootchk; 1510 } 1511 1512 static void pc_machine_set_fd_bootchk(Object *obj, bool value, Error **errp) 1513 { 1514 PCMachineState *pcms = PC_MACHINE(obj); 1515 1516 pcms->fd_bootchk = value; 1517 } 1518 1519 static bool pc_machine_get_smbus(Object *obj, Error **errp) 1520 { 1521 PCMachineState *pcms = PC_MACHINE(obj); 1522 1523 return pcms->smbus_enabled; 1524 } 1525 1526 static void pc_machine_set_smbus(Object *obj, bool value, Error **errp) 1527 { 1528 PCMachineState *pcms = PC_MACHINE(obj); 1529 1530 pcms->smbus_enabled = value; 1531 } 1532 1533 static bool pc_machine_get_sata(Object *obj, Error **errp) 1534 { 1535 PCMachineState *pcms = PC_MACHINE(obj); 1536 1537 return pcms->sata_enabled; 1538 } 1539 1540 static void pc_machine_set_sata(Object *obj, bool value, Error **errp) 1541 { 1542 PCMachineState *pcms = PC_MACHINE(obj); 1543 1544 pcms->sata_enabled = value; 1545 } 1546 1547 static bool pc_machine_get_hpet(Object *obj, Error **errp) 1548 { 1549 PCMachineState *pcms = PC_MACHINE(obj); 1550 1551 return pcms->hpet_enabled; 1552 } 1553 1554 static void pc_machine_set_hpet(Object *obj, bool value, Error **errp) 1555 { 1556 PCMachineState *pcms = PC_MACHINE(obj); 1557 1558 pcms->hpet_enabled = value; 1559 } 1560 1561 static bool pc_machine_get_i8042(Object *obj, Error **errp) 1562 { 1563 PCMachineState *pcms = PC_MACHINE(obj); 1564 1565 return pcms->i8042_enabled; 1566 } 1567 1568 static void pc_machine_set_i8042(Object *obj, bool value, Error **errp) 1569 { 1570 PCMachineState *pcms = PC_MACHINE(obj); 1571 1572 pcms->i8042_enabled = value; 1573 } 1574 1575 static bool pc_machine_get_default_bus_bypass_iommu(Object *obj, Error **errp) 1576 { 1577 PCMachineState *pcms = PC_MACHINE(obj); 1578 1579 return pcms->default_bus_bypass_iommu; 1580 } 1581 1582 static void pc_machine_set_default_bus_bypass_iommu(Object *obj, bool value, 1583 Error **errp) 1584 { 1585 PCMachineState *pcms = PC_MACHINE(obj); 1586 1587 pcms->default_bus_bypass_iommu = value; 1588 } 1589 1590 static void pc_machine_get_smbios_ep(Object *obj, Visitor *v, const char *name, 1591 void *opaque, Error **errp) 1592 { 1593 PCMachineState *pcms = PC_MACHINE(obj); 1594 SmbiosEntryPointType smbios_entry_point_type = pcms->smbios_entry_point_type; 1595 1596 visit_type_SmbiosEntryPointType(v, name, &smbios_entry_point_type, errp); 1597 } 1598 1599 static void pc_machine_set_smbios_ep(Object *obj, Visitor *v, const char *name, 1600 void *opaque, Error **errp) 1601 { 1602 PCMachineState *pcms = PC_MACHINE(obj); 1603 1604 visit_type_SmbiosEntryPointType(v, name, &pcms->smbios_entry_point_type, errp); 1605 } 1606 1607 static void pc_machine_get_max_ram_below_4g(Object *obj, Visitor *v, 1608 const char *name, void *opaque, 1609 Error **errp) 1610 { 1611 PCMachineState *pcms = PC_MACHINE(obj); 1612 uint64_t value = pcms->max_ram_below_4g; 1613 1614 visit_type_size(v, name, &value, errp); 1615 } 1616 1617 static void pc_machine_set_max_ram_below_4g(Object *obj, Visitor *v, 1618 const char *name, void *opaque, 1619 Error **errp) 1620 { 1621 PCMachineState *pcms = PC_MACHINE(obj); 1622 uint64_t value; 1623 1624 if (!visit_type_size(v, name, &value, errp)) { 1625 return; 1626 } 1627 if (value > 4 * GiB) { 1628 error_setg(errp, 1629 "Machine option 'max-ram-below-4g=%"PRIu64 1630 "' expects size less than or equal to 4G", value); 1631 return; 1632 } 1633 1634 if (value < 1 * MiB) { 1635 warn_report("Only %" PRIu64 " bytes of RAM below the 4GiB boundary," 1636 "BIOS may not work with less than 1MiB", value); 1637 } 1638 1639 pcms->max_ram_below_4g = value; 1640 } 1641 1642 static void pc_machine_get_max_fw_size(Object *obj, Visitor *v, 1643 const char *name, void *opaque, 1644 Error **errp) 1645 { 1646 PCMachineState *pcms = PC_MACHINE(obj); 1647 uint64_t value = pcms->max_fw_size; 1648 1649 visit_type_size(v, name, &value, errp); 1650 } 1651 1652 static void pc_machine_set_max_fw_size(Object *obj, Visitor *v, 1653 const char *name, void *opaque, 1654 Error **errp) 1655 { 1656 PCMachineState *pcms = PC_MACHINE(obj); 1657 uint64_t value; 1658 1659 if (!visit_type_size(v, name, &value, errp)) { 1660 return; 1661 } 1662 1663 /* 1664 * We don't have a theoretically justifiable exact lower bound on the base 1665 * address of any flash mapping. In practice, the IO-APIC MMIO range is 1666 * [0xFEE00000..0xFEE01000] -- see IO_APIC_DEFAULT_ADDRESS --, leaving free 1667 * only 18MiB-4KiB below 4GiB. For now, restrict the cumulative mapping to 1668 * 16MiB in size. 1669 */ 1670 if (value > 16 * MiB) { 1671 error_setg(errp, 1672 "User specified max allowed firmware size %" PRIu64 " is " 1673 "greater than 16MiB. If combined firmware size exceeds " 1674 "16MiB the system may not boot, or experience intermittent" 1675 "stability issues.", 1676 value); 1677 return; 1678 } 1679 1680 pcms->max_fw_size = value; 1681 } 1682 1683 1684 static void pc_machine_initfn(Object *obj) 1685 { 1686 PCMachineState *pcms = PC_MACHINE(obj); 1687 PCMachineClass *pcmc = PC_MACHINE_GET_CLASS(pcms); 1688 1689 #ifdef CONFIG_VMPORT 1690 pcms->vmport = ON_OFF_AUTO_AUTO; 1691 #else 1692 pcms->vmport = ON_OFF_AUTO_OFF; 1693 #endif /* CONFIG_VMPORT */ 1694 pcms->max_ram_below_4g = 0; /* use default */ 1695 pcms->smbios_entry_point_type = pcmc->default_smbios_ep_type; 1696 pcms->south_bridge = pcmc->default_south_bridge; 1697 1698 /* acpi build is enabled by default if machine supports it */ 1699 pcms->acpi_build_enabled = pcmc->has_acpi_build; 1700 pcms->smbus_enabled = true; 1701 pcms->sata_enabled = true; 1702 pcms->i8042_enabled = true; 1703 pcms->max_fw_size = 8 * MiB; 1704 #if defined(CONFIG_HPET) || defined(CONFIG_X_HPET_RUST) 1705 pcms->hpet_enabled = true; 1706 #endif 1707 pcms->fd_bootchk = true; 1708 pcms->default_bus_bypass_iommu = false; 1709 1710 pc_system_flash_create(pcms); 1711 pcms->pcspk = isa_new(TYPE_PC_SPEAKER); 1712 object_property_add_alias(OBJECT(pcms), "pcspk-audiodev", 1713 OBJECT(pcms->pcspk), "audiodev"); 1714 if (pcmc->pci_enabled) { 1715 cxl_machine_init(obj, &pcms->cxl_devices_state); 1716 } 1717 1718 pcms->machine_done.notify = pc_machine_done; 1719 qemu_add_machine_init_done_notifier(&pcms->machine_done); 1720 } 1721 1722 static void pc_machine_reset(MachineState *machine, ResetType type) 1723 { 1724 CPUState *cs; 1725 X86CPU *cpu; 1726 1727 qemu_devices_reset(type); 1728 1729 /* Reset APIC after devices have been reset to cancel 1730 * any changes that qemu_devices_reset() might have done. 1731 */ 1732 CPU_FOREACH(cs) { 1733 cpu = X86_CPU(cs); 1734 1735 x86_cpu_after_reset(cpu); 1736 } 1737 } 1738 1739 static void pc_machine_wakeup(MachineState *machine) 1740 { 1741 cpu_synchronize_all_states(); 1742 pc_machine_reset(machine, RESET_TYPE_WAKEUP); 1743 cpu_synchronize_all_post_reset(); 1744 } 1745 1746 static bool pc_hotplug_allowed(MachineState *ms, DeviceState *dev, Error **errp) 1747 { 1748 X86IOMMUState *iommu = x86_iommu_get_default(); 1749 IntelIOMMUState *intel_iommu; 1750 1751 if (iommu && 1752 object_dynamic_cast((Object *)iommu, TYPE_INTEL_IOMMU_DEVICE) && 1753 object_dynamic_cast((Object *)dev, "vfio-pci")) { 1754 intel_iommu = INTEL_IOMMU_DEVICE(iommu); 1755 if (!intel_iommu->caching_mode) { 1756 error_setg(errp, "Device assignment is not allowed without " 1757 "enabling caching-mode=on for Intel IOMMU."); 1758 return false; 1759 } 1760 } 1761 1762 return true; 1763 } 1764 1765 static void pc_machine_class_init(ObjectClass *oc, void *data) 1766 { 1767 MachineClass *mc = MACHINE_CLASS(oc); 1768 X86MachineClass *x86mc = X86_MACHINE_CLASS(oc); 1769 PCMachineClass *pcmc = PC_MACHINE_CLASS(oc); 1770 HotplugHandlerClass *hc = HOTPLUG_HANDLER_CLASS(oc); 1771 1772 pcmc->pci_enabled = true; 1773 pcmc->has_acpi_build = true; 1774 pcmc->smbios_defaults = true; 1775 pcmc->gigabyte_align = true; 1776 pcmc->has_reserved_memory = true; 1777 pcmc->enforce_amd_1tb_hole = true; 1778 pcmc->isa_bios_alias = true; 1779 pcmc->pvh_enabled = true; 1780 pcmc->kvmclock_create_always = true; 1781 x86mc->apic_xrupt_override = true; 1782 assert(!mc->get_hotplug_handler); 1783 mc->get_hotplug_handler = pc_get_hotplug_handler; 1784 mc->hotplug_allowed = pc_hotplug_allowed; 1785 mc->auto_enable_numa_with_memhp = true; 1786 mc->auto_enable_numa_with_memdev = true; 1787 mc->has_hotpluggable_cpus = true; 1788 mc->default_boot_order = "cad"; 1789 mc->block_default_type = IF_IDE; 1790 mc->max_cpus = 255; 1791 mc->reset = pc_machine_reset; 1792 mc->wakeup = pc_machine_wakeup; 1793 hc->pre_plug = pc_machine_device_pre_plug_cb; 1794 hc->plug = pc_machine_device_plug_cb; 1795 hc->unplug_request = pc_machine_device_unplug_request_cb; 1796 hc->unplug = pc_machine_device_unplug_cb; 1797 mc->default_cpu_type = TARGET_DEFAULT_CPU_TYPE; 1798 mc->nvdimm_supported = true; 1799 mc->smp_props.dies_supported = true; 1800 mc->smp_props.modules_supported = true; 1801 mc->default_ram_id = "pc.ram"; 1802 pcmc->default_smbios_ep_type = SMBIOS_ENTRY_POINT_TYPE_AUTO; 1803 1804 object_class_property_add(oc, PC_MACHINE_MAX_RAM_BELOW_4G, "size", 1805 pc_machine_get_max_ram_below_4g, pc_machine_set_max_ram_below_4g, 1806 NULL, NULL); 1807 object_class_property_set_description(oc, PC_MACHINE_MAX_RAM_BELOW_4G, 1808 "Maximum ram below the 4G boundary (32bit boundary)"); 1809 1810 object_class_property_add(oc, PC_MACHINE_VMPORT, "OnOffAuto", 1811 pc_machine_get_vmport, pc_machine_set_vmport, 1812 NULL, NULL); 1813 object_class_property_set_description(oc, PC_MACHINE_VMPORT, 1814 "Enable vmport (pc & q35)"); 1815 1816 object_class_property_add_bool(oc, PC_MACHINE_SMBUS, 1817 pc_machine_get_smbus, pc_machine_set_smbus); 1818 object_class_property_set_description(oc, PC_MACHINE_SMBUS, 1819 "Enable/disable system management bus"); 1820 1821 object_class_property_add_bool(oc, PC_MACHINE_SATA, 1822 pc_machine_get_sata, pc_machine_set_sata); 1823 object_class_property_set_description(oc, PC_MACHINE_SATA, 1824 "Enable/disable Serial ATA bus"); 1825 1826 object_class_property_add_bool(oc, "hpet", 1827 pc_machine_get_hpet, pc_machine_set_hpet); 1828 object_class_property_set_description(oc, "hpet", 1829 "Enable/disable high precision event timer emulation"); 1830 1831 object_class_property_add_bool(oc, PC_MACHINE_I8042, 1832 pc_machine_get_i8042, pc_machine_set_i8042); 1833 object_class_property_set_description(oc, PC_MACHINE_I8042, 1834 "Enable/disable Intel 8042 PS/2 controller emulation"); 1835 1836 object_class_property_add_bool(oc, "default-bus-bypass-iommu", 1837 pc_machine_get_default_bus_bypass_iommu, 1838 pc_machine_set_default_bus_bypass_iommu); 1839 1840 object_class_property_add(oc, PC_MACHINE_MAX_FW_SIZE, "size", 1841 pc_machine_get_max_fw_size, pc_machine_set_max_fw_size, 1842 NULL, NULL); 1843 object_class_property_set_description(oc, PC_MACHINE_MAX_FW_SIZE, 1844 "Maximum combined firmware size"); 1845 1846 object_class_property_add(oc, PC_MACHINE_SMBIOS_EP, "str", 1847 pc_machine_get_smbios_ep, pc_machine_set_smbios_ep, 1848 NULL, NULL); 1849 object_class_property_set_description(oc, PC_MACHINE_SMBIOS_EP, 1850 "SMBIOS Entry Point type [32, 64]"); 1851 1852 object_class_property_add_bool(oc, "fd-bootchk", 1853 pc_machine_get_fd_bootchk, 1854 pc_machine_set_fd_bootchk); 1855 } 1856 1857 static const TypeInfo pc_machine_info = { 1858 .name = TYPE_PC_MACHINE, 1859 .parent = TYPE_X86_MACHINE, 1860 .abstract = true, 1861 .instance_size = sizeof(PCMachineState), 1862 .instance_init = pc_machine_initfn, 1863 .class_size = sizeof(PCMachineClass), 1864 .class_init = pc_machine_class_init, 1865 .interfaces = (InterfaceInfo[]) { 1866 { TYPE_HOTPLUG_HANDLER }, 1867 { } 1868 }, 1869 }; 1870 1871 static void pc_machine_register_types(void) 1872 { 1873 type_register_static(&pc_machine_info); 1874 } 1875 1876 type_init(pc_machine_register_types) 1877