1 /* 2 * QEMU PC System Emulator 3 * 4 * Copyright (c) 2003-2004 Fabrice Bellard 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a copy 7 * of this software and associated documentation files (the "Software"), to deal 8 * in the Software without restriction, including without limitation the rights 9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 10 * copies of the Software, and to permit persons to whom the Software is 11 * furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice shall be included in 14 * all copies or substantial portions of the Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN 22 * THE SOFTWARE. 23 */ 24 25 #include "qemu/osdep.h" 26 #include "qemu/units.h" 27 #include "hw/i386/pc.h" 28 #include "hw/char/serial-isa.h" 29 #include "hw/char/parallel.h" 30 #include "hw/hyperv/hv-balloon.h" 31 #include "hw/i386/fw_cfg.h" 32 #include "hw/i386/vmport.h" 33 #include "system/cpus.h" 34 #include "hw/ide/ide-bus.h" 35 #include "hw/timer/hpet.h" 36 #include "hw/loader.h" 37 #include "hw/rtc/mc146818rtc.h" 38 #include "hw/intc/i8259.h" 39 #include "hw/timer/i8254.h" 40 #include "hw/input/i8042.h" 41 #include "hw/audio/pcspk.h" 42 #include "system/system.h" 43 #include "system/xen.h" 44 #include "system/reset.h" 45 #include "kvm/kvm_i386.h" 46 #include "hw/xen/xen.h" 47 #include "qobject/qlist.h" 48 #include "qemu/error-report.h" 49 #include "hw/acpi/cpu_hotplug.h" 50 #include "acpi-build.h" 51 #include "hw/mem/nvdimm.h" 52 #include "hw/cxl/cxl_host.h" 53 #include "hw/usb.h" 54 #include "hw/i386/intel_iommu.h" 55 #include "hw/net/ne2000-isa.h" 56 #include "hw/virtio/virtio-iommu.h" 57 #include "hw/virtio/virtio-md-pci.h" 58 #include "hw/i386/kvm/xen_overlay.h" 59 #include "hw/i386/kvm/xen_evtchn.h" 60 #include "hw/i386/kvm/xen_gnttab.h" 61 #include "hw/i386/kvm/xen_xenstore.h" 62 #include "hw/mem/memory-device.h" 63 #include "e820_memory_layout.h" 64 #include "trace.h" 65 #include "sev.h" 66 #include CONFIG_DEVICES 67 68 #ifdef CONFIG_XEN_EMU 69 #include "hw/xen/xen-legacy-backend.h" 70 #include "hw/xen/xen-bus.h" 71 #endif 72 73 /* 74 * Helper for setting model-id for CPU models that changed model-id 75 * depending on QEMU versions up to QEMU 2.4. 76 */ 77 #define PC_CPU_MODEL_IDS(v) \ 78 { "qemu32-" TYPE_X86_CPU, "model-id", "QEMU Virtual CPU version " v, },\ 79 { "qemu64-" TYPE_X86_CPU, "model-id", "QEMU Virtual CPU version " v, },\ 80 { "athlon-" TYPE_X86_CPU, "model-id", "QEMU Virtual CPU version " v, }, 81 82 GlobalProperty pc_compat_10_0[] = {}; 83 const size_t pc_compat_10_0_len = G_N_ELEMENTS(pc_compat_10_0); 84 85 GlobalProperty pc_compat_9_2[] = {}; 86 const size_t pc_compat_9_2_len = G_N_ELEMENTS(pc_compat_9_2); 87 88 GlobalProperty pc_compat_9_1[] = { 89 { "ICH9-LPC", "x-smi-swsmi-timer", "off" }, 90 { "ICH9-LPC", "x-smi-periodic-timer", "off" }, 91 { TYPE_INTEL_IOMMU_DEVICE, "stale-tm", "on" }, 92 { TYPE_INTEL_IOMMU_DEVICE, "aw-bits", "39" }, 93 }; 94 const size_t pc_compat_9_1_len = G_N_ELEMENTS(pc_compat_9_1); 95 96 GlobalProperty pc_compat_9_0[] = { 97 { TYPE_X86_CPU, "x-amd-topoext-features-only", "false" }, 98 { TYPE_X86_CPU, "x-l1-cache-per-thread", "false" }, 99 { TYPE_X86_CPU, "guest-phys-bits", "0" }, 100 { "sev-guest", "legacy-vm-type", "on" }, 101 { TYPE_X86_CPU, "legacy-multi-node", "on" }, 102 }; 103 const size_t pc_compat_9_0_len = G_N_ELEMENTS(pc_compat_9_0); 104 105 GlobalProperty pc_compat_8_2[] = {}; 106 const size_t pc_compat_8_2_len = G_N_ELEMENTS(pc_compat_8_2); 107 108 GlobalProperty pc_compat_8_1[] = {}; 109 const size_t pc_compat_8_1_len = G_N_ELEMENTS(pc_compat_8_1); 110 111 GlobalProperty pc_compat_8_0[] = { 112 { "virtio-mem", "unplugged-inaccessible", "auto" }, 113 }; 114 const size_t pc_compat_8_0_len = G_N_ELEMENTS(pc_compat_8_0); 115 116 GlobalProperty pc_compat_7_2[] = { 117 { "ICH9-LPC", "noreboot", "true" }, 118 }; 119 const size_t pc_compat_7_2_len = G_N_ELEMENTS(pc_compat_7_2); 120 121 GlobalProperty pc_compat_7_1[] = {}; 122 const size_t pc_compat_7_1_len = G_N_ELEMENTS(pc_compat_7_1); 123 124 GlobalProperty pc_compat_7_0[] = {}; 125 const size_t pc_compat_7_0_len = G_N_ELEMENTS(pc_compat_7_0); 126 127 GlobalProperty pc_compat_6_2[] = { 128 { "virtio-mem", "unplugged-inaccessible", "off" }, 129 }; 130 const size_t pc_compat_6_2_len = G_N_ELEMENTS(pc_compat_6_2); 131 132 GlobalProperty pc_compat_6_1[] = { 133 { TYPE_X86_CPU, "hv-version-id-build", "0x1bbc" }, 134 { TYPE_X86_CPU, "hv-version-id-major", "0x0006" }, 135 { TYPE_X86_CPU, "hv-version-id-minor", "0x0001" }, 136 { "ICH9-LPC", "x-keep-pci-slot-hpc", "false" }, 137 }; 138 const size_t pc_compat_6_1_len = G_N_ELEMENTS(pc_compat_6_1); 139 140 GlobalProperty pc_compat_6_0[] = { 141 { "qemu64" "-" TYPE_X86_CPU, "family", "6" }, 142 { "qemu64" "-" TYPE_X86_CPU, "model", "6" }, 143 { "qemu64" "-" TYPE_X86_CPU, "stepping", "3" }, 144 { TYPE_X86_CPU, "x-vendor-cpuid-only", "off" }, 145 { "ICH9-LPC", ACPI_PM_PROP_ACPI_PCIHP_BRIDGE, "off" }, 146 { "ICH9-LPC", "x-keep-pci-slot-hpc", "true" }, 147 }; 148 const size_t pc_compat_6_0_len = G_N_ELEMENTS(pc_compat_6_0); 149 150 GlobalProperty pc_compat_5_2[] = { 151 { "ICH9-LPC", "x-smi-cpu-hotunplug", "off" }, 152 }; 153 const size_t pc_compat_5_2_len = G_N_ELEMENTS(pc_compat_5_2); 154 155 GlobalProperty pc_compat_5_1[] = { 156 { "ICH9-LPC", "x-smi-cpu-hotplug", "off" }, 157 { TYPE_X86_CPU, "kvm-msi-ext-dest-id", "off" }, 158 }; 159 const size_t pc_compat_5_1_len = G_N_ELEMENTS(pc_compat_5_1); 160 161 GlobalProperty pc_compat_5_0[] = { 162 }; 163 const size_t pc_compat_5_0_len = G_N_ELEMENTS(pc_compat_5_0); 164 165 GlobalProperty pc_compat_4_2[] = { 166 { "mch", "smbase-smram", "off" }, 167 }; 168 const size_t pc_compat_4_2_len = G_N_ELEMENTS(pc_compat_4_2); 169 170 GlobalProperty pc_compat_4_1[] = {}; 171 const size_t pc_compat_4_1_len = G_N_ELEMENTS(pc_compat_4_1); 172 173 GlobalProperty pc_compat_4_0[] = {}; 174 const size_t pc_compat_4_0_len = G_N_ELEMENTS(pc_compat_4_0); 175 176 GlobalProperty pc_compat_3_1[] = { 177 { "intel-iommu", "dma-drain", "off" }, 178 { "Opteron_G3" "-" TYPE_X86_CPU, "rdtscp", "off" }, 179 { "Opteron_G4" "-" TYPE_X86_CPU, "rdtscp", "off" }, 180 { "Opteron_G4" "-" TYPE_X86_CPU, "npt", "off" }, 181 { "Opteron_G4" "-" TYPE_X86_CPU, "nrip-save", "off" }, 182 { "Opteron_G5" "-" TYPE_X86_CPU, "rdtscp", "off" }, 183 { "Opteron_G5" "-" TYPE_X86_CPU, "npt", "off" }, 184 { "Opteron_G5" "-" TYPE_X86_CPU, "nrip-save", "off" }, 185 { "EPYC" "-" TYPE_X86_CPU, "npt", "off" }, 186 { "EPYC" "-" TYPE_X86_CPU, "nrip-save", "off" }, 187 { "EPYC-IBPB" "-" TYPE_X86_CPU, "npt", "off" }, 188 { "EPYC-IBPB" "-" TYPE_X86_CPU, "nrip-save", "off" }, 189 { "Skylake-Client" "-" TYPE_X86_CPU, "mpx", "on" }, 190 { "Skylake-Client-IBRS" "-" TYPE_X86_CPU, "mpx", "on" }, 191 { "Skylake-Server" "-" TYPE_X86_CPU, "mpx", "on" }, 192 { "Skylake-Server-IBRS" "-" TYPE_X86_CPU, "mpx", "on" }, 193 { "Cascadelake-Server" "-" TYPE_X86_CPU, "mpx", "on" }, 194 { "Icelake-Client" "-" TYPE_X86_CPU, "mpx", "on" }, 195 { "Icelake-Server" "-" TYPE_X86_CPU, "mpx", "on" }, 196 { "Cascadelake-Server" "-" TYPE_X86_CPU, "stepping", "5" }, 197 { TYPE_X86_CPU, "x-intel-pt-auto-level", "off" }, 198 }; 199 const size_t pc_compat_3_1_len = G_N_ELEMENTS(pc_compat_3_1); 200 201 GlobalProperty pc_compat_3_0[] = { 202 { TYPE_X86_CPU, "x-hv-synic-kvm-only", "on" }, 203 { "Skylake-Server" "-" TYPE_X86_CPU, "pku", "off" }, 204 { "Skylake-Server-IBRS" "-" TYPE_X86_CPU, "pku", "off" }, 205 }; 206 const size_t pc_compat_3_0_len = G_N_ELEMENTS(pc_compat_3_0); 207 208 GlobalProperty pc_compat_2_12[] = { 209 { TYPE_X86_CPU, "legacy-cache", "on" }, 210 { TYPE_X86_CPU, "topoext", "off" }, 211 { "EPYC-" TYPE_X86_CPU, "xlevel", "0x8000000a" }, 212 { "EPYC-IBPB-" TYPE_X86_CPU, "xlevel", "0x8000000a" }, 213 }; 214 const size_t pc_compat_2_12_len = G_N_ELEMENTS(pc_compat_2_12); 215 216 GlobalProperty pc_compat_2_11[] = { 217 { TYPE_X86_CPU, "x-migrate-smi-count", "off" }, 218 { "Skylake-Server" "-" TYPE_X86_CPU, "clflushopt", "off" }, 219 }; 220 const size_t pc_compat_2_11_len = G_N_ELEMENTS(pc_compat_2_11); 221 222 GlobalProperty pc_compat_2_10[] = { 223 { TYPE_X86_CPU, "x-hv-max-vps", "0x40" }, 224 { "i440FX-pcihost", "x-pci-hole64-fix", "off" }, 225 { "q35-pcihost", "x-pci-hole64-fix", "off" }, 226 }; 227 const size_t pc_compat_2_10_len = G_N_ELEMENTS(pc_compat_2_10); 228 229 GlobalProperty pc_compat_2_9[] = { 230 { "mch", "extended-tseg-mbytes", "0" }, 231 }; 232 const size_t pc_compat_2_9_len = G_N_ELEMENTS(pc_compat_2_9); 233 234 GlobalProperty pc_compat_2_8[] = { 235 { TYPE_X86_CPU, "tcg-cpuid", "off" }, 236 { "kvmclock", "x-mach-use-reliable-get-clock", "off" }, 237 { "ICH9-LPC", "x-smi-broadcast", "off" }, 238 { TYPE_X86_CPU, "vmware-cpuid-freq", "off" }, 239 { "Haswell-" TYPE_X86_CPU, "stepping", "1" }, 240 }; 241 const size_t pc_compat_2_8_len = G_N_ELEMENTS(pc_compat_2_8); 242 243 GlobalProperty pc_compat_2_7[] = { 244 { TYPE_X86_CPU, "l3-cache", "off" }, 245 { TYPE_X86_CPU, "full-cpuid-auto-level", "off" }, 246 { "Opteron_G3" "-" TYPE_X86_CPU, "family", "15" }, 247 { "Opteron_G3" "-" TYPE_X86_CPU, "model", "6" }, 248 { "Opteron_G3" "-" TYPE_X86_CPU, "stepping", "1" }, 249 { "isa-pcspk", "migrate", "off" }, 250 }; 251 const size_t pc_compat_2_7_len = G_N_ELEMENTS(pc_compat_2_7); 252 253 GlobalProperty pc_compat_2_6[] = { 254 { TYPE_X86_CPU, "cpuid-0xb", "off" }, 255 { "vmxnet3", "romfile", "" }, 256 { TYPE_X86_CPU, "fill-mtrr-mask", "off" }, 257 { "apic-common", "legacy-instance-id", "on", } 258 }; 259 const size_t pc_compat_2_6_len = G_N_ELEMENTS(pc_compat_2_6); 260 261 GlobalProperty pc_compat_2_5[] = {}; 262 const size_t pc_compat_2_5_len = G_N_ELEMENTS(pc_compat_2_5); 263 264 GlobalProperty pc_compat_2_4[] = { 265 PC_CPU_MODEL_IDS("2.4.0") 266 { "Haswell-" TYPE_X86_CPU, "abm", "off" }, 267 { "Haswell-noTSX-" TYPE_X86_CPU, "abm", "off" }, 268 { "Broadwell-" TYPE_X86_CPU, "abm", "off" }, 269 { "Broadwell-noTSX-" TYPE_X86_CPU, "abm", "off" }, 270 { "host" "-" TYPE_X86_CPU, "host-cache-info", "on" }, 271 { TYPE_X86_CPU, "check", "off" }, 272 { "qemu64" "-" TYPE_X86_CPU, "sse4a", "on" }, 273 { "qemu64" "-" TYPE_X86_CPU, "abm", "on" }, 274 { "qemu64" "-" TYPE_X86_CPU, "popcnt", "on" }, 275 { "qemu32" "-" TYPE_X86_CPU, "popcnt", "on" }, 276 { "Opteron_G2" "-" TYPE_X86_CPU, "rdtscp", "on" }, 277 { "Opteron_G3" "-" TYPE_X86_CPU, "rdtscp", "on" }, 278 { "Opteron_G4" "-" TYPE_X86_CPU, "rdtscp", "on" }, 279 { "Opteron_G5" "-" TYPE_X86_CPU, "rdtscp", "on", } 280 }; 281 const size_t pc_compat_2_4_len = G_N_ELEMENTS(pc_compat_2_4); 282 283 /* 284 * @PC_FW_DATA: 285 * Size of the chunk of memory at the top of RAM for the BIOS ACPI tables 286 * and other BIOS datastructures. 287 * 288 * BIOS ACPI tables: 128K. Other BIOS datastructures: less than 4K 289 * reported to be used at the moment, 32K should be enough for a while. 290 */ 291 #define PC_FW_DATA (0x20000 + 0x8000) 292 293 GSIState *pc_gsi_create(qemu_irq **irqs, bool pci_enabled) 294 { 295 GSIState *s; 296 297 s = g_new0(GSIState, 1); 298 if (kvm_ioapic_in_kernel()) { 299 kvm_pc_setup_irq_routing(pci_enabled); 300 } 301 *irqs = qemu_allocate_irqs(gsi_handler, s, IOAPIC_NUM_PINS); 302 303 return s; 304 } 305 306 static void ioport80_write(void *opaque, hwaddr addr, uint64_t data, 307 unsigned size) 308 { 309 } 310 311 static uint64_t ioport80_read(void *opaque, hwaddr addr, unsigned size) 312 { 313 return 0xffffffffffffffffULL; 314 } 315 316 /* MS-DOS compatibility mode FPU exception support */ 317 static void ioportF0_write(void *opaque, hwaddr addr, uint64_t data, 318 unsigned size) 319 { 320 if (tcg_enabled()) { 321 cpu_set_ignne(); 322 } 323 } 324 325 static uint64_t ioportF0_read(void *opaque, hwaddr addr, unsigned size) 326 { 327 return 0xffffffffffffffffULL; 328 } 329 330 /* PC cmos mappings */ 331 332 #define REG_EQUIPMENT_BYTE 0x14 333 334 static void cmos_init_hd(MC146818RtcState *s, int type_ofs, int info_ofs, 335 int16_t cylinders, int8_t heads, int8_t sectors) 336 { 337 mc146818rtc_set_cmos_data(s, type_ofs, 47); 338 mc146818rtc_set_cmos_data(s, info_ofs, cylinders); 339 mc146818rtc_set_cmos_data(s, info_ofs + 1, cylinders >> 8); 340 mc146818rtc_set_cmos_data(s, info_ofs + 2, heads); 341 mc146818rtc_set_cmos_data(s, info_ofs + 3, 0xff); 342 mc146818rtc_set_cmos_data(s, info_ofs + 4, 0xff); 343 mc146818rtc_set_cmos_data(s, info_ofs + 5, 0xc0 | ((heads > 8) << 3)); 344 mc146818rtc_set_cmos_data(s, info_ofs + 6, cylinders); 345 mc146818rtc_set_cmos_data(s, info_ofs + 7, cylinders >> 8); 346 mc146818rtc_set_cmos_data(s, info_ofs + 8, sectors); 347 } 348 349 /* convert boot_device letter to something recognizable by the bios */ 350 static int boot_device2nibble(char boot_device) 351 { 352 switch(boot_device) { 353 case 'a': 354 case 'b': 355 return 0x01; /* floppy boot */ 356 case 'c': 357 return 0x02; /* hard drive boot */ 358 case 'd': 359 return 0x03; /* CD-ROM boot */ 360 case 'n': 361 return 0x04; /* Network boot */ 362 } 363 return 0; 364 } 365 366 static void set_boot_dev(PCMachineState *pcms, MC146818RtcState *s, 367 const char *boot_device, Error **errp) 368 { 369 #define PC_MAX_BOOT_DEVICES 3 370 int nbds, bds[3] = { 0, }; 371 int i; 372 373 nbds = strlen(boot_device); 374 if (nbds > PC_MAX_BOOT_DEVICES) { 375 error_setg(errp, "Too many boot devices for PC"); 376 return; 377 } 378 for (i = 0; i < nbds; i++) { 379 bds[i] = boot_device2nibble(boot_device[i]); 380 if (bds[i] == 0) { 381 error_setg(errp, "Invalid boot device for PC: '%c'", 382 boot_device[i]); 383 return; 384 } 385 } 386 mc146818rtc_set_cmos_data(s, 0x3d, (bds[1] << 4) | bds[0]); 387 mc146818rtc_set_cmos_data(s, 0x38, (bds[2] << 4) | !pcms->fd_bootchk); 388 } 389 390 static void pc_boot_set(void *opaque, const char *boot_device, Error **errp) 391 { 392 PCMachineState *pcms = opaque; 393 X86MachineState *x86ms = X86_MACHINE(pcms); 394 395 set_boot_dev(pcms, MC146818_RTC(x86ms->rtc), boot_device, errp); 396 } 397 398 static void pc_cmos_init_floppy(MC146818RtcState *rtc_state, ISADevice *floppy) 399 { 400 int val, nb; 401 FloppyDriveType fd_type[2] = { FLOPPY_DRIVE_TYPE_NONE, 402 FLOPPY_DRIVE_TYPE_NONE }; 403 404 #ifdef CONFIG_FDC_ISA 405 /* floppy type */ 406 if (floppy) { 407 for (int i = 0; i < 2; i++) { 408 fd_type[i] = isa_fdc_get_drive_type(floppy, i); 409 } 410 } 411 #endif 412 413 val = (cmos_get_fd_drive_type(fd_type[0]) << 4) | 414 cmos_get_fd_drive_type(fd_type[1]); 415 mc146818rtc_set_cmos_data(rtc_state, 0x10, val); 416 417 val = mc146818rtc_get_cmos_data(rtc_state, REG_EQUIPMENT_BYTE); 418 nb = 0; 419 if (fd_type[0] != FLOPPY_DRIVE_TYPE_NONE) { 420 nb++; 421 } 422 if (fd_type[1] != FLOPPY_DRIVE_TYPE_NONE) { 423 nb++; 424 } 425 switch (nb) { 426 case 0: 427 break; 428 case 1: 429 val |= 0x01; /* 1 drive, ready for boot */ 430 break; 431 case 2: 432 val |= 0x41; /* 2 drives, ready for boot */ 433 break; 434 } 435 mc146818rtc_set_cmos_data(rtc_state, REG_EQUIPMENT_BYTE, val); 436 } 437 438 typedef struct check_fdc_state { 439 ISADevice *floppy; 440 bool multiple; 441 } CheckFdcState; 442 443 static int check_fdc(Object *obj, void *opaque) 444 { 445 CheckFdcState *state = opaque; 446 Object *fdc; 447 uint32_t iobase; 448 Error *local_err = NULL; 449 450 fdc = object_dynamic_cast(obj, TYPE_ISA_FDC); 451 if (!fdc) { 452 return 0; 453 } 454 455 iobase = object_property_get_uint(obj, "iobase", &local_err); 456 if (local_err || iobase != 0x3f0) { 457 error_free(local_err); 458 return 0; 459 } 460 461 if (state->floppy) { 462 state->multiple = true; 463 } else { 464 state->floppy = ISA_DEVICE(obj); 465 } 466 return 0; 467 } 468 469 static const char * const fdc_container_path[] = { 470 "unattached", "peripheral", "peripheral-anon" 471 }; 472 473 /* 474 * Locate the FDC at IO address 0x3f0, in order to configure the CMOS registers 475 * and ACPI objects. 476 */ 477 static ISADevice *pc_find_fdc0(void) 478 { 479 int i; 480 Object *container; 481 CheckFdcState state = { 0 }; 482 483 for (i = 0; i < ARRAY_SIZE(fdc_container_path); i++) { 484 container = machine_get_container(fdc_container_path[i]); 485 object_child_foreach(container, check_fdc, &state); 486 } 487 488 if (state.multiple) { 489 warn_report("multiple floppy disk controllers with " 490 "iobase=0x3f0 have been found"); 491 error_printf("the one being picked for CMOS setup might not reflect " 492 "your intent"); 493 } 494 495 return state.floppy; 496 } 497 498 static void pc_cmos_init_late(PCMachineState *pcms) 499 { 500 X86MachineState *x86ms = X86_MACHINE(pcms); 501 MC146818RtcState *s = MC146818_RTC(x86ms->rtc); 502 int16_t cylinders; 503 int8_t heads, sectors; 504 int val; 505 int i, trans; 506 507 val = 0; 508 if (pcms->idebus[0] && 509 ide_get_geometry(pcms->idebus[0], 0, 510 &cylinders, &heads, §ors) >= 0) { 511 cmos_init_hd(s, 0x19, 0x1b, cylinders, heads, sectors); 512 val |= 0xf0; 513 } 514 if (pcms->idebus[0] && 515 ide_get_geometry(pcms->idebus[0], 1, 516 &cylinders, &heads, §ors) >= 0) { 517 cmos_init_hd(s, 0x1a, 0x24, cylinders, heads, sectors); 518 val |= 0x0f; 519 } 520 mc146818rtc_set_cmos_data(s, 0x12, val); 521 522 val = 0; 523 for (i = 0; i < 4; i++) { 524 /* NOTE: ide_get_geometry() returns the physical 525 geometry. It is always such that: 1 <= sects <= 63, 1 526 <= heads <= 16, 1 <= cylinders <= 16383. The BIOS 527 geometry can be different if a translation is done. */ 528 BusState *idebus = pcms->idebus[i / 2]; 529 if (idebus && 530 ide_get_geometry(idebus, i % 2, 531 &cylinders, &heads, §ors) >= 0) { 532 trans = ide_get_bios_chs_trans(idebus, i % 2) - 1; 533 assert((trans & ~3) == 0); 534 val |= trans << (i * 2); 535 } 536 } 537 mc146818rtc_set_cmos_data(s, 0x39, val); 538 539 pc_cmos_init_floppy(s, pc_find_fdc0()); 540 541 /* various important CMOS locations needed by PC/Bochs bios */ 542 543 /* memory size */ 544 /* base memory (first MiB) */ 545 val = MIN(x86ms->below_4g_mem_size / KiB, 640); 546 mc146818rtc_set_cmos_data(s, 0x15, val); 547 mc146818rtc_set_cmos_data(s, 0x16, val >> 8); 548 /* extended memory (next 64MiB) */ 549 if (x86ms->below_4g_mem_size > 1 * MiB) { 550 val = (x86ms->below_4g_mem_size - 1 * MiB) / KiB; 551 } else { 552 val = 0; 553 } 554 if (val > 65535) 555 val = 65535; 556 mc146818rtc_set_cmos_data(s, 0x17, val); 557 mc146818rtc_set_cmos_data(s, 0x18, val >> 8); 558 mc146818rtc_set_cmos_data(s, 0x30, val); 559 mc146818rtc_set_cmos_data(s, 0x31, val >> 8); 560 /* memory between 16MiB and 4GiB */ 561 if (x86ms->below_4g_mem_size > 16 * MiB) { 562 val = (x86ms->below_4g_mem_size - 16 * MiB) / (64 * KiB); 563 } else { 564 val = 0; 565 } 566 if (val > 65535) 567 val = 65535; 568 mc146818rtc_set_cmos_data(s, 0x34, val); 569 mc146818rtc_set_cmos_data(s, 0x35, val >> 8); 570 /* memory above 4GiB */ 571 val = x86ms->above_4g_mem_size / 65536; 572 mc146818rtc_set_cmos_data(s, 0x5b, val); 573 mc146818rtc_set_cmos_data(s, 0x5c, val >> 8); 574 mc146818rtc_set_cmos_data(s, 0x5d, val >> 16); 575 576 val = 0; 577 val |= 0x02; /* FPU is there */ 578 val |= 0x04; /* PS/2 mouse installed */ 579 mc146818rtc_set_cmos_data(s, REG_EQUIPMENT_BYTE, val); 580 } 581 582 static void handle_a20_line_change(void *opaque, int irq, int level) 583 { 584 X86CPU *cpu = opaque; 585 586 /* XXX: send to all CPUs ? */ 587 /* XXX: add logic to handle multiple A20 line sources */ 588 x86_cpu_set_a20(cpu, level); 589 } 590 591 #define NE2000_NB_MAX 6 592 593 static const int ne2000_io[NE2000_NB_MAX] = { 0x300, 0x320, 0x340, 0x360, 594 0x280, 0x380 }; 595 static const int ne2000_irq[NE2000_NB_MAX] = { 9, 10, 11, 3, 4, 5 }; 596 597 static gboolean pc_init_ne2k_isa(ISABus *bus, NICInfo *nd, Error **errp) 598 { 599 static int nb_ne2k = 0; 600 601 if (nb_ne2k == NE2000_NB_MAX) { 602 error_setg(errp, 603 "maximum number of ISA NE2000 devices exceeded"); 604 return false; 605 } 606 isa_ne2000_init(bus, ne2000_io[nb_ne2k], 607 ne2000_irq[nb_ne2k], nd); 608 nb_ne2k++; 609 return true; 610 } 611 612 void pc_acpi_smi_interrupt(void *opaque, int irq, int level) 613 { 614 X86CPU *cpu = opaque; 615 616 if (level) { 617 cpu_interrupt(CPU(cpu), CPU_INTERRUPT_SMI); 618 } 619 } 620 621 static 622 void pc_machine_done(Notifier *notifier, void *data) 623 { 624 PCMachineState *pcms = container_of(notifier, 625 PCMachineState, machine_done); 626 X86MachineState *x86ms = X86_MACHINE(pcms); 627 628 cxl_hook_up_pxb_registers(pcms->pcibus, &pcms->cxl_devices_state, 629 &error_fatal); 630 631 if (pcms->cxl_devices_state.is_enabled) { 632 cxl_fmws_link_targets(&pcms->cxl_devices_state, &error_fatal); 633 } 634 635 /* set the number of CPUs */ 636 x86_rtc_set_cpus_count(x86ms->rtc, x86ms->boot_cpus); 637 638 pci_bus_add_fw_cfg_extra_pci_roots(x86ms->fw_cfg, pcms->pcibus, 639 &error_abort); 640 641 acpi_setup(); 642 if (x86ms->fw_cfg) { 643 fw_cfg_build_smbios(pcms, x86ms->fw_cfg, pcms->smbios_entry_point_type); 644 fw_cfg_add_e820(x86ms->fw_cfg); 645 fw_cfg_build_feature_control(MACHINE(pcms), x86ms->fw_cfg); 646 /* update FW_CFG_NB_CPUS to account for -device added CPUs */ 647 fw_cfg_modify_i16(x86ms->fw_cfg, FW_CFG_NB_CPUS, x86ms->boot_cpus); 648 } 649 650 pc_cmos_init_late(pcms); 651 } 652 653 /* setup pci memory address space mapping into system address space */ 654 void pc_pci_as_mapping_init(MemoryRegion *system_memory, 655 MemoryRegion *pci_address_space) 656 { 657 /* Set to lower priority than RAM */ 658 memory_region_add_subregion_overlap(system_memory, 0x0, 659 pci_address_space, -1); 660 } 661 662 void xen_load_linux(PCMachineState *pcms) 663 { 664 int i; 665 FWCfgState *fw_cfg; 666 PCMachineClass *pcmc = PC_MACHINE_GET_CLASS(pcms); 667 X86MachineState *x86ms = X86_MACHINE(pcms); 668 669 assert(MACHINE(pcms)->kernel_filename != NULL); 670 671 fw_cfg = fw_cfg_init_io_dma(FW_CFG_IO_BASE, FW_CFG_IO_BASE + 4, 672 &address_space_memory); 673 fw_cfg_add_i16(fw_cfg, FW_CFG_NB_CPUS, x86ms->boot_cpus); 674 rom_set_fw(fw_cfg); 675 676 x86_load_linux(x86ms, fw_cfg, PC_FW_DATA, pcmc->pvh_enabled); 677 for (i = 0; i < nb_option_roms; i++) { 678 assert(!strcmp(option_rom[i].name, "linuxboot.bin") || 679 !strcmp(option_rom[i].name, "linuxboot_dma.bin") || 680 !strcmp(option_rom[i].name, "pvh.bin") || 681 !strcmp(option_rom[i].name, "multiboot.bin") || 682 !strcmp(option_rom[i].name, "multiboot_dma.bin")); 683 rom_add_option(option_rom[i].name, option_rom[i].bootindex); 684 } 685 x86ms->fw_cfg = fw_cfg; 686 } 687 688 #define PC_ROM_MIN_VGA 0xc0000 689 #define PC_ROM_MIN_OPTION 0xc8000 690 #define PC_ROM_MAX 0xe0000 691 #define PC_ROM_ALIGN 0x800 692 #define PC_ROM_SIZE (PC_ROM_MAX - PC_ROM_MIN_VGA) 693 694 static hwaddr pc_above_4g_end(PCMachineState *pcms) 695 { 696 X86MachineState *x86ms = X86_MACHINE(pcms); 697 698 if (pcms->sgx_epc.size != 0) { 699 return sgx_epc_above_4g_end(&pcms->sgx_epc); 700 } 701 702 return x86ms->above_4g_mem_start + x86ms->above_4g_mem_size; 703 } 704 705 static void pc_get_device_memory_range(PCMachineState *pcms, 706 hwaddr *base, 707 ram_addr_t *device_mem_size) 708 { 709 MachineState *machine = MACHINE(pcms); 710 ram_addr_t size; 711 hwaddr addr; 712 713 size = machine->maxram_size - machine->ram_size; 714 addr = ROUND_UP(pc_above_4g_end(pcms), 1 * GiB); 715 716 /* size device region assuming 1G page max alignment per slot */ 717 size += (1 * GiB) * machine->ram_slots; 718 719 *base = addr; 720 *device_mem_size = size; 721 } 722 723 static uint64_t pc_get_cxl_range_start(PCMachineState *pcms) 724 { 725 PCMachineClass *pcmc = PC_MACHINE_GET_CLASS(pcms); 726 MachineState *ms = MACHINE(pcms); 727 hwaddr cxl_base; 728 ram_addr_t size; 729 730 if (pcmc->has_reserved_memory && 731 (ms->ram_size < ms->maxram_size)) { 732 pc_get_device_memory_range(pcms, &cxl_base, &size); 733 cxl_base += size; 734 } else { 735 cxl_base = pc_above_4g_end(pcms); 736 } 737 738 return cxl_base; 739 } 740 741 static uint64_t pc_get_cxl_range_end(PCMachineState *pcms) 742 { 743 uint64_t start = pc_get_cxl_range_start(pcms) + MiB; 744 745 if (pcms->cxl_devices_state.fixed_windows) { 746 GList *it; 747 748 start = ROUND_UP(start, 256 * MiB); 749 for (it = pcms->cxl_devices_state.fixed_windows; it; it = it->next) { 750 CXLFixedWindow *fw = it->data; 751 start += fw->size; 752 } 753 } 754 755 return start; 756 } 757 758 static hwaddr pc_max_used_gpa(PCMachineState *pcms, uint64_t pci_hole64_size) 759 { 760 X86CPU *cpu = X86_CPU(first_cpu); 761 PCMachineClass *pcmc = PC_MACHINE_GET_CLASS(pcms); 762 MachineState *ms = MACHINE(pcms); 763 764 if (cpu->env.features[FEAT_8000_0001_EDX] & CPUID_EXT2_LM) { 765 /* 64-bit systems */ 766 return pc_pci_hole64_start() + pci_hole64_size - 1; 767 } 768 769 /* 32-bit systems */ 770 if (pcmc->broken_32bit_mem_addr_check) { 771 /* old value for compatibility reasons */ 772 return ((hwaddr)1 << cpu->phys_bits) - 1; 773 } 774 775 /* 776 * 32-bit systems don't have hole64 but they might have a region for 777 * memory devices. Even if additional hotplugged memory devices might 778 * not be usable by most guest OSes, we need to still consider them for 779 * calculating the highest possible GPA so that we can properly report 780 * if someone configures them on a CPU that cannot possibly address them. 781 */ 782 if (pcmc->has_reserved_memory && 783 (ms->ram_size < ms->maxram_size)) { 784 hwaddr devmem_start; 785 ram_addr_t devmem_size; 786 787 pc_get_device_memory_range(pcms, &devmem_start, &devmem_size); 788 devmem_start += devmem_size; 789 return devmem_start - 1; 790 } 791 792 /* configuration without any memory hotplug */ 793 return pc_above_4g_end(pcms) - 1; 794 } 795 796 /* 797 * AMD systems with an IOMMU have an additional hole close to the 798 * 1Tb, which are special GPAs that cannot be DMA mapped. Depending 799 * on kernel version, VFIO may or may not let you DMA map those ranges. 800 * Starting Linux v5.4 we validate it, and can't create guests on AMD machines 801 * with certain memory sizes. It's also wrong to use those IOVA ranges 802 * in detriment of leading to IOMMU INVALID_DEVICE_REQUEST or worse. 803 * The ranges reserved for Hyper-Transport are: 804 * 805 * FD_0000_0000h - FF_FFFF_FFFFh 806 * 807 * The ranges represent the following: 808 * 809 * Base Address Top Address Use 810 * 811 * FD_0000_0000h FD_F7FF_FFFFh Reserved interrupt address space 812 * FD_F800_0000h FD_F8FF_FFFFh Interrupt/EOI IntCtl 813 * FD_F900_0000h FD_F90F_FFFFh Legacy PIC IACK 814 * FD_F910_0000h FD_F91F_FFFFh System Management 815 * FD_F920_0000h FD_FAFF_FFFFh Reserved Page Tables 816 * FD_FB00_0000h FD_FBFF_FFFFh Address Translation 817 * FD_FC00_0000h FD_FDFF_FFFFh I/O Space 818 * FD_FE00_0000h FD_FFFF_FFFFh Configuration 819 * FE_0000_0000h FE_1FFF_FFFFh Extended Configuration/Device Messages 820 * FE_2000_0000h FF_FFFF_FFFFh Reserved 821 * 822 * See AMD IOMMU spec, section 2.1.2 "IOMMU Logical Topology", 823 * Table 3: Special Address Controls (GPA) for more information. 824 */ 825 #define AMD_HT_START 0xfd00000000UL 826 #define AMD_HT_END 0xffffffffffUL 827 #define AMD_ABOVE_1TB_START (AMD_HT_END + 1) 828 #define AMD_HT_SIZE (AMD_ABOVE_1TB_START - AMD_HT_START) 829 830 void pc_memory_init(PCMachineState *pcms, 831 MemoryRegion *system_memory, 832 MemoryRegion *rom_memory, 833 uint64_t pci_hole64_size) 834 { 835 int linux_boot, i; 836 MemoryRegion *option_rom_mr; 837 MemoryRegion *ram_below_4g, *ram_above_4g; 838 FWCfgState *fw_cfg; 839 MachineState *machine = MACHINE(pcms); 840 MachineClass *mc = MACHINE_GET_CLASS(machine); 841 PCMachineClass *pcmc = PC_MACHINE_GET_CLASS(pcms); 842 X86MachineState *x86ms = X86_MACHINE(pcms); 843 hwaddr maxphysaddr, maxusedaddr; 844 hwaddr cxl_base, cxl_resv_end = 0; 845 X86CPU *cpu = X86_CPU(first_cpu); 846 847 assert(machine->ram_size == x86ms->below_4g_mem_size + 848 x86ms->above_4g_mem_size); 849 850 linux_boot = (machine->kernel_filename != NULL); 851 852 /* 853 * The HyperTransport range close to the 1T boundary is unique to AMD 854 * hosts with IOMMUs enabled. Restrict the ram-above-4g relocation 855 * to above 1T to AMD vCPUs only. @enforce_amd_1tb_hole is only false in 856 * older machine types (<= 7.0) for compatibility purposes. 857 */ 858 if (IS_AMD_CPU(&cpu->env) && pcmc->enforce_amd_1tb_hole) { 859 /* Bail out if max possible address does not cross HT range */ 860 if (pc_max_used_gpa(pcms, pci_hole64_size) >= AMD_HT_START) { 861 x86ms->above_4g_mem_start = AMD_ABOVE_1TB_START; 862 } 863 864 /* 865 * Advertise the HT region if address space covers the reserved 866 * region or if we relocate. 867 */ 868 if (cpu->phys_bits >= 40) { 869 e820_add_entry(AMD_HT_START, AMD_HT_SIZE, E820_RESERVED); 870 } 871 } 872 873 /* 874 * phys-bits is required to be appropriately configured 875 * to make sure max used GPA is reachable. 876 */ 877 maxusedaddr = pc_max_used_gpa(pcms, pci_hole64_size); 878 maxphysaddr = ((hwaddr)1 << cpu->phys_bits) - 1; 879 if (maxphysaddr < maxusedaddr) { 880 error_report("Address space limit 0x%"PRIx64" < 0x%"PRIx64 881 " phys-bits too low (%u)", 882 maxphysaddr, maxusedaddr, cpu->phys_bits); 883 exit(EXIT_FAILURE); 884 } 885 886 /* 887 * Split single memory region and use aliases to address portions of it, 888 * done for backwards compatibility with older qemus. 889 */ 890 ram_below_4g = g_malloc(sizeof(*ram_below_4g)); 891 memory_region_init_alias(ram_below_4g, NULL, "ram-below-4g", machine->ram, 892 0, x86ms->below_4g_mem_size); 893 memory_region_add_subregion(system_memory, 0, ram_below_4g); 894 e820_add_entry(0, x86ms->below_4g_mem_size, E820_RAM); 895 if (x86ms->above_4g_mem_size > 0) { 896 ram_above_4g = g_malloc(sizeof(*ram_above_4g)); 897 memory_region_init_alias(ram_above_4g, NULL, "ram-above-4g", 898 machine->ram, 899 x86ms->below_4g_mem_size, 900 x86ms->above_4g_mem_size); 901 memory_region_add_subregion(system_memory, x86ms->above_4g_mem_start, 902 ram_above_4g); 903 e820_add_entry(x86ms->above_4g_mem_start, x86ms->above_4g_mem_size, 904 E820_RAM); 905 } 906 907 if (pcms->sgx_epc.size != 0) { 908 e820_add_entry(pcms->sgx_epc.base, pcms->sgx_epc.size, E820_RESERVED); 909 } 910 911 if (!pcmc->has_reserved_memory && 912 (machine->ram_slots || 913 (machine->maxram_size > machine->ram_size))) { 914 915 error_report("\"-memory 'slots|maxmem'\" is not supported by: %s", 916 mc->name); 917 exit(EXIT_FAILURE); 918 } 919 920 /* initialize device memory address space */ 921 if (pcmc->has_reserved_memory && 922 (machine->ram_size < machine->maxram_size)) { 923 ram_addr_t device_mem_size; 924 hwaddr device_mem_base; 925 926 if (machine->ram_slots > ACPI_MAX_RAM_SLOTS) { 927 error_report("unsupported amount of memory slots: %"PRIu64, 928 machine->ram_slots); 929 exit(EXIT_FAILURE); 930 } 931 932 if (QEMU_ALIGN_UP(machine->maxram_size, 933 TARGET_PAGE_SIZE) != machine->maxram_size) { 934 error_report("maximum memory size must by aligned to multiple of " 935 "%d bytes", TARGET_PAGE_SIZE); 936 exit(EXIT_FAILURE); 937 } 938 939 pc_get_device_memory_range(pcms, &device_mem_base, &device_mem_size); 940 941 if (device_mem_base + device_mem_size < device_mem_size) { 942 error_report("unsupported amount of maximum memory: " RAM_ADDR_FMT, 943 machine->maxram_size); 944 exit(EXIT_FAILURE); 945 } 946 machine_memory_devices_init(machine, device_mem_base, device_mem_size); 947 } 948 949 if (pcms->cxl_devices_state.is_enabled) { 950 MemoryRegion *mr = &pcms->cxl_devices_state.host_mr; 951 hwaddr cxl_size = MiB; 952 953 cxl_base = pc_get_cxl_range_start(pcms); 954 memory_region_init(mr, OBJECT(machine), "cxl_host_reg", cxl_size); 955 memory_region_add_subregion(system_memory, cxl_base, mr); 956 cxl_resv_end = cxl_base + cxl_size; 957 if (pcms->cxl_devices_state.fixed_windows) { 958 hwaddr cxl_fmw_base; 959 GList *it; 960 961 cxl_fmw_base = ROUND_UP(cxl_base + cxl_size, 256 * MiB); 962 for (it = pcms->cxl_devices_state.fixed_windows; it; it = it->next) { 963 CXLFixedWindow *fw = it->data; 964 965 fw->base = cxl_fmw_base; 966 memory_region_init_io(&fw->mr, OBJECT(machine), &cfmws_ops, fw, 967 "cxl-fixed-memory-region", fw->size); 968 memory_region_add_subregion(system_memory, fw->base, &fw->mr); 969 cxl_fmw_base += fw->size; 970 cxl_resv_end = cxl_fmw_base; 971 } 972 } 973 } 974 975 /* Initialize PC system firmware */ 976 pc_system_firmware_init(pcms, rom_memory); 977 978 option_rom_mr = g_malloc(sizeof(*option_rom_mr)); 979 if (machine_require_guest_memfd(machine)) { 980 memory_region_init_ram_guest_memfd(option_rom_mr, NULL, "pc.rom", 981 PC_ROM_SIZE, &error_fatal); 982 } else { 983 memory_region_init_ram(option_rom_mr, NULL, "pc.rom", PC_ROM_SIZE, 984 &error_fatal); 985 if (pcmc->pci_enabled) { 986 memory_region_set_readonly(option_rom_mr, true); 987 } 988 } 989 memory_region_add_subregion_overlap(rom_memory, 990 PC_ROM_MIN_VGA, 991 option_rom_mr, 992 1); 993 994 fw_cfg = fw_cfg_arch_create(machine, 995 x86ms->boot_cpus, x86ms->apic_id_limit); 996 997 rom_set_fw(fw_cfg); 998 999 if (machine->device_memory) { 1000 uint64_t *val = g_malloc(sizeof(*val)); 1001 uint64_t res_mem_end = machine->device_memory->base; 1002 1003 if (!pcmc->broken_reserved_end) { 1004 res_mem_end += memory_region_size(&machine->device_memory->mr); 1005 } 1006 1007 if (pcms->cxl_devices_state.is_enabled) { 1008 res_mem_end = cxl_resv_end; 1009 } 1010 *val = cpu_to_le64(ROUND_UP(res_mem_end, 1 * GiB)); 1011 fw_cfg_add_file(fw_cfg, "etc/reserved-memory-end", val, sizeof(*val)); 1012 } 1013 1014 if (linux_boot) { 1015 x86_load_linux(x86ms, fw_cfg, PC_FW_DATA, pcmc->pvh_enabled); 1016 } 1017 1018 for (i = 0; i < nb_option_roms; i++) { 1019 rom_add_option(option_rom[i].name, option_rom[i].bootindex); 1020 } 1021 x86ms->fw_cfg = fw_cfg; 1022 1023 /* Init default IOAPIC address space */ 1024 x86ms->ioapic_as = &address_space_memory; 1025 1026 /* Init ACPI memory hotplug IO base address */ 1027 pcms->memhp_io_base = ACPI_MEMORY_HOTPLUG_BASE; 1028 } 1029 1030 /* 1031 * The 64bit pci hole starts after "above 4G RAM" and 1032 * potentially the space reserved for memory hotplug. 1033 */ 1034 uint64_t pc_pci_hole64_start(void) 1035 { 1036 PCMachineState *pcms = PC_MACHINE(qdev_get_machine()); 1037 PCMachineClass *pcmc = PC_MACHINE_GET_CLASS(pcms); 1038 MachineState *ms = MACHINE(pcms); 1039 uint64_t hole64_start = 0; 1040 ram_addr_t size = 0; 1041 1042 if (pcms->cxl_devices_state.is_enabled) { 1043 hole64_start = pc_get_cxl_range_end(pcms); 1044 } else if (pcmc->has_reserved_memory && (ms->ram_size < ms->maxram_size)) { 1045 pc_get_device_memory_range(pcms, &hole64_start, &size); 1046 if (!pcmc->broken_reserved_end) { 1047 hole64_start += size; 1048 } 1049 } else { 1050 hole64_start = pc_above_4g_end(pcms); 1051 } 1052 1053 return ROUND_UP(hole64_start, 1 * GiB); 1054 } 1055 1056 DeviceState *pc_vga_init(ISABus *isa_bus, PCIBus *pci_bus) 1057 { 1058 DeviceState *dev = NULL; 1059 1060 rom_set_order_override(FW_CFG_ORDER_OVERRIDE_VGA); 1061 if (pci_bus) { 1062 PCIDevice *pcidev = pci_vga_init(pci_bus); 1063 dev = pcidev ? &pcidev->qdev : NULL; 1064 } else if (isa_bus) { 1065 ISADevice *isadev = isa_vga_init(isa_bus); 1066 dev = isadev ? DEVICE(isadev) : NULL; 1067 } 1068 rom_reset_order_override(); 1069 return dev; 1070 } 1071 1072 static const MemoryRegionOps ioport80_io_ops = { 1073 .write = ioport80_write, 1074 .read = ioport80_read, 1075 .endianness = DEVICE_LITTLE_ENDIAN, 1076 .impl = { 1077 .min_access_size = 1, 1078 .max_access_size = 1, 1079 }, 1080 }; 1081 1082 static const MemoryRegionOps ioportF0_io_ops = { 1083 .write = ioportF0_write, 1084 .read = ioportF0_read, 1085 .endianness = DEVICE_LITTLE_ENDIAN, 1086 .impl = { 1087 .min_access_size = 1, 1088 .max_access_size = 1, 1089 }, 1090 }; 1091 1092 static void pc_superio_init(ISABus *isa_bus, bool create_fdctrl, 1093 bool create_i8042, bool no_vmport, Error **errp) 1094 { 1095 int i; 1096 DriveInfo *fd[MAX_FD]; 1097 qemu_irq *a20_line; 1098 ISADevice *i8042, *port92, *vmmouse; 1099 1100 serial_hds_isa_init(isa_bus, 0, MAX_ISA_SERIAL_PORTS); 1101 parallel_hds_isa_init(isa_bus, MAX_PARALLEL_PORTS); 1102 1103 for (i = 0; i < MAX_FD; i++) { 1104 fd[i] = drive_get(IF_FLOPPY, 0, i); 1105 create_fdctrl |= !!fd[i]; 1106 } 1107 if (create_fdctrl) { 1108 #ifdef CONFIG_FDC_ISA 1109 ISADevice *fdc = isa_new(TYPE_ISA_FDC); 1110 if (fdc) { 1111 isa_realize_and_unref(fdc, isa_bus, &error_fatal); 1112 isa_fdc_init_drives(fdc, fd); 1113 } 1114 #endif 1115 } 1116 1117 if (!create_i8042) { 1118 if (!no_vmport) { 1119 error_setg(errp, 1120 "vmport requires the i8042 controller to be enabled"); 1121 } 1122 return; 1123 } 1124 1125 i8042 = isa_create_simple(isa_bus, TYPE_I8042); 1126 if (!no_vmport) { 1127 isa_create_simple(isa_bus, TYPE_VMPORT); 1128 vmmouse = isa_try_new("vmmouse"); 1129 } else { 1130 vmmouse = NULL; 1131 } 1132 if (vmmouse) { 1133 object_property_set_link(OBJECT(vmmouse), TYPE_I8042, OBJECT(i8042), 1134 &error_abort); 1135 isa_realize_and_unref(vmmouse, isa_bus, &error_fatal); 1136 } 1137 port92 = isa_create_simple(isa_bus, TYPE_PORT92); 1138 1139 a20_line = qemu_allocate_irqs(handle_a20_line_change, first_cpu, 2); 1140 qdev_connect_gpio_out_named(DEVICE(i8042), 1141 I8042_A20_LINE, 0, a20_line[0]); 1142 qdev_connect_gpio_out_named(DEVICE(port92), 1143 PORT92_A20_LINE, 0, a20_line[1]); 1144 g_free(a20_line); 1145 } 1146 1147 void pc_basic_device_init(struct PCMachineState *pcms, 1148 ISABus *isa_bus, qemu_irq *gsi, 1149 ISADevice *rtc_state, 1150 bool create_fdctrl, 1151 uint32_t hpet_irqs) 1152 { 1153 int i; 1154 DeviceState *hpet = NULL; 1155 int pit_isa_irq = 0; 1156 qemu_irq pit_alt_irq = NULL; 1157 ISADevice *pit = NULL; 1158 MemoryRegion *ioport80_io = g_new(MemoryRegion, 1); 1159 MemoryRegion *ioportF0_io = g_new(MemoryRegion, 1); 1160 X86MachineState *x86ms = X86_MACHINE(pcms); 1161 1162 memory_region_init_io(ioport80_io, NULL, &ioport80_io_ops, NULL, "ioport80", 1); 1163 memory_region_add_subregion(isa_bus->address_space_io, 0x80, ioport80_io); 1164 1165 memory_region_init_io(ioportF0_io, NULL, &ioportF0_io_ops, NULL, "ioportF0", 1); 1166 memory_region_add_subregion(isa_bus->address_space_io, 0xf0, ioportF0_io); 1167 1168 /* 1169 * Check if an HPET shall be created. 1170 */ 1171 if (pcms->hpet_enabled) { 1172 qemu_irq rtc_irq; 1173 1174 hpet = qdev_try_new(TYPE_HPET); 1175 if (!hpet) { 1176 error_report("couldn't create HPET device"); 1177 exit(1); 1178 } 1179 /* 1180 * For pc-piix-*, hpet's intcap is always IRQ2. For pc-q35-*, 1181 * use IRQ16~23, IRQ8 and IRQ2. If the user has already set 1182 * the property, use whatever mask they specified. 1183 */ 1184 uint8_t compat = object_property_get_uint(OBJECT(hpet), 1185 HPET_INTCAP, NULL); 1186 if (!compat) { 1187 qdev_prop_set_uint32(hpet, HPET_INTCAP, hpet_irqs); 1188 } 1189 sysbus_realize_and_unref(SYS_BUS_DEVICE(hpet), &error_fatal); 1190 sysbus_mmio_map(SYS_BUS_DEVICE(hpet), 0, HPET_BASE); 1191 1192 for (i = 0; i < IOAPIC_NUM_PINS; i++) { 1193 sysbus_connect_irq(SYS_BUS_DEVICE(hpet), i, gsi[i]); 1194 } 1195 pit_isa_irq = -1; 1196 pit_alt_irq = qdev_get_gpio_in(hpet, HPET_LEGACY_PIT_INT); 1197 rtc_irq = qdev_get_gpio_in(hpet, HPET_LEGACY_RTC_INT); 1198 1199 /* overwrite connection created by south bridge */ 1200 qdev_connect_gpio_out(DEVICE(rtc_state), 0, rtc_irq); 1201 } 1202 1203 object_property_add_alias(OBJECT(pcms), "rtc-time", OBJECT(rtc_state), 1204 "date"); 1205 1206 #ifdef CONFIG_XEN_EMU 1207 if (xen_mode == XEN_EMULATE) { 1208 xen_overlay_create(); 1209 xen_evtchn_create(IOAPIC_NUM_PINS, gsi); 1210 xen_gnttab_create(); 1211 xen_xenstore_create(); 1212 if (pcms->pcibus) { 1213 pci_create_simple(pcms->pcibus, -1, "xen-platform"); 1214 } 1215 xen_bus_init(); 1216 } 1217 #endif 1218 1219 qemu_register_boot_set(pc_boot_set, pcms); 1220 set_boot_dev(pcms, MC146818_RTC(rtc_state), 1221 MACHINE(pcms)->boot_config.order, &error_fatal); 1222 1223 if (!xen_enabled() && 1224 (x86ms->pit == ON_OFF_AUTO_AUTO || x86ms->pit == ON_OFF_AUTO_ON)) { 1225 if (kvm_pit_in_kernel()) { 1226 pit = kvm_pit_init(isa_bus, 0x40); 1227 } else { 1228 pit = i8254_pit_init(isa_bus, 0x40, pit_isa_irq, pit_alt_irq); 1229 } 1230 if (hpet) { 1231 /* connect PIT to output control line of the HPET */ 1232 qdev_connect_gpio_out(hpet, 0, qdev_get_gpio_in(DEVICE(pit), 0)); 1233 } 1234 object_property_set_link(OBJECT(pcms->pcspk), "pit", 1235 OBJECT(pit), &error_fatal); 1236 isa_realize_and_unref(pcms->pcspk, isa_bus, &error_fatal); 1237 } 1238 1239 if (pcms->vmport == ON_OFF_AUTO_AUTO) { 1240 pcms->vmport = (xen_enabled() || !pcms->i8042_enabled) 1241 ? ON_OFF_AUTO_OFF : ON_OFF_AUTO_ON; 1242 } 1243 1244 /* Super I/O */ 1245 pc_superio_init(isa_bus, create_fdctrl, pcms->i8042_enabled, 1246 pcms->vmport != ON_OFF_AUTO_ON, &error_fatal); 1247 1248 pcms->machine_done.notify = pc_machine_done; 1249 qemu_add_machine_init_done_notifier(&pcms->machine_done); 1250 } 1251 1252 void pc_nic_init(PCMachineClass *pcmc, ISABus *isa_bus, PCIBus *pci_bus) 1253 { 1254 MachineClass *mc = MACHINE_CLASS(pcmc); 1255 bool default_is_ne2k = g_str_equal(mc->default_nic, TYPE_ISA_NE2000); 1256 NICInfo *nd; 1257 1258 rom_set_order_override(FW_CFG_ORDER_OVERRIDE_NIC); 1259 1260 while ((nd = qemu_find_nic_info(TYPE_ISA_NE2000, default_is_ne2k, NULL))) { 1261 pc_init_ne2k_isa(isa_bus, nd, &error_fatal); 1262 } 1263 1264 /* Anything remaining should be a PCI NIC */ 1265 if (pci_bus) { 1266 pci_init_nic_devices(pci_bus, mc->default_nic); 1267 } 1268 1269 rom_reset_order_override(); 1270 } 1271 1272 void pc_i8259_create(ISABus *isa_bus, qemu_irq *i8259_irqs) 1273 { 1274 qemu_irq *i8259; 1275 1276 if (kvm_pic_in_kernel()) { 1277 i8259 = kvm_i8259_init(isa_bus); 1278 } else if (xen_enabled()) { 1279 i8259 = xen_interrupt_controller_init(); 1280 } else { 1281 i8259 = i8259_init(isa_bus, x86_allocate_cpu_irq()); 1282 } 1283 1284 for (size_t i = 0; i < ISA_NUM_IRQS; i++) { 1285 i8259_irqs[i] = i8259[i]; 1286 } 1287 1288 g_free(i8259); 1289 } 1290 1291 static void pc_memory_pre_plug(HotplugHandler *hotplug_dev, DeviceState *dev, 1292 Error **errp) 1293 { 1294 const X86MachineState *x86ms = X86_MACHINE(hotplug_dev); 1295 const MachineState *ms = MACHINE(hotplug_dev); 1296 const bool is_nvdimm = object_dynamic_cast(OBJECT(dev), TYPE_NVDIMM); 1297 Error *local_err = NULL; 1298 1299 /* 1300 * When "acpi=off" is used with the Q35 machine type, no ACPI is built, 1301 * but pcms->acpi_dev is still created. Check !acpi_enabled in 1302 * addition to cover this case. 1303 */ 1304 if (!x86ms->acpi_dev || !x86_machine_is_acpi_enabled(x86ms)) { 1305 error_setg(errp, 1306 "memory hotplug is not enabled: missing acpi device or acpi disabled"); 1307 return; 1308 } 1309 1310 if (is_nvdimm && !ms->nvdimms_state->is_enabled) { 1311 error_setg(errp, "nvdimm is not enabled: missing 'nvdimm' in '-M'"); 1312 return; 1313 } 1314 1315 hotplug_handler_pre_plug(x86ms->acpi_dev, dev, &local_err); 1316 if (local_err) { 1317 error_propagate(errp, local_err); 1318 return; 1319 } 1320 1321 pc_dimm_pre_plug(PC_DIMM(dev), MACHINE(hotplug_dev), errp); 1322 } 1323 1324 static void pc_memory_plug(HotplugHandler *hotplug_dev, 1325 DeviceState *dev, Error **errp) 1326 { 1327 PCMachineState *pcms = PC_MACHINE(hotplug_dev); 1328 X86MachineState *x86ms = X86_MACHINE(hotplug_dev); 1329 MachineState *ms = MACHINE(hotplug_dev); 1330 bool is_nvdimm = object_dynamic_cast(OBJECT(dev), TYPE_NVDIMM); 1331 1332 pc_dimm_plug(PC_DIMM(dev), MACHINE(pcms)); 1333 1334 if (is_nvdimm) { 1335 nvdimm_plug(ms->nvdimms_state); 1336 } 1337 1338 hotplug_handler_plug(x86ms->acpi_dev, dev, &error_abort); 1339 } 1340 1341 static void pc_memory_unplug_request(HotplugHandler *hotplug_dev, 1342 DeviceState *dev, Error **errp) 1343 { 1344 X86MachineState *x86ms = X86_MACHINE(hotplug_dev); 1345 1346 /* 1347 * When "acpi=off" is used with the Q35 machine type, no ACPI is built, 1348 * but pcms->acpi_dev is still created. Check !acpi_enabled in 1349 * addition to cover this case. 1350 */ 1351 if (!x86ms->acpi_dev || !x86_machine_is_acpi_enabled(x86ms)) { 1352 error_setg(errp, 1353 "memory hotplug is not enabled: missing acpi device or acpi disabled"); 1354 return; 1355 } 1356 1357 if (object_dynamic_cast(OBJECT(dev), TYPE_NVDIMM)) { 1358 error_setg(errp, "nvdimm device hot unplug is not supported yet."); 1359 return; 1360 } 1361 1362 hotplug_handler_unplug_request(x86ms->acpi_dev, dev, 1363 errp); 1364 } 1365 1366 static void pc_memory_unplug(HotplugHandler *hotplug_dev, 1367 DeviceState *dev, Error **errp) 1368 { 1369 PCMachineState *pcms = PC_MACHINE(hotplug_dev); 1370 X86MachineState *x86ms = X86_MACHINE(hotplug_dev); 1371 Error *local_err = NULL; 1372 1373 hotplug_handler_unplug(x86ms->acpi_dev, dev, &local_err); 1374 if (local_err) { 1375 goto out; 1376 } 1377 1378 pc_dimm_unplug(PC_DIMM(dev), MACHINE(pcms)); 1379 qdev_unrealize(dev); 1380 out: 1381 error_propagate(errp, local_err); 1382 } 1383 1384 static void pc_hv_balloon_pre_plug(HotplugHandler *hotplug_dev, 1385 DeviceState *dev, Error **errp) 1386 { 1387 /* The vmbus handler has no hotplug handler; we should never end up here. */ 1388 g_assert(!dev->hotplugged); 1389 memory_device_pre_plug(MEMORY_DEVICE(dev), MACHINE(hotplug_dev), errp); 1390 } 1391 1392 static void pc_hv_balloon_plug(HotplugHandler *hotplug_dev, 1393 DeviceState *dev, Error **errp) 1394 { 1395 memory_device_plug(MEMORY_DEVICE(dev), MACHINE(hotplug_dev)); 1396 } 1397 1398 static void pc_machine_device_pre_plug_cb(HotplugHandler *hotplug_dev, 1399 DeviceState *dev, Error **errp) 1400 { 1401 if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM)) { 1402 pc_memory_pre_plug(hotplug_dev, dev, errp); 1403 } else if (object_dynamic_cast(OBJECT(dev), TYPE_CPU)) { 1404 x86_cpu_pre_plug(hotplug_dev, dev, errp); 1405 } else if (object_dynamic_cast(OBJECT(dev), TYPE_VIRTIO_MD_PCI)) { 1406 virtio_md_pci_pre_plug(VIRTIO_MD_PCI(dev), MACHINE(hotplug_dev), errp); 1407 } else if (object_dynamic_cast(OBJECT(dev), TYPE_VIRTIO_IOMMU_PCI)) { 1408 /* Declare the APIC range as the reserved MSI region */ 1409 char *resv_prop_str = g_strdup_printf("0xfee00000:0xfeefffff:%d", 1410 VIRTIO_IOMMU_RESV_MEM_T_MSI); 1411 QList *reserved_regions = qlist_new(); 1412 1413 qlist_append_str(reserved_regions, resv_prop_str); 1414 qdev_prop_set_array(dev, "reserved-regions", reserved_regions); 1415 1416 g_free(resv_prop_str); 1417 } 1418 1419 if (object_dynamic_cast(OBJECT(dev), TYPE_X86_IOMMU_DEVICE) || 1420 object_dynamic_cast(OBJECT(dev), TYPE_VIRTIO_IOMMU_PCI)) { 1421 PCMachineState *pcms = PC_MACHINE(hotplug_dev); 1422 1423 if (pcms->iommu) { 1424 error_setg(errp, "QEMU does not support multiple vIOMMUs " 1425 "for x86 yet."); 1426 return; 1427 } 1428 pcms->iommu = dev; 1429 } else if (object_dynamic_cast(OBJECT(dev), TYPE_HV_BALLOON)) { 1430 pc_hv_balloon_pre_plug(hotplug_dev, dev, errp); 1431 } 1432 } 1433 1434 static void pc_machine_device_plug_cb(HotplugHandler *hotplug_dev, 1435 DeviceState *dev, Error **errp) 1436 { 1437 if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM)) { 1438 pc_memory_plug(hotplug_dev, dev, errp); 1439 } else if (object_dynamic_cast(OBJECT(dev), TYPE_CPU)) { 1440 x86_cpu_plug(hotplug_dev, dev, errp); 1441 } else if (object_dynamic_cast(OBJECT(dev), TYPE_VIRTIO_MD_PCI)) { 1442 virtio_md_pci_plug(VIRTIO_MD_PCI(dev), MACHINE(hotplug_dev), errp); 1443 } else if (object_dynamic_cast(OBJECT(dev), TYPE_HV_BALLOON)) { 1444 pc_hv_balloon_plug(hotplug_dev, dev, errp); 1445 } 1446 } 1447 1448 static void pc_machine_device_unplug_request_cb(HotplugHandler *hotplug_dev, 1449 DeviceState *dev, Error **errp) 1450 { 1451 if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM)) { 1452 pc_memory_unplug_request(hotplug_dev, dev, errp); 1453 } else if (object_dynamic_cast(OBJECT(dev), TYPE_CPU)) { 1454 x86_cpu_unplug_request_cb(hotplug_dev, dev, errp); 1455 } else if (object_dynamic_cast(OBJECT(dev), TYPE_VIRTIO_MD_PCI)) { 1456 virtio_md_pci_unplug_request(VIRTIO_MD_PCI(dev), MACHINE(hotplug_dev), 1457 errp); 1458 } else { 1459 error_setg(errp, "acpi: device unplug request for not supported device" 1460 " type: %s", object_get_typename(OBJECT(dev))); 1461 } 1462 } 1463 1464 static void pc_machine_device_unplug_cb(HotplugHandler *hotplug_dev, 1465 DeviceState *dev, Error **errp) 1466 { 1467 if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM)) { 1468 pc_memory_unplug(hotplug_dev, dev, errp); 1469 } else if (object_dynamic_cast(OBJECT(dev), TYPE_CPU)) { 1470 x86_cpu_unplug_cb(hotplug_dev, dev, errp); 1471 } else if (object_dynamic_cast(OBJECT(dev), TYPE_VIRTIO_MD_PCI)) { 1472 virtio_md_pci_unplug(VIRTIO_MD_PCI(dev), MACHINE(hotplug_dev), errp); 1473 } else { 1474 error_setg(errp, "acpi: device unplug for not supported device" 1475 " type: %s", object_get_typename(OBJECT(dev))); 1476 } 1477 } 1478 1479 static HotplugHandler *pc_get_hotplug_handler(MachineState *machine, 1480 DeviceState *dev) 1481 { 1482 if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM) || 1483 object_dynamic_cast(OBJECT(dev), TYPE_CPU) || 1484 object_dynamic_cast(OBJECT(dev), TYPE_VIRTIO_MD_PCI) || 1485 object_dynamic_cast(OBJECT(dev), TYPE_VIRTIO_IOMMU_PCI) || 1486 object_dynamic_cast(OBJECT(dev), TYPE_HV_BALLOON) || 1487 object_dynamic_cast(OBJECT(dev), TYPE_X86_IOMMU_DEVICE)) { 1488 return HOTPLUG_HANDLER(machine); 1489 } 1490 1491 return NULL; 1492 } 1493 1494 static void pc_machine_get_vmport(Object *obj, Visitor *v, const char *name, 1495 void *opaque, Error **errp) 1496 { 1497 PCMachineState *pcms = PC_MACHINE(obj); 1498 OnOffAuto vmport = pcms->vmport; 1499 1500 visit_type_OnOffAuto(v, name, &vmport, errp); 1501 } 1502 1503 static void pc_machine_set_vmport(Object *obj, Visitor *v, const char *name, 1504 void *opaque, Error **errp) 1505 { 1506 PCMachineState *pcms = PC_MACHINE(obj); 1507 1508 visit_type_OnOffAuto(v, name, &pcms->vmport, errp); 1509 } 1510 1511 static bool pc_machine_get_fd_bootchk(Object *obj, Error **errp) 1512 { 1513 PCMachineState *pcms = PC_MACHINE(obj); 1514 1515 return pcms->fd_bootchk; 1516 } 1517 1518 static void pc_machine_set_fd_bootchk(Object *obj, bool value, Error **errp) 1519 { 1520 PCMachineState *pcms = PC_MACHINE(obj); 1521 1522 pcms->fd_bootchk = value; 1523 } 1524 1525 static bool pc_machine_get_smbus(Object *obj, Error **errp) 1526 { 1527 PCMachineState *pcms = PC_MACHINE(obj); 1528 1529 return pcms->smbus_enabled; 1530 } 1531 1532 static void pc_machine_set_smbus(Object *obj, bool value, Error **errp) 1533 { 1534 PCMachineState *pcms = PC_MACHINE(obj); 1535 1536 pcms->smbus_enabled = value; 1537 } 1538 1539 static bool pc_machine_get_sata(Object *obj, Error **errp) 1540 { 1541 PCMachineState *pcms = PC_MACHINE(obj); 1542 1543 return pcms->sata_enabled; 1544 } 1545 1546 static void pc_machine_set_sata(Object *obj, bool value, Error **errp) 1547 { 1548 PCMachineState *pcms = PC_MACHINE(obj); 1549 1550 pcms->sata_enabled = value; 1551 } 1552 1553 static bool pc_machine_get_hpet(Object *obj, Error **errp) 1554 { 1555 PCMachineState *pcms = PC_MACHINE(obj); 1556 1557 return pcms->hpet_enabled; 1558 } 1559 1560 static void pc_machine_set_hpet(Object *obj, bool value, Error **errp) 1561 { 1562 PCMachineState *pcms = PC_MACHINE(obj); 1563 1564 pcms->hpet_enabled = value; 1565 } 1566 1567 static bool pc_machine_get_i8042(Object *obj, Error **errp) 1568 { 1569 PCMachineState *pcms = PC_MACHINE(obj); 1570 1571 return pcms->i8042_enabled; 1572 } 1573 1574 static void pc_machine_set_i8042(Object *obj, bool value, Error **errp) 1575 { 1576 PCMachineState *pcms = PC_MACHINE(obj); 1577 1578 pcms->i8042_enabled = value; 1579 } 1580 1581 static bool pc_machine_get_default_bus_bypass_iommu(Object *obj, Error **errp) 1582 { 1583 PCMachineState *pcms = PC_MACHINE(obj); 1584 1585 return pcms->default_bus_bypass_iommu; 1586 } 1587 1588 static void pc_machine_set_default_bus_bypass_iommu(Object *obj, bool value, 1589 Error **errp) 1590 { 1591 PCMachineState *pcms = PC_MACHINE(obj); 1592 1593 pcms->default_bus_bypass_iommu = value; 1594 } 1595 1596 static void pc_machine_get_smbios_ep(Object *obj, Visitor *v, const char *name, 1597 void *opaque, Error **errp) 1598 { 1599 PCMachineState *pcms = PC_MACHINE(obj); 1600 SmbiosEntryPointType smbios_entry_point_type = pcms->smbios_entry_point_type; 1601 1602 visit_type_SmbiosEntryPointType(v, name, &smbios_entry_point_type, errp); 1603 } 1604 1605 static void pc_machine_set_smbios_ep(Object *obj, Visitor *v, const char *name, 1606 void *opaque, Error **errp) 1607 { 1608 PCMachineState *pcms = PC_MACHINE(obj); 1609 1610 visit_type_SmbiosEntryPointType(v, name, &pcms->smbios_entry_point_type, errp); 1611 } 1612 1613 static void pc_machine_get_max_ram_below_4g(Object *obj, Visitor *v, 1614 const char *name, void *opaque, 1615 Error **errp) 1616 { 1617 PCMachineState *pcms = PC_MACHINE(obj); 1618 uint64_t value = pcms->max_ram_below_4g; 1619 1620 visit_type_size(v, name, &value, errp); 1621 } 1622 1623 static void pc_machine_set_max_ram_below_4g(Object *obj, Visitor *v, 1624 const char *name, void *opaque, 1625 Error **errp) 1626 { 1627 PCMachineState *pcms = PC_MACHINE(obj); 1628 uint64_t value; 1629 1630 if (!visit_type_size(v, name, &value, errp)) { 1631 return; 1632 } 1633 if (value > 4 * GiB) { 1634 error_setg(errp, 1635 "Machine option 'max-ram-below-4g=%"PRIu64 1636 "' expects size less than or equal to 4G", value); 1637 return; 1638 } 1639 1640 if (value < 1 * MiB) { 1641 warn_report("Only %" PRIu64 " bytes of RAM below the 4GiB boundary," 1642 "BIOS may not work with less than 1MiB", value); 1643 } 1644 1645 pcms->max_ram_below_4g = value; 1646 } 1647 1648 static void pc_machine_get_max_fw_size(Object *obj, Visitor *v, 1649 const char *name, void *opaque, 1650 Error **errp) 1651 { 1652 PCMachineState *pcms = PC_MACHINE(obj); 1653 uint64_t value = pcms->max_fw_size; 1654 1655 visit_type_size(v, name, &value, errp); 1656 } 1657 1658 static void pc_machine_set_max_fw_size(Object *obj, Visitor *v, 1659 const char *name, void *opaque, 1660 Error **errp) 1661 { 1662 PCMachineState *pcms = PC_MACHINE(obj); 1663 uint64_t value; 1664 1665 if (!visit_type_size(v, name, &value, errp)) { 1666 return; 1667 } 1668 1669 /* 1670 * We don't have a theoretically justifiable exact lower bound on the base 1671 * address of any flash mapping. In practice, the IO-APIC MMIO range is 1672 * [0xFEE00000..0xFEE01000] -- see IO_APIC_DEFAULT_ADDRESS --, leaving free 1673 * only 18MiB-4KiB below 4GiB. For now, restrict the cumulative mapping to 1674 * 16MiB in size. 1675 */ 1676 if (value > 16 * MiB) { 1677 error_setg(errp, 1678 "User specified max allowed firmware size %" PRIu64 " is " 1679 "greater than 16MiB. If combined firmware size exceeds " 1680 "16MiB the system may not boot, or experience intermittent" 1681 "stability issues.", 1682 value); 1683 return; 1684 } 1685 1686 pcms->max_fw_size = value; 1687 } 1688 1689 1690 static void pc_machine_initfn(Object *obj) 1691 { 1692 PCMachineState *pcms = PC_MACHINE(obj); 1693 PCMachineClass *pcmc = PC_MACHINE_GET_CLASS(pcms); 1694 1695 #ifdef CONFIG_VMPORT 1696 pcms->vmport = ON_OFF_AUTO_AUTO; 1697 #else 1698 pcms->vmport = ON_OFF_AUTO_OFF; 1699 #endif /* CONFIG_VMPORT */ 1700 pcms->max_ram_below_4g = 0; /* use default */ 1701 pcms->smbios_entry_point_type = pcmc->default_smbios_ep_type; 1702 pcms->south_bridge = pcmc->default_south_bridge; 1703 1704 /* acpi build is enabled by default if machine supports it */ 1705 pcms->acpi_build_enabled = pcmc->has_acpi_build; 1706 pcms->smbus_enabled = true; 1707 pcms->sata_enabled = true; 1708 pcms->i8042_enabled = true; 1709 pcms->max_fw_size = 8 * MiB; 1710 #if defined(CONFIG_HPET) 1711 pcms->hpet_enabled = true; 1712 #endif 1713 pcms->fd_bootchk = true; 1714 pcms->default_bus_bypass_iommu = false; 1715 1716 pc_system_flash_create(pcms); 1717 pcms->pcspk = isa_new(TYPE_PC_SPEAKER); 1718 object_property_add_alias(OBJECT(pcms), "pcspk-audiodev", 1719 OBJECT(pcms->pcspk), "audiodev"); 1720 if (pcmc->pci_enabled) { 1721 cxl_machine_init(obj, &pcms->cxl_devices_state); 1722 } 1723 } 1724 1725 static void pc_machine_reset(MachineState *machine, ResetType type) 1726 { 1727 CPUState *cs; 1728 X86CPU *cpu; 1729 1730 qemu_devices_reset(type); 1731 1732 /* Reset APIC after devices have been reset to cancel 1733 * any changes that qemu_devices_reset() might have done. 1734 */ 1735 CPU_FOREACH(cs) { 1736 cpu = X86_CPU(cs); 1737 1738 x86_cpu_after_reset(cpu); 1739 } 1740 } 1741 1742 static void pc_machine_wakeup(MachineState *machine) 1743 { 1744 cpu_synchronize_all_states(); 1745 pc_machine_reset(machine, RESET_TYPE_WAKEUP); 1746 cpu_synchronize_all_post_reset(); 1747 } 1748 1749 static bool pc_hotplug_allowed(MachineState *ms, DeviceState *dev, Error **errp) 1750 { 1751 X86IOMMUState *iommu = x86_iommu_get_default(); 1752 IntelIOMMUState *intel_iommu; 1753 1754 if (iommu && 1755 object_dynamic_cast((Object *)iommu, TYPE_INTEL_IOMMU_DEVICE) && 1756 object_dynamic_cast((Object *)dev, "vfio-pci")) { 1757 intel_iommu = INTEL_IOMMU_DEVICE(iommu); 1758 if (!intel_iommu->caching_mode) { 1759 error_setg(errp, "Device assignment is not allowed without " 1760 "enabling caching-mode=on for Intel IOMMU."); 1761 return false; 1762 } 1763 } 1764 1765 return true; 1766 } 1767 1768 static void pc_machine_class_init(ObjectClass *oc, void *data) 1769 { 1770 MachineClass *mc = MACHINE_CLASS(oc); 1771 X86MachineClass *x86mc = X86_MACHINE_CLASS(oc); 1772 PCMachineClass *pcmc = PC_MACHINE_CLASS(oc); 1773 HotplugHandlerClass *hc = HOTPLUG_HANDLER_CLASS(oc); 1774 1775 pcmc->pci_enabled = true; 1776 pcmc->has_acpi_build = true; 1777 pcmc->smbios_defaults = true; 1778 pcmc->gigabyte_align = true; 1779 pcmc->has_reserved_memory = true; 1780 pcmc->enforce_amd_1tb_hole = true; 1781 pcmc->isa_bios_alias = true; 1782 pcmc->pvh_enabled = true; 1783 pcmc->kvmclock_create_always = true; 1784 x86mc->apic_xrupt_override = true; 1785 assert(!mc->get_hotplug_handler); 1786 mc->get_hotplug_handler = pc_get_hotplug_handler; 1787 mc->hotplug_allowed = pc_hotplug_allowed; 1788 mc->auto_enable_numa_with_memhp = true; 1789 mc->auto_enable_numa_with_memdev = true; 1790 mc->has_hotpluggable_cpus = true; 1791 mc->default_boot_order = "cad"; 1792 mc->block_default_type = IF_IDE; 1793 mc->max_cpus = 255; 1794 mc->reset = pc_machine_reset; 1795 mc->wakeup = pc_machine_wakeup; 1796 hc->pre_plug = pc_machine_device_pre_plug_cb; 1797 hc->plug = pc_machine_device_plug_cb; 1798 hc->unplug_request = pc_machine_device_unplug_request_cb; 1799 hc->unplug = pc_machine_device_unplug_cb; 1800 mc->default_cpu_type = TARGET_DEFAULT_CPU_TYPE; 1801 mc->nvdimm_supported = true; 1802 mc->smp_props.dies_supported = true; 1803 mc->smp_props.modules_supported = true; 1804 mc->smp_props.cache_supported[CACHE_LEVEL_AND_TYPE_L1D] = true; 1805 mc->smp_props.cache_supported[CACHE_LEVEL_AND_TYPE_L1I] = true; 1806 mc->smp_props.cache_supported[CACHE_LEVEL_AND_TYPE_L2] = true; 1807 mc->smp_props.cache_supported[CACHE_LEVEL_AND_TYPE_L3] = true; 1808 mc->default_ram_id = "pc.ram"; 1809 pcmc->default_smbios_ep_type = SMBIOS_ENTRY_POINT_TYPE_AUTO; 1810 1811 object_class_property_add(oc, PC_MACHINE_MAX_RAM_BELOW_4G, "size", 1812 pc_machine_get_max_ram_below_4g, pc_machine_set_max_ram_below_4g, 1813 NULL, NULL); 1814 object_class_property_set_description(oc, PC_MACHINE_MAX_RAM_BELOW_4G, 1815 "Maximum ram below the 4G boundary (32bit boundary)"); 1816 1817 object_class_property_add(oc, PC_MACHINE_VMPORT, "OnOffAuto", 1818 pc_machine_get_vmport, pc_machine_set_vmport, 1819 NULL, NULL); 1820 object_class_property_set_description(oc, PC_MACHINE_VMPORT, 1821 "Enable vmport (pc & q35)"); 1822 1823 object_class_property_add_bool(oc, PC_MACHINE_SMBUS, 1824 pc_machine_get_smbus, pc_machine_set_smbus); 1825 object_class_property_set_description(oc, PC_MACHINE_SMBUS, 1826 "Enable/disable system management bus"); 1827 1828 object_class_property_add_bool(oc, PC_MACHINE_SATA, 1829 pc_machine_get_sata, pc_machine_set_sata); 1830 object_class_property_set_description(oc, PC_MACHINE_SATA, 1831 "Enable/disable Serial ATA bus"); 1832 1833 object_class_property_add_bool(oc, "hpet", 1834 pc_machine_get_hpet, pc_machine_set_hpet); 1835 object_class_property_set_description(oc, "hpet", 1836 "Enable/disable high precision event timer emulation"); 1837 1838 object_class_property_add_bool(oc, PC_MACHINE_I8042, 1839 pc_machine_get_i8042, pc_machine_set_i8042); 1840 object_class_property_set_description(oc, PC_MACHINE_I8042, 1841 "Enable/disable Intel 8042 PS/2 controller emulation"); 1842 1843 object_class_property_add_bool(oc, "default-bus-bypass-iommu", 1844 pc_machine_get_default_bus_bypass_iommu, 1845 pc_machine_set_default_bus_bypass_iommu); 1846 1847 object_class_property_add(oc, PC_MACHINE_MAX_FW_SIZE, "size", 1848 pc_machine_get_max_fw_size, pc_machine_set_max_fw_size, 1849 NULL, NULL); 1850 object_class_property_set_description(oc, PC_MACHINE_MAX_FW_SIZE, 1851 "Maximum combined firmware size"); 1852 1853 object_class_property_add(oc, PC_MACHINE_SMBIOS_EP, "str", 1854 pc_machine_get_smbios_ep, pc_machine_set_smbios_ep, 1855 NULL, NULL); 1856 object_class_property_set_description(oc, PC_MACHINE_SMBIOS_EP, 1857 "SMBIOS Entry Point type [32, 64]"); 1858 1859 object_class_property_add_bool(oc, "fd-bootchk", 1860 pc_machine_get_fd_bootchk, 1861 pc_machine_set_fd_bootchk); 1862 } 1863 1864 static const TypeInfo pc_machine_info = { 1865 .name = TYPE_PC_MACHINE, 1866 .parent = TYPE_X86_MACHINE, 1867 .abstract = true, 1868 .instance_size = sizeof(PCMachineState), 1869 .instance_init = pc_machine_initfn, 1870 .class_size = sizeof(PCMachineClass), 1871 .class_init = pc_machine_class_init, 1872 .interfaces = (InterfaceInfo[]) { 1873 { TYPE_HOTPLUG_HANDLER }, 1874 { } 1875 }, 1876 }; 1877 1878 static void pc_machine_register_types(void) 1879 { 1880 type_register_static(&pc_machine_info); 1881 } 1882 1883 type_init(pc_machine_register_types) 1884