1 /* 2 * KVM in-kernel APIC support 3 * 4 * Copyright (c) 2011 Siemens AG 5 * 6 * Authors: 7 * Jan Kiszka <jan.kiszka@siemens.com> 8 * 9 * This work is licensed under the terms of the GNU GPL version 2. 10 * See the COPYING file in the top-level directory. 11 */ 12 13 #include "qemu/osdep.h" 14 #include "qemu/module.h" 15 #include "hw/i386/apic_internal.h" 16 #include "hw/pci/msi.h" 17 #include "system/hw_accel.h" 18 #include "system/kvm.h" 19 #include "kvm/kvm_i386.h" 20 #include "kvm/tdx.h" 21 22 static inline void kvm_apic_set_reg(struct kvm_lapic_state *kapic, 23 int reg_id, uint32_t val) 24 { 25 *((uint32_t *)(kapic->regs + (reg_id << 4))) = val; 26 } 27 28 static inline uint32_t kvm_apic_get_reg(struct kvm_lapic_state *kapic, 29 int reg_id) 30 { 31 return *((uint32_t *)(kapic->regs + (reg_id << 4))); 32 } 33 34 static void kvm_put_apic_state(APICCommonState *s, struct kvm_lapic_state *kapic) 35 { 36 int i; 37 38 memset(kapic, 0, sizeof(*kapic)); 39 if (kvm_has_x2apic_api() && s->apicbase & MSR_IA32_APICBASE_EXTD) { 40 kvm_apic_set_reg(kapic, 0x2, s->initial_apic_id); 41 } else { 42 kvm_apic_set_reg(kapic, 0x2, s->id << 24); 43 } 44 kvm_apic_set_reg(kapic, 0x8, s->tpr); 45 kvm_apic_set_reg(kapic, 0xd, s->log_dest << 24); 46 kvm_apic_set_reg(kapic, 0xe, s->dest_mode << 28 | 0x0fffffff); 47 kvm_apic_set_reg(kapic, 0xf, s->spurious_vec); 48 for (i = 0; i < 8; i++) { 49 kvm_apic_set_reg(kapic, 0x10 + i, s->isr[i]); 50 kvm_apic_set_reg(kapic, 0x18 + i, s->tmr[i]); 51 kvm_apic_set_reg(kapic, 0x20 + i, s->irr[i]); 52 } 53 kvm_apic_set_reg(kapic, 0x28, s->esr); 54 kvm_apic_set_reg(kapic, 0x30, s->icr[0]); 55 kvm_apic_set_reg(kapic, 0x31, s->icr[1]); 56 for (i = 0; i < APIC_LVT_NB; i++) { 57 kvm_apic_set_reg(kapic, 0x32 + i, s->lvt[i]); 58 } 59 kvm_apic_set_reg(kapic, 0x38, s->initial_count); 60 kvm_apic_set_reg(kapic, 0x3e, s->divide_conf); 61 } 62 63 void kvm_get_apic_state(DeviceState *dev, struct kvm_lapic_state *kapic) 64 { 65 APICCommonState *s = APIC_COMMON(dev); 66 int i, v; 67 68 if (kvm_has_x2apic_api() && s->apicbase & MSR_IA32_APICBASE_EXTD) { 69 assert(kvm_apic_get_reg(kapic, 0x2) == s->initial_apic_id); 70 } else { 71 s->id = kvm_apic_get_reg(kapic, 0x2) >> 24; 72 } 73 s->tpr = kvm_apic_get_reg(kapic, 0x8); 74 s->arb_id = kvm_apic_get_reg(kapic, 0x9); 75 s->log_dest = kvm_apic_get_reg(kapic, 0xd) >> 24; 76 s->dest_mode = kvm_apic_get_reg(kapic, 0xe) >> 28; 77 s->spurious_vec = kvm_apic_get_reg(kapic, 0xf); 78 for (i = 0; i < 8; i++) { 79 s->isr[i] = kvm_apic_get_reg(kapic, 0x10 + i); 80 s->tmr[i] = kvm_apic_get_reg(kapic, 0x18 + i); 81 s->irr[i] = kvm_apic_get_reg(kapic, 0x20 + i); 82 } 83 s->esr = kvm_apic_get_reg(kapic, 0x28); 84 s->icr[0] = kvm_apic_get_reg(kapic, 0x30); 85 s->icr[1] = kvm_apic_get_reg(kapic, 0x31); 86 for (i = 0; i < APIC_LVT_NB; i++) { 87 s->lvt[i] = kvm_apic_get_reg(kapic, 0x32 + i); 88 } 89 s->initial_count = kvm_apic_get_reg(kapic, 0x38); 90 s->divide_conf = kvm_apic_get_reg(kapic, 0x3e); 91 92 v = (s->divide_conf & 3) | ((s->divide_conf >> 1) & 4); 93 s->count_shift = (v + 1) & 7; 94 95 s->initial_count_load_time = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL); 96 apic_next_timer(s, s->initial_count_load_time); 97 } 98 99 static int kvm_apic_set_base(APICCommonState *s, uint64_t val) 100 { 101 s->apicbase = val; 102 return 0; 103 } 104 105 static void kvm_apic_set_tpr(APICCommonState *s, uint8_t val) 106 { 107 s->tpr = (val & 0x0f) << 4; 108 } 109 110 static uint8_t kvm_apic_get_tpr(APICCommonState *s) 111 { 112 return s->tpr >> 4; 113 } 114 115 static void kvm_apic_enable_tpr_reporting(APICCommonState *s, bool enable) 116 { 117 struct kvm_tpr_access_ctl ctl = { 118 .enabled = enable 119 }; 120 121 kvm_vcpu_ioctl(CPU(s->cpu), KVM_TPR_ACCESS_REPORTING, &ctl); 122 } 123 124 static void kvm_apic_vapic_base_update(APICCommonState *s) 125 { 126 struct kvm_vapic_addr vapid_addr = { 127 .vapic_addr = s->vapic_paddr, 128 }; 129 int ret; 130 131 ret = kvm_vcpu_ioctl(CPU(s->cpu), KVM_SET_VAPIC_ADDR, &vapid_addr); 132 if (ret < 0) { 133 fprintf(stderr, "KVM: setting VAPIC address failed (%s)\n", 134 strerror(-ret)); 135 abort(); 136 } 137 } 138 139 static void kvm_apic_put(CPUState *cs, run_on_cpu_data data) 140 { 141 APICCommonState *s = data.host_ptr; 142 struct kvm_lapic_state kapic; 143 int ret; 144 145 if (is_tdx_vm()) { 146 return; 147 } 148 149 kvm_put_apicbase(s->cpu, s->apicbase); 150 kvm_put_apic_state(s, &kapic); 151 152 ret = kvm_vcpu_ioctl(CPU(s->cpu), KVM_SET_LAPIC, &kapic); 153 if (ret < 0) { 154 fprintf(stderr, "KVM_SET_LAPIC failed: %s\n", strerror(-ret)); 155 abort(); 156 } 157 } 158 159 static void kvm_apic_post_load(APICCommonState *s) 160 { 161 run_on_cpu(CPU(s->cpu), kvm_apic_put, RUN_ON_CPU_HOST_PTR(s)); 162 } 163 164 static void do_inject_external_nmi(CPUState *cpu, run_on_cpu_data data) 165 { 166 APICCommonState *s = data.host_ptr; 167 uint32_t lvt; 168 int ret; 169 170 cpu_synchronize_state(cpu); 171 172 lvt = s->lvt[APIC_LVT_LINT1]; 173 if (!(lvt & APIC_LVT_MASKED) && ((lvt >> 8) & 7) == APIC_DM_NMI) { 174 ret = kvm_vcpu_ioctl(cpu, KVM_NMI); 175 if (ret < 0) { 176 fprintf(stderr, "KVM: injection failed, NMI lost (%s)\n", 177 strerror(-ret)); 178 } 179 } 180 } 181 182 static void kvm_apic_external_nmi(APICCommonState *s) 183 { 184 run_on_cpu(CPU(s->cpu), do_inject_external_nmi, RUN_ON_CPU_HOST_PTR(s)); 185 } 186 187 static void kvm_send_msi(MSIMessage *msg) 188 { 189 int ret; 190 191 /* 192 * The message has already passed through interrupt remapping if enabled, 193 * but the legacy extended destination ID in low bits still needs to be 194 * handled. 195 */ 196 msg->address = kvm_swizzle_msi_ext_dest_id(msg->address); 197 198 ret = kvm_irqchip_send_msi(kvm_state, *msg); 199 if (ret < 0) { 200 fprintf(stderr, "KVM: injection failed, MSI lost (%s)\n", 201 strerror(-ret)); 202 } 203 } 204 205 static uint64_t kvm_apic_mem_read(void *opaque, hwaddr addr, 206 unsigned size) 207 { 208 return ~(uint64_t)0; 209 } 210 211 static void kvm_apic_mem_write(void *opaque, hwaddr addr, 212 uint64_t data, unsigned size) 213 { 214 MSIMessage msg = { .address = addr, .data = data }; 215 216 kvm_send_msi(&msg); 217 } 218 219 static const MemoryRegionOps kvm_apic_io_ops = { 220 .read = kvm_apic_mem_read, 221 .write = kvm_apic_mem_write, 222 .endianness = DEVICE_LITTLE_ENDIAN, 223 }; 224 225 static void kvm_apic_reset(APICCommonState *s) 226 { 227 /* Not used by KVM, which uses the CPU mp_state instead. */ 228 s->wait_for_sipi = 0; 229 230 run_on_cpu(CPU(s->cpu), kvm_apic_put, RUN_ON_CPU_HOST_PTR(s)); 231 } 232 233 static void kvm_apic_realize(DeviceState *dev, Error **errp) 234 { 235 APICCommonState *s = APIC_COMMON(dev); 236 237 memory_region_init_io(&s->io_memory, OBJECT(s), &kvm_apic_io_ops, s, 238 "kvm-apic-msi", APIC_SPACE_SIZE); 239 240 assert(kvm_has_gsi_routing()); 241 msi_nonbroken = true; 242 } 243 244 static void kvm_apic_unrealize(DeviceState *dev) 245 { 246 } 247 248 static void kvm_apic_class_init(ObjectClass *klass, const void *data) 249 { 250 APICCommonClass *k = APIC_COMMON_CLASS(klass); 251 252 k->realize = kvm_apic_realize; 253 k->unrealize = kvm_apic_unrealize; 254 k->reset = kvm_apic_reset; 255 k->set_base = kvm_apic_set_base; 256 k->set_tpr = kvm_apic_set_tpr; 257 k->get_tpr = kvm_apic_get_tpr; 258 k->post_load = kvm_apic_post_load; 259 k->enable_tpr_reporting = kvm_apic_enable_tpr_reporting; 260 k->vapic_base_update = kvm_apic_vapic_base_update; 261 k->external_nmi = kvm_apic_external_nmi; 262 k->send_msi = kvm_send_msi; 263 } 264 265 static const TypeInfo kvm_apic_info = { 266 .name = "kvm-apic", 267 .parent = TYPE_APIC_COMMON, 268 .instance_size = sizeof(APICCommonState), 269 .class_init = kvm_apic_class_init, 270 }; 271 272 static void kvm_apic_register_types(void) 273 { 274 type_register_static(&kvm_apic_info); 275 } 276 277 type_init(kvm_apic_register_types) 278